DS1707/DS1708 3.3 and 5.0-Volt MicroMonitor www.dalsemi.com FEATURES PIN ASSIGNMENT Holds microprocessor in check during power transients Automatically restarts microprocessor after power failure Monitors pushbutton for external override Accurate 5%, 10% or 20% resets for 3.3V systems and 5% or 10% resets for 5.0V systems Eliminates the need for discrete components 20% tolerance compatible with 3.0V systems Pin compatible with the MAXIM MAX707/MAX708 in 8-pin DIP, 8-pin SOIC packages 8-pin DIP, 8-pin and µ-SOP SOIC and 8-pin µ-SOP packages available Industrial temperature range -40°C to +85°C PBRST 1 8 RST VCC 2 7 RST GND 3 6 NC IN 4 5 NMI 8-Pin DIP (300-mil) PBRST 1 8 RST VCC 2 7 RST GND 3 6 NC IN 4 5 NMI 8-Pin SOIC (150-mil) RST RST PBRST VCC 1 2 3 4 8 7 6 5 NC NMI IN GND 8-Pin µ-SOP (118-mil) See Mech. Drawings Section DS1707 and DS1708_R/S/T PIN DESCRIPTION PBRST VCC GND IN NMI NC RST RST - Pushbutton Reset Input - Power Supply - Ground - Input - Non-maskable Interrupt - No Connect - Active Low Reset Output - Active High Reset Output DESCRIPTION The DS1707/DS1708 3.3- or 5.0-Volt MicroMonitor monitors three vital conditions for a microprocessor: power supply, voltage sense, and external override. A precision temperature-compensated reference and comparator circuit monitor the status of VCC at the device and at an upstream point for maximum protection. When the sense input detects an out-of-tolerance condition a non-maskable interrupt is generated. As the voltage at the device degrades an internal power fail signal is generated which forces the reset to an active state. When VCC returns to an in-tolerance condition, the reset signal is kept in the active state for a minimum of 130 ms to allow the power supply and processor to stabilize. 1 of 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 071700 DS1707/DS1708 The third function the DS1707/DS1708 performs is pushbutton reset control. The DS1707/DS1708 debounces the pushbutton input and guarantees an active reset pulse width of 130 ms minimum. OPERATION Power Monitor The DS1707/DS1708 detects out-of-tolerance power supply conditions and warns a processor-based system of impending power failure. When VCC falls below the minimum VCC tolerance, a comparator outputs the RST and RST signals. RST and RST are excellent control signals for a microprocessor, as processing is stopped at the last possible moment of valid VCC. On power-up, RST and RST are kept active for a minimum of 130 ms to allow the power supply and processor to stabilize. Pushbutton Reset The DS1707/DS1708 provides an input pin for direct connection to a pushbutton reset (see Figure 2). The pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such that RST and RST signals of at least 130 ms minimum will be generated. The 130 ms delay commences as the pushbutton reset input is released from the low level. The pushbutton can be initiated by connecting the NMI output to the PBRST input as shown in Figure 3. Non-Maskable Interrupt The DS1707/DS1708 generates a non-maskable interrupt ( NMI ) for early warning of a power failure. A precision comparator monitors the voltage level at the IN pin relative to an on-chip reference generated by an internal band gap. The IN pin is a high impedance input allowing for a user-defined sense point. An external resistor voltage divider network (Figure 5) is used to interface with high voltage signals. This sense point may be derived from a regulated supply or from a higher DC voltage level closer to the main system power input. Since the IN trip point VTP is 1.25 volts, the proper values for R1 and R2 can be determined by the equation as shown in Figure 5. Proper operation of the DS1707/DS1708 requires that the voltage at the IN pin be limited to VCC. Therefore, the maximum allowable voltage at the supply being monitored (VMAX) can also be derived as shown in Figure 5. A simple approach to solving the equation is to select a value for R2 high enough to keep power consumption low, and solve for R1. The flexibility of the IN input pin allows for detection of power loss at the earliest point in a power supply system, maximizing the amount of time for system shut-down between NMI and RST/ RST . When the supply being monitored decays to the voltage sense point, the DS1707/DS1708 pulses the NMI output to the active state for a minimum 200 µs. The NMI power-fail detection circuitry also has built-in hysteresis of 100 µV. The supply must be below the voltage sense point for approximately 5 µs before a low NMI will be generated. In this way, power supply noise is removed from the monitoring function, preventing false interrupts. During a power-up, any detected IN pin levels below VTP by the comparator are disabled from generating an interrupt until VCC rises to VCCTP. As a result, any potential NMI pulse will not be initiated until VCC reaches VCCTP. Connecting NMI to PBRST would allow the non-maskable interrupt to generate an automatic reset when an out-of-tolerance condition occurred in a monitored supply. An example is shown in Figure 3. 2 of 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 DS1707/DS1708 MICROMONITOR BLOCK DIAGRAM Figure 1 PUSHBUTTON RESET Figure 2 PUSHBUTTON RESET CONTROLLED BY NMI Figure 3 3 of 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 DS1707/DS1708 TIMING DIAGRAM: PUSHBUTTON RESET Figure 4 NON-MASKABLE INTERRUPT CIRCUIT EXAMPLE Figure 5 VSENSE = R1+ R2 X 1.25 R2 Example: Therefore: VMAX = VSENSE X VCC VTP VSENSE = 4.70V at the trip point VCC = 3.3V 10 k = R2 4.70 X 3.3 = 12.4V maximum 1.25 4.70 = R1 + 10k X 1.25 10k 4 of 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 R1 = 27.6 k DS1707/DS1708 TIMING DIAGRAM: NON-MASKABLE INTERRUPT Figure 6 TIMING DIAGRAM: POWER-DOWN Figure 7 5 of 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 DS1707/DS1708 TIMING DIAGRAM: POWER UP Figure 8 6 of 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 DS1707/DS1708 ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Pin Relative to Ground Voltage on I/O Relative to Ground** Operating Temperature Storage Temperature Soldering Temperature * -0.5V to +7.0V -0.5V to VCC + 0.5V -40°C to +85°C -55°C to +125°C 260°C for 10 seconds This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ** The voltage input limits on IN and PBRST can be exceeded if the input current is less than 10 mA. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Supply Voltage SYMBOL VCC MIN 1.2 PBRST Input High Level VIH PBRST Input Low Level VIL MAX 5.5 UNITS V NOTES 1 2.0 VCC-0.5 VCC+0.3 V 1, 3 1, 4 -0.03 +0.5 V 1 DC ELECTRICAL CHARACTERISTICS TYP (-40°C to +85°C) (-40°C to +85°C; VCC=1.2V to 5.5V) PARAMETER VCC Trip Point DS1707 SYMBOL VCCTP MIN 4.50 TYP 4.65 MAX 4.75 UNITS V NOTES 1 VCC Trip Point DS1708 VCCTP 4.25 4.40 4.50 V 1 VCC Trip Point DS1708T VCCTP 3.00 3.08 3.15 V 1 VCC Trip Point DS1708S VCCTP 2.85 2.93 3.00 V 1 VCC Trip Point DS1708R VCCTP 2.55 2.63 2.70 V 1 Input Leakage IIL -1.0 +1.0 µA 2 Output Current @ 2.4V IOH µA 3 Output Current @ 0.4V IOL mA 3 Output Voltage VOH V 3 Operating Current @ VCC < 5.5V ICC 60 µA 5 Operating Current @ VCC < 3.6V ICC 50 µA 5 IN Input Trip Point VTP 1.30 V 1 350 10 VCC-0.1 1.20 1.25 CAPACITANCE PARAMETER (tA=25ካC) SYMBOL Input Capacitance Output Capacitance MIN MAX UNITS CIN 5 pF COUT 7 pF 7 of 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 TYP NOTES DS1707/DS1708 AC ELECTRICAL CHARACTERISTICS PARAMETER (-40°C to +85°C; VCC=1.2V to 5.5V) SYMBOL tPB MIN 150 TYP MAX UNITS ns Reset Active Time tRST 130 205 285 ms VCC Detect to RST and RST tRPD 5 8 µs PBRST = VIL VCC Slew Rate VCC Detect to RST and RST VCC Slew Rate PBRST Stable Low to RST and RST VIN Detect to NMI tF 20 tRPU 130 tR 0 205 285 5 250 ns 8 µs 1. All voltages are referenced to ground. 2. PBRST is internally pulled up to VCC with an internal impedance of 40 k typical. 2.4V 4. VCC < 2.4V 5. Measured with outputs open and all inputs at VCC or ground. 6. tR = 5 µs 7. Noise immunity - pulses < 2 µs at VCCTP minimum will not cause a reset. 8 of 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 ms 6 ns NOTES: 3. VCC 7 µs tPDLY tIPD NOTES 7 DS1707/DS1708 PART MARKING CODES 8-PIN µ-SOP (118 MIL) A, B, C and D represents the device type and tolerance. ABCD 707_ 708_ 708R 708S 708T - DS1707 DS1708 DS1708R DS1708S DS1708T WWY represents the device manufacturing Work Week, Year. 9 of 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 DS1707/DS1708 DATA SHEET REVISION SUMMARY The following represent the key differences between 01/09/96 and 06/17/97 versions of the DS1707/08 data sheet. Please review this summary carefully. 1. Page 7 add the following statement to the “Absolute Maximum Ratings” The voltage input limits on IN and PBRST can be exceeded if the input current is less than 10 mA. The following represent the key differences between 06/17/97 and 08/31/98 versions of the DS1707/08 data sheet. Please review this summary carefully. 1. Add –SOP to Maximum Compatible list Change pin out on µ–SOP package to match with Maximum 2. Correct “Supply Voltage” Minimum to 1.2 3. Correct Example Equation 10 of 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003