4 Ω RON, Triple/Quad SPDT ±15 V/+12 V/±5 V iCMOS® Switches ADG1433/ADG1434 FEATURES FUNCTIONAL BLOCK DIAGRAMS 4.7 Ω maximum on resistance @ 25°C 0.5 Ω on resistance flatness 33 V supply maximum ratings Fully specified at ±15 V/+12 V/±5 V 3 V logic compatible inputs Rail-to-rail operation Break-before-make switching action 16-/20-lead TSSOP and 4 mm × 4 mm LFCSP_VQ packages ADG1433 S1A D1 S1B S3B D3 S2B S3A D2 S2A LOGIC APPLICATIONS Relay replacement Audio and video routing Automatic test equipment Data acquisition systems Temperature measurement systems Avionics Battery-powered systems Communication systems Medical equipment 06181-001 IN1 IN2 IN3 EN SWITCHES SHOWN FOR A “1” INPUT LOGIC. Figure 1. ADG1433 TSSOP and LFCSP_VQ ADG1434 ADG1434 S4A D2 D1 S1B S4B IN1 IN4 IN2 IN3 S4B S2B S3B D3 S3A S2A LOGIC 06181-002 S3A SWITCHES SHOWN FOR A “1” INPUT LOGIC. S1B D2 D3 D2 S2A D2 D1 S3B S2B S4A S1A Figure 2. ADG1434 TSSOP IN1 IN2 IN3 IN4 EN SWITCHES SHOWN FOR A “1” INPUT LOGIC. 06181-101 S1A Figure 3. ADG1434 LFCSP_VQ GENERAL DESCRIPTION The ADG1433 and ADG1434 are monolithic industrial-CMOS (iCMOS) analog switches comprising three independently selectable single-pole, double-throw (SPDT) switches and four independently selectable SPDT switches, respectively. All channels exhibit break-before-make switching action that prevents momentary shorting when switching channels. An EN input on the ADG1433 (LFCSP and TSSOP packages) and ADG1434 (LFCSP package only) is used to enable or disable the device. When disabled, all channels are switched off. The iCMOS modular manufacturing process combines high voltage, complementary metal-oxide semiconductor (CMOS) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow on resistance and on resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications, where low distortion is critical. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 4.7 Ω maximum on resistance. 0.5 Ω on resistance flatness. 3 V logic compatible digital input VIH = 2.0 V, VIL = 0.8 V. 16-/20-lead TSSOP and 4 mm × 4 mm LFCSP_VQ packages. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADG1433/ADG1434 TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .......................................................................7 Applications....................................................................................... 1 ESD Caution...................................................................................7 Functional Block Diagrams............................................................. 1 Pin Configurations and Function Descriptions ............................8 General Description ......................................................................... 1 ADG1433........................................................................................8 Product Highlights ........................................................................... 1 ADG1434........................................................................................9 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 10 Specifications..................................................................................... 3 Test Circuits..................................................................................... 13 15 V Dual Supply.......................................................................... 3 Terminology .................................................................................... 15 12 V Single Supply........................................................................ 5 Outline Dimensions ....................................................................... 16 5 V Dual Supply............................................................................ 6 Ordering Guide .......................................................................... 17 Absolute Maximum Ratings............................................................ 7 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADG1433/ADG1434 SPECIFICATIONS 15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, ΔRON On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Drain Off Leakage, ID (OFF) Channel On Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH +25°C −40°C to +85°C −40°C to +125°C 1 VSS to VDD 4 4.7 0.5 0.78 0.5 0.72 ±0.04 ±0.3 ±0.04 ±0.3 ±0.05 ±0.4 5.7 6.7 0.85 1.1 0.77 0.92 ±0.6 ±3 ±0.6 ±3 ±0.8 ±8 2.0 0.8 ±0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANS Break-Before-Make Time Delay, tD 3 140 170 40 200 230 30 tON(EN) tOFF(EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion, THD + N −3 dB Bandwidth Insertion Loss CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD 140 170 60 75 −50 −70 −70 0.025 200 230 85 90 200 0.24 12 22 72 V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ 0.001 1 IDD Unit 260 440 Rev. 0 | Page 3 of 20 μA typ μA max μA typ μA max Test Conditions/Comments VS = ±10 V, IS = −10 mA; see Figure 25 VDD = +13.5 V, VSS = −13.5 V VS = ±10 V, IS = −10 mA VS = ±10 V, IS = −10 mA VDD = +16.5 V, VSS = −16.5 V VD = ±10 V, VS = ±10 V; see Figure 26 VD = ±10 V, VS = ±10 V; see Figure 26 VS = VD = ±10 V; see Figure 27 VIN = VGND or VDD RL = 100 Ω, CL = 35 pF VS = 10 V, see Figure 28 RL = 100 Ω, CL = 35 pF VS1 = VS2 = 10 V; see Figure 29 RL = 100 Ω, CL = 35 pF VS = 10 V, see Figure 30 RL = 100 Ω, CL = 35 pF VS = 10 V; see Figure 30 VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz, see Figure 35 RL = 50 Ω, CL = 5 pF, see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V ADG1433/ADG1434 Parameter ISS +25°C 0.001 VDD/VSS 1 2 −40°C to +85°C −40°C to +125°C 1 1 ±4.5/±16.5 Temperature range for Y version: −40°C to +125°C. Guaranteed by design, not subject to production test. Rev. 0 | Page 4 of 20 Unit μA typ μA max V min/max Test Conditions/Comments Digital inputs = 0 V, 5 V, or VDD GND = 0 V ADG1433/ADG1434 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, ΔRON On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Drain Off Leakage, ID (OFF) Channel On Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH +25°C −40°C to +85°C −40°C to +125°C 1 0 to VDD 6 8 0.55 0.82 1.5 2.5 ±0.04 ±0.3 ±0.04 ±0.3 ±0.06 ±0.4 9.5 11.2 0.85 1.1 2.5 2.8 ±0.6 ±3 ±0.6 ±3 ±0.8 ±8 2.0 0.8 ±0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANS Break-Before-Make Time Delay, tD 4 200 255 80 310 350 55 tON(EN) tOFF(EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk −3 dB Bandwidth Insertion Loss CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD 210 270 70 86 −10 –70 –70 135 0.5 25 45 80 320 360 95 105 0.002 1 IDD 260 VDD 1 2 440 5/16.5 Unit V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ MHz typ dB typ pF typ pF typ pF typ μA typ μA max μA typ μA max V min/max Temperature range for Y version: −40°C to +125°C. Guaranteed by design, not subject to production test. Rev. 0 | Page 5 of 20 Test Conditions/Comments VS = 0 V to 10 V, IS = −10 mA, see Figure 25 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = −10 mA VS = 0 V to 10 V, IS = −10 mA VDD = 13.2 V VS = 1 V/10 V, VD = 10 V/1 V, see Figure 26 VS = 1 V/10 V, VD = 10 V/1 V, see Figure 26 VS = VD = 1 V or 10 V, see Figure 27 VIN = VGND or VDD RL = 100 Ω, CL = 35 pF VS = 8 V, see Figure 28 RL = 100 Ω, CL = 35 pF VS1 = VS2 = 8 V, see Figure 29 RL = 100 Ω, CL = 35 pF VS = 8 V, see Figure 30 RL = 100 Ω, CL = 35 pF VS = 8 V, see Figure 30 VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 RL = 50 Ω, CL = 5 pF, see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33 f = 1 MHz f = 1 MHz f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V VSS = 0 V, GND = 0 V ADG1433/ADG1434 5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (ΔRON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Drain Off Leakage, ID (OFF) Channel On Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH +25°C −40°C to +85°C −40°C to +125°C 1 VSS to VDD 7 9 0.55 0.78 1.5 2.5 ±0.02 ±0.3 ±0.02 ±0.3 ±0.04 ±0.4 10.5 12 0.91 1.1 2.5 3 ±0.6 ±3 ±0.6 ±3 ±0.8 ±8 2.0 0.8 ±0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANS Break-Before-Make Time Delay, tD 4 315 430 90 480 550 55 tON(EN) tOFF(EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion, THD + N −3 dB Bandwidth Insertion Loss CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD 325 425 150 200 −10 −70 −70 0.06 145 0.5 18 32 80 490 545 225 240 0.002 1 ISS 0.001 VDD/VSS 1 2 1 ±4.5/±16.5 Unit V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ μA typ μA max μA typ μA max V min/max Temperature range for Y version: −40°C to +125°C. Guaranteed by design, not subject to production test. Rev. 0 | Page 6 of 20 Test Conditions/Comments VS = ±4.5 V, IS = −10 mA, see Figure 25 VDD = +4.5 V, VSS = −4.5 V VS = ±4.5 V, IS = −10 mA VS = ±4.5 V, IS = −10 mA VDD = +5.5 V, VSS = −5.5 V VD = ±4.5 V, VS = ±4.5 V, see Figure 26 VD = ±4.5 V, VS = ±4.5 V, see Figure 26 VS = VD = ±4.5 V, see Figure 27 VIN = VGND or VDD RL = 100 Ω, CL = 35 pF VS = 5 V, see Figure 28 RL = 100 Ω, CL = 35 pF VS1 = VS2 = 5 V, see Figure 29 RL = 100 Ω, CL = 35 pF VS = 5 V, see Figure 30 RL = 100 Ω, CL = 35 pF VS = 5 V, see Figure 30 VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz, see Figure 35 RL = 50 Ω, CL = 5 pF, see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +5.5 V, VSS = −5.5 V Digital inputs = 0 V, 5 V, or VDD Digital inputs = 0 V, 5 V, or VDD GND = 0 V ADG1433/ADG1434 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 4. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs, Digital Inputs1 Continuous Current, S or D Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Maximum) Operating Temperature Range Industrial (Y Version) Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature (Pb-Free) 1 Rating 35 V −0.3 V to +25 V +0.3 V to −25 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 30 mA 100 mA Table 5. Thermal Resistance Package Type TSSOP LFCSP_VQ ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 260 (+ 0 to −5)°C Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. Rev. 0 | Page 7 of 20 θJA 150.4 30.4 θJC 50 – Unit °C/W °C/W ADG1433/ADG1434 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EN S1B 4 TOP VIEW (Not to Scale) 13 VSS S1B 2 S2B 3 S3B 11 D3 S2A 7 10 S3A IN2 8 9 IN3 D2 4 ADG1433 TOP VIEW (Not to Scale) S2A 5 12 D2 6 06181-003 S2B 5 PIN 1 INDICATOR D1 1 12 EN 11 VSS 10 S3B 9 D3 06181-005 ADG1433 14 IN3 7 IN1 D1 3 S3A 8 GND 13 IN1 16 S1A 16 15 IN2 6 VDD 1 S1A 2 15 VDD 14 GND ADG1433 Figure 5. LFCSP_VQ Pin Configuration Figure 4. TSSOP Pin Configuration Table 6. ADG1433 Pin Function Descriptions Pin Number TSSOP LFCSP_VQ 1 15 2 16 3 1 4 2 5 3 6 4 7 5 8 6 9 7 10 8 11 9 12 10 13 11 14 12 Mnemonic VDD S1A D1 S1B S2B D2 S2A IN2 IN3 S3A D3 S3B VSS EN 15 16 IN1 GND 13 14 Description Most Positive Power Supply Potential. Source Terminal 1A. Can be an input or an output. Drain Terminal 1. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Source Terminal 2B. Can be an input or an output. Drain Terminal 2. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Logic Control Input. Logic Control Input. Source Terminal 3A. Can be an input or an output. Drain Terminal 3. Can be an input or an output. Source Terminal 3B. Can be an input or an output. Most Negative Power Supply Potential. In single supply applications, it can be connected to ground. Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx logic inputs determine the on switches. Logic Control Input. Ground (0 V) Reference. Table 7. ADG1433 Truth Table EN INx SxA SxB 1 0 0 X 0 1 Off Off On Off On Off Rev. 0 | Page 8 of 20 ADG1433/ADG1434 D4 S1B 4 17 S4B 16 VDD 15 NC 14 S3B ADG1434 VSS 5 TOP VIEW (Not to Scale) GND 6 S2B 7 D2 8 13 D3 S2A 9 12 S3A IN2 10 11 IN3 NC = NO CONNECT D1 S1B VSS GND S2B 1 2 3 4 5 PIN 1 INDICATOR ADG1434 TOP VIEW (Not to Scale) 15 14 13 12 11 D4 S4B VDD S3B D3 06181-006 18 20 19 18 17 16 S4A D1 3 6 7 8 9 10 IN4 D2 S2A IN2 IN3 S3A 20 19 06181-004 IN1 1 S1A 2 S1A IN1 EN IN4 S4A ADG1434 Figure 7. LFCSP_VQ Pin Configuration Figure 6. TSSOP Pin Configuration Table 8. ADG1434 Pin Function Descriptions Pin Number TSSOP LFCSP_VQ 1 19 2 20 3 1 4 2 5 3 6 4 7 5 8 6 9 7 10 8 11 9 12 10 13 11 14 12 15 – 16 13 17 14 18 15 19 16 20 17 – 18 Mnemonic IN1 S1A D1 S1B VSS GND S2B D2 S2A IN2 IN3 S3A D3 S3B NC VDD S4B D4 S4A IN4 EN Description Logic Control Input. Source Terminal 1A. Can be an input or an output. Drain Terminal 1. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Most Negative Power Supply Potential. In single supply applications, it can be connected to ground. Ground (0 V) Reference. Source Terminal 2B. Can be an input or an output. Drain Terminal 2. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Logic Control Input. Logic Control Input. Source Terminal 3A. Can be an input or an output. Drain Terminal 3. Can be an input or an output. Source Terminal 3B. Can be an input or an output. No Connect. Most Positive Power Supply Potential. Source Terminal 4B. Can be an input or an output. Drain Terminal 4. Can be an input or an output. Source Terminal 4A. Can be an input or an output. Logic Control Input. Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx logic inputs determine the on switches. Table 9. ADG1434 TSSOP Truth Table INx 0 1 SxA Off On SxB On Off Table 10. ADG1434 LFCSP_VQ Truth Table EN INx SxA SxB 1 0 0 X 0 1 Off Off On Off On Off Rev. 0 | Page 9 of 20 ADG1433/ADG1434 TYPICAL PERFORMANCE CHARACTERISTICS 7 VDD = +15V VSS = –15V TA = 25°C 6 ON RESISTANCE (Ω) 4 3 2 1 0 –16.5 VDD VDD VDD VDD VDD = +15V, VSS = –15V = +13.5V, VSS = –13.5V = +12V, VSS = –12V = +10V, VSS = –10V = +16.5V, VSS = –16.5V –12.5 –8.5 –4.5 5 4 3 2 1 –0.5 3.5 7.5 11.5 15.5 SOURCE OR DRAIN VOLTAGE (V) 0 –15 06181-007 ON RESISTANCE (Ω) 5 TA = +25°C TA = +85°C TA = –40°C TA = +125°C –10 –5 0 5 15 10 SOURCE OR DRAIN VOLTAGE (V) 06181-010 6 Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures, 15 V Dual Supply Figure 8. On Resistance as a Function of VD (VS), Dual Supply 12 9 VDD = +5V VSS = –5V TA = 25°C 8 10 5 4 3 2 1 0 –7 VDD VDD VDD VDD –6 = +7V, VSS = –7V = +5.5V, VSS = –5.5V = +5V, VSS = –5V = +4.5V, VSS = –4.5V –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 4 0 –5 TA = +25°C TA = +85°C TA = –40°C TA = +125°C –4 –3 –2 –1 0 1 2 3 4 5 SOURCE OR DRAIN VOLTAGE (V) Figure 12. On Resistance as a Function of VD (VS) for Different Temperatures, 5 V Dual Supply Figure 9. On Resistance as a Function of VD (VS), Dual Supply 13 10 TA = 25°C VSS = 0V 12 VDD = 12V VSS = 0V 9 11 8 ON RESISTANCE (Ω) 9 8 7 6 5 4 2 1 0 VDD VDD VDD VDD VDD = 12V = 13.2V = 10.8V = 8V = 5V 1 2 3 6 5 4 3 2 TA = +25°C TA = +85°C TA = –40°C TA = +125°C 1 4 5 6 7 8 9 10 11 12 13 SOURCE OR DRAIN VOLTAGE (V) Figure 10. On Resistance as a Function of VD (VS), Single Supply 0 06181-009 3 7 0 2 4 6 8 SOURCE OR DRAIN VOLTAGE (V) 10 12 06181-012 10 ON RESISTANCE (Ω) 6 2 SOURCE OR DRAIN VOLTAGE (V) 0 8 06181-011 ON RESISTANCE (Ω) 6 06181-008 ON RESISTANCE (Ω) 7 Figure 13. On Resistance as a Function of VD (VS) for Different Temperatures, 12 V Single Supply Rev. 0 | Page 10 of 20 ADG1433/ADG1434 70 1600 ID, IS (ON) + + 1200 IS (OFF) + – 1000 IDD PER CHANNEL TA = 25°C 60 50 800 IDD (µA) 600 40 30 400 20 IS (OFF) – + 200 10 0 20 40 60 80 100 120 TEMPERATURE (°C) 0 06181-013 2 0 10 12 14 200 VDD = +5V 1400 VSS = –5V VBIAS = +4.5V/–4.5V TA = 25°C 150 ID, IS (ON) + + 1200 CHARGE INJECTION (pC) LEAKAGE CURRENT (pA) 8 Figure 17. IDD vs. Logic Level 1600 1000 IS (OFF) + – 800 600 ID, IS (ON) – – 400 200 100 50 VDD = +5V VSS = –5V 0 VDD = +12V VSS = 0V –50 –100 VDD = +15V VSS = –15V –150 0 IS (OFF) – + 20 40 60 80 100 120 –200 –15 06181-014 0 TEMPERATURE (°C) –10 –5 0 5 10 15 VS (V) Figure 15. Leakage Currents as a Function of Temperature, 5 V Dual Supply Figure 18. Charge Injection vs. Source Voltage 2000 350 VDD = 12V 1800 VSS = 0V VBIAS = 1V/10V 1600 300 ID, IS (ON) + + 1400 250 TIME (ns) ID, IS (ON) – – 1200 1000 800 IS (OFF) + – 600 VDD = +5V VSS = –5V VDD = +12V VSS = 0V 200 150 VDD = +15V VSS = –15V 100 400 200 50 0 IS (OFF) – + 0 20 40 60 80 100 120 TEMPERATURE (°C) 06181-020 –200 6 LOGIC, INx (V) Figure 14. Leakage Currents as a Function of VD (VS), 15 V Dual Supply –200 4 06181-016 –200 VDD = +5V VSS = –5V 06181-015 ID, IS (ON) – – 0 LEAKAGE CURRENT (pA) VDD = +15V VSS = –15V VDD = +12V VSS = 0V Figure 16. Leakage Currents as a Function of Temperature, 12 V Single Supply 0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 19. Transition Time vs. Temperature Rev. 0 | Page 11 of 20 120 06181-017 LEAKAGE CURRENT (pA) VDD = +15V 1400 VSS = –15V VBIAS = +10V/–10V ADG1433/ADG1434 0 LOAD = 110Ω TA = 25°C 0.09 0.08 –30 0.07 THD + N (%) –40 –50 –60 –70 VDD = +5V, VSS = –5V, VS = +5V p-p 0.06 0.05 0.04 0.03 –80 –90 0.02 –100 0.01 –110 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) VDD = +15V, VSS = –15V, VS = +15V p-p 0 10 06181-018 OFF ISOLATION (dB) –20 0.10 VDD = +15V VSS = –15V TA = 25°C 10k 100k Figure 23. THD + N vs. Frequency 0 –20 1k FREQUENCY (Hz) Figure 20. Off Isolation vs. Frequency –10 100 06181-032 –10 0 VDD = +15V VSS = –15V TA = 25°C –20 VDD = +15V VSS = –15V TA = 25°C V p-p = 0.63V –40 –40 LOSS (dB) CROSSTALK (dB) –30 –50 –60 –70 NO DECOUPLING CAPACITORS –60 –80 –80 –90 DECOUPLING CAPACITORS ON SUPPLIES –100 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 21. Crosstalk vs. Frequency 0 –1.5 –2.0 –2.5 –3.0 –3.5 1k 10k 100k 1M 10M FREQUENCY (Hz) 100M 1G 06181-100 LOSS (dB) –1.0 –4.0 100 1k 10k 100k FREQUENCY (Hz) Figure 24. ACPSRR vs. Frequency VDD = +15V VSS = –15V TA = 25°C –0.5 –120 100 Figure 22. On Response vs. Frequency Rev. 0 | Page 12 of 20 1M 10M 06181-035 –110 1k 06181-019 –100 ADG1433/ADG1434 TEST CIRCUITS V A D IDS D Figure 26. Off Leakage ID (ON) D NC = NO CONNECT A VD 06181-023 S NC Figure 27. On Leakage VDD VSS VDD VIN 50% 50% VIN 50% 50% VSS SB VS 0.1µF D SA VOUT RL 100Ω IN CL 35pF 90% 90% VOUT tON tOFF 06181-024 GND VIN Figure 28. Switching Timing 0.1µF VDD VSS VDD VSS SB VS 0.1µF VIN D SA VOUT RL 100Ω IN VOUT 80% CL 35pF tBBM GND tBBM 06181-025 VIN Figure 29. Break-Before-Make Delay VDD VSS VDD VSS 0.1µF 3V ENABLE DRIVE (VIN) ADG1433 A2 S1A A1 S1B VS 0V VOUT A0 VIN VOUT D1 EN 50Ω GND 50% 50% RL 100Ω CL 35pF OUTPUT 0V Figure 30. Enable Delay, tON(EN), tOFF(EN) Rev. 0 | Page 13 of 20 tOFF (EN) 0.9VO tON (EN) 0.9VO 06181-026 0.1µF A VD Figure 25. On Resistance 0.1µF ID (OFF) VS 06181-021 VS S 06181-022 IS (OFF) S ADG1433/ADG1434 VS VDD VSS VDD VSS 0.1µF VIN (NORMALLY CLOSED SWITCH) SB D NC SA CL 1nF IN VOUT OFF VIN (NORMALLY OPEN SWITCH) VOUT GND VIN ON ΔVOUT QINJ = CL × ΔVOUT 06181-027 0.1µF Figure 31. Charge Injection VDD NETWORK ANALYZER VSS SA NC SB VSS 0.1µF 0.1µF 0.1µF VDD IN VDD VSS 0.1µF NETWORK ANALYZER 50Ω VOUT VDD SA VSS RL 50Ω 50Ω D VS SB R 50Ω D GND OFF ISOLATION = 20 log VOUT IN VS 06181-028 RL 50Ω VOUT VS GND CHANNEL-TO-CHANNEL CROSSTALK = 20 log Figure 32. Off Isolation VOUT VS 06181-030 VIN Figure 34. Channel-to-Channel Crosstalk VDD VSS 0.1µF VDD IN NETWORK ANALYZER VSS NC SB SA VDD VSS 0.1µF 0.1µF AUDIO PRECISION 50Ω VDD VSS RS 50Ω VS S VIN RL 50Ω GND VS V p-p IN D VOUT D VIN 06181-029 GND VOUT WITH SWITCH INSERTION LOSS = 20 log VOUT WITHOUT SWITCH RL 110Ω Figure 35. THD + Noise Figure 33. Bandwidth Rev. 0 | Page 14 of 20 VOUT 06181-031 0.1µF ADG1433/ADG1434 TERMINOLOGY TBBM Off time measured between the 80% point of both switches when switching from one address state to another. RON Ohmic resistance between Terminal D and Terminal S. ΔRON The difference between the RON of any two channels. VINL Maximum input voltage for Logic 0. RFLAT(ON) The difference between the maximum and minimum value of on resistance as measured. VINH Minimum input voltage for Logic 1. IS (OFF) Source leakage current when the switch is off. IINL (IINH) Input current of the digital input. ID (OFF) Drain leakage current when the switch is off. IDD Positive supply current. ID, IS (ON) Channel leakage current when the switch is on. ISS Negative supply current. VD (VS) Analog voltage on Terminal D and Terminal S. Off Isolation A measure of unwanted signal coupling through an off channel. CS (OFF) Channel input capacitance for off condition. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. CD (OFF) Channel output capacitance for off condition. Bandwidth The frequency at which the output is attenuated by 3 dB. CD, CS (ON) On switch capacitance. On Response The frequency response of the on switch. CIN Digital input capacitance. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. tON(EN) Delay time between the 50% and 90% points of the digital input and switch on condition. tOFF(EN) Delay time between the 50% and 90% points of the digital input and switch off condition. tTRANS Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. AC Power Supply Rejection Ratio (ACPSRR) A measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR. Rev. 0 | Page 15 of 20 ADG1433/ADG1434 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 4.00 BSC SQ 0.60 MAX 12 13 3.75 BSC SQ TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING 0.30 PLANE 0.23 0.18 1 16 EXPOSED PAD 0.65 BSC 4 8 9 PIN 1 INDICATOR 2.65 2.50 SQ 2.35 5 0.25 MIN 1.95 BCS 0.80 MAX 0.65 TYP BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.20 REF 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC. Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm, Very Thin Quad (CP-16-13) Dimensions shown in millimeters Rev. 0 | Page 16 of 20 031006-A PIN 1 INDICATOR 0.50 0.40 0.30 ADG1433/ADG1434 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 38. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 0.60 MAX 4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 1.00 0.85 0.80 SEATING PLANE 0.50 BSC 16 15 20 1 11 10 6 2.25 2.10 SQ 1.95 3.75 BCS SQ 0.80 MAX 0.65 TYP 12° MAX PIN 1 INDICATOR 0.75 0.55 0.35 0.25 MIN 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.20 REF 5 COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 39. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Description EN Pin Package Option ADG1433YRUZ 1 ADG1433YRUZ-REEL1 ADG1433YRUZ-REEL71 ADG1433YCPZ-REEL1 ADG1433YCPZ-REEL71 ADG1434YRUZ1 ADG1434YRUZ-REEL1 ADG1434YRUZ-REEL71 ADG1434YCPZ-REEL1 ADG1434YCPZ-REEL71 −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Yes Yes Yes Yes Yes No No No Yes Yes RU-16 RU-16 RU-16 CP-16-13 CP-16-13 RU-20 RU-20 RU-20 CP-20-1 CP-20-1 1 Z = Pb-free part. Rev. 0 | Page 17 of 20 ADG1433/ADG1434 NOTES Rev. 0 | Page 18 of 20 ADG1433/ADG1434 NOTES Rev. 0 | Page 19 of 20 ADG1433/ADG1434 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06181-0-10/06(0) Rev. 0 | Page 20 of 20