a CMOS 12-Bit Buffered Multiplying DAC AD7545 FEATURES 12-Bit Resolution Low Gain TC: 2 ppm/ⴗC typ Fast TTL Compatible Data Latches Single +5 V to +15 V Supply Small 20-Lead 0.3" DIP and 20-Terminal Surface Mount Packages Latch Free (Schottky Protection Diode Not Required) Low Cost Ideal for Battery Operated Equipment FUNCTIONAL BLOCK DIAGRAM RFB 20 AD7545 VREF 19 R 12-BIT MULTIPLYING DAC 1 OUT 1 2 AGND 12 WR 17 CS 16 18 VDD INPUT DATA LATCHES 3 DGND 12 DB11–DB0 (PINS 4–15) The AD7545 is particularly suitable for single supply operation and applications with wide temperature variations. GENERAL DESCRIPTION The AD7545 is a monolithic 12-bit CMOS multiplying DAC with onboard data latches. It is loaded by a single 12-bit wide word and directly interfaces to most 12- and 16-bit bus systems. Data is loaded into the input latches under the control of the CS and WR inputs; tying these control inputs low makes the input latches transparent, allowing direct unbuffered operation of the DAC. The AD7545 can be used with any supply voltage from +5 V to +15 V. With CMOS logic levels at the inputs the device dissipates less than 0.5 mW for VDD = +5 V. PIN CONFIGURATIONS DB11 (MSB) 4 18 VDD 16 CS DB10 5 AD7545 17 WR DB10 5 DB9 6 TOP VIEW (Not to Scale) 16 CS DB9 6 15 DB0 (LSB) DB8 7 16 CS 15 DB0 (LSB) DB7 8 14 DB1 9 10 11 12 13 DB2 9 10 11 12 13 DB3 11 DB4 18 VDD 17 WR AD7545 TOP VIEW (Not to Scale) DB4 12 DB3 DB5 10 20 19 PIN 1 IDENTIFIER DB6 13 DB2 DB6 9 14 DB1 DB7 8 DB2 DB7 8 DB8 7 DB3 TOP VIEW 15 DB0 (MSB) (Not to Scale) 14 DB1 DB4 DB8 7 1 DB11 (MSB) 4 DB6 DB9 6 AD7545 DB5 DB10 5 2 VREF 17 WR RFB DB11 (MSB) 4 3 AGND 18 VDD RFB 19 VREF DGND 3 OUT 1 1 20 19 20 RFB AGND 2 DB5 2 OUT 1 1 DGND 3 VREF AGND PLCC OUT 1 LCCC DGND DIP REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 AD7545–SPECIFICATIONS (V Parameter STATIC PERFORMANCE Resolution Differential Nonlinearity Gain Error (Using Internal RFB) 2 Gain Temperature Coefficient 3 ∆Gain/∆Temperature DC Supply Rejection 3 ∆Gain/∆VDD Output Leakage Current at OUT1 DYNAMIC PERFORMANCE Current Settling Time 3 Propagation Delay 3 (from Digital Input Change to 90% of Final Analog Output) Digital-to-Analog Glitch Inpulse AC Feedthrough5 At OUT1 REFERENCE INPUT Input Resistance (Pin 19 to GND) ANALOG OUTPUT Output Capacitance 3 COUT1 COUT1 DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL Input Current6 IIN Input Capacitance3 DB0–DB11 WR, CS SWITCHING CHARACTERISTICS 7 Chip Select to Write Setup Time tCS Chip Select to Write Hold Time tCH Write Pulse Width tWR Data Setup Time tDS Data Hold Time tDH POWER SUPPLY IDD REF = +10 V, VOUT1 = O V, AGND = DGND unless otherwise noted) Version VDD = +5 V Limits TA = + 25ⴗC TMIN, TMAX1 VDD = +15 V Limits TA = + 25ⴗC TMIN, TMAX1 Units Test Conditions/Comments All J, A, S K, B, T L, C, U GL, GC, GU J, A, S K, B, T L, C, U GL, GC, GU J, A, S K, B, T L, C, U GL, GC, GU 12 ±2 ±1 ± 1/2 ± 1/2 ±4 ±1 ±1 ±1 ± 20 ± 10 ±5 ±1 12 ±2 ±1 ± 1/2 ± 1/2 ±4 ±1 ±1 ±1 ± 20 ± 10 ±6 ±2 12 ±2 ±1 ± 1/2 ± 1/2 ±4 ±1 ±1 ±1 ± 25 ± 15 ± 10 ±6 12 ±2 ±1 ± 1/2 ± 1/2 ±4 ±1 ±1 ±1 ± 25 ± 15 ± 10 ±7 Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max 10-Bit Monotonic TMIN to TMAX 12-Bit Monotonic TMIN to TMAX 12-Bit Monotonic TMIN to TMAX 12-Bit Monotonic TMIN to TMAX DAC Register Loaded with 1111 1111 1111 Gain Error Is Adjustable Using the Circuits of Figures 4, 5, and 6 All ±5 ±5 ± 10 ± 10 ppm/°C max Typical Value is 2 ppm/°C for VDD = +5 V All J, K, L, GL A, B, C, GC S, T, U, GU 0.015 10 10 10 0.03 50 50 200 0.01 10 10 10 0.02 50 50 200 % per % max nA max nA max nA max ∆VDD = ± 5% DB0–DB11 = 0 V; WR, CS = 0 V All 2 2 2 2 µs max To 1/2 LSB. OUT1 Load = 100 Ω. DAC Output Measured from Falling Edge of WR, CS = 0. All All 300 400 – – 250 250 – – ns max nV sec typ OUT1 Load = 100 Ω, CEXT = 13 pF4 VREF = AGND All 5 5 5 5 mV p-p typ VREF = ± 10 V, 10 kHz Sinewave All 7 25 7 25 7 25 7 25 kΩ min kΩ max Input Resistance TC = –300 ppm/°C typ Typical Input Resistance = 11 kΩ All 70 200 70 200 70 200 70 200 pF max pF max DB0–DB11 = 0 V, WR, CS = 0 V DB0–DB11 = VDD, WR, CS = 0 V All 2.4 2.4 13.5 13.5 V min All 0.8 0.8 1.5 1.5 V max All ±1 ± 10 ±1 ± 10 µA max VIN = 0 or VDD All All 5 20 5 20 5 20 5 20 pF max pF max VIN = 0 VIN = 0 All 280 200 380 270 180 120 200 150 ns min ns typ See Timing Diagram All 0 0 0 0 ns min All 250 175 140 100 400 280 210 150 160 100 90 60 240 170 120 80 ns min ns typ ns min ns typ All 10 10 10 10 ns min All 2 100 10 2 500 10 2 100 10 2 500 10 mA max µA max µA typ All tCS ≥ tWR, tCH ≥ 0 All Digital Inputs VIL or VIH All Digital Inputs 0 V to VDD All Digital Inputs 0 V to VDD NOTES 1 Temperature range as follows: J, K, L, GL versions, 0°C to +70°C; A, B, C, GC versions, –25°C to +85°C; S, T, U GU versions, –55°C to +125°C. 2 This includes the effect of 5 ppm max gain TC. 3 Guaranteed but not tested. 4 DB0–DB11 = 0 V to VDD or VDD to 0 V. 5 Feedthrough can be further reduced by connecting the metal lid on the ceramic package (Suffix D) to DGND. 6 Logic inputs are MOS gates. Typical input current (+25°C) is less than 1 nA. 7 Sample tested at +25°C to ensure compliance. Specifications subject to change without notice. –2– REV. A AD7545 tCH tCS MODE SELECTION VDD CHIP SELECT 0 tWR WRITE MODE: HOLD MODE: CS AND WR LOW, DAC RESPONDS TO DATA BUS (DB0–DB11) INPUTS. EITHER CS OR WR HIGH, DATA BUS (DB0–DB11) IS LOCKED OUT; DAC HOLDS LAST DATA PRESENT WHEN WR OR CS ASSUMED HIGH STATE. VDD WRITE NOTES: VDD = +5V; tr = tf = 20ns VDD = +15V; tr = tf = 40ns ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF VDD. TIMING MEASUREMENT REFERENCE LEVEL IS VIH + VIL/2. 0 tDS VIH VIL DATA IN (DB0–DB11) tDH VDD DATA VALID 0 Write Cycle Timing Diagram Commercial (J, K, L, GL) Grades . . . . . . . . 0°C to +70°C Industrial (A, B, C, GC) Grades . . . . . . . . –25°C to +85°C Extended (S, T, U, GU) Grades . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C ABSOLUTE MAXIMUM RATINGS* (TA = + 25°C unless otherwise noted) VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +17 V Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD +0.3 V VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V VPIN1 to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C Operating Temperature *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7545 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. TERMINOLOGY WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE1 RELATIVE ACCURACY The amount by which the D/A converter transfer function differs from the ideal transfer function after the zero and fullscale points have been adjusted. This is an endpoint linearity measurement. DIFFERENTIAL NONLINEARITY The difference between the measured change and the ideal change between any two adjacent codes. If a device has a differential nonlinearity of less than 1 LSB it will be monotonic, i.e., the output will always increase for an increase in digital code applied to the D/A converter. PROPAGATION DELAY This is a measure of the internal delay of the circuit and is measured from the time a digital input changes to the point at which the analog output at OUT1 reaches 90% of its final value. DIGITAL-TO-ANALOG GLITCH IMPULSE This is a measure of the amount of charge injected from the digital inputs to the analog outputs when the inputs change state. It is usually specified as the area of the glitch in nV secs and is measured with VREF = AGND and an ADLH0032CG as the output op amp, C1 (phase compensation) = 33 pF. REV. A Model2 Temperature Range Relative Accuracy Maximum Gain Error TA = +25ⴗC VDD = +5 V AD7545JN AD7545AQ AD7545SQ AD7545KN AD7545BQ AD7545TQ AD7545LN AD7545CQ AD7545UQ AD7545GLN AD7545GCQ AD7545GUQ AD7545JP AD7545SE AD7545KP AD7545TE AD7545LP AD7545UE AD7545GLP AD7545GUE 0°C to +70°C –25°C to +85°C –55°C to +125°C 0°C to +70°C –25°C to +85°C –55°C to +125°C 0°C to +70°C –25°C to +85°C –55°C to +125°C 0°C to +70°C –25°C to +85°C –55°C to +125°C 0°C to +70°C –55°C to +125°C 0°C to +70°C –55°C to +125°C 0°C to +70°C –55°C to +125°C 0°C to +70°C –55°C to +125°C ± 2 LSB ± 2 LSB ± 2 LSB ± 1 LSB ± 1 LSB ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 1/2 LSB ± 1/2 LSB ± 1/2 LSB ± 1/2 LSB ± 2 LSB ± 2 LSB ± 1 LSB ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 1/2 LSB ± 1/2 LSB ± 20 LSB ± 20 LSB ± 20 LSB ± 10 LSB ± 10 LSB ± 10 LSB ± 5 LSB ± 5 LSB ± 5 LSB ± 1 LSB ± 1 LSB ± 1 LSB ± 20 LSB ± 20 LSB ± 10 LSB ± 10 LSB ± 5 LSB ± 5 LSB ± 1 LSB ± 1 LSB Package Options3 N-20 Q-20 Q-20 N-20 Q-20 Q-20 N-20 Q-20 Q-20 N-20 Q-20 Q-20 P-20A E-20A P-20A E-20A P-20A E-20A P-20A E-20A NOTES 1 Analog Devices reserves the right to ship either ceramic (D-20) in lieu of cerdip packages (Q-20). 2 To order MIL-STD-883, Class B process parts, add /883B to part number. Contact local sales office for military data sheet. For U.S. Standard Military DRAWING (SMD) see DESC drawing 5962-87702. 3 E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip. –3– AD7545 power supply. To minimize power supply currents it is recommended that the digital input voltages be as close as practicably possible to the supply rails (VDD and DGND). CIRCUIT INFORMATION—D/A CONVERTER SECTION Figure 1 shows a simplified circuit of the D/A converter section of the AD7545 and Figure 2 gives an approximate equivalent circuit. Note that the ladder termination resistor is connected to AGND. R is typically 11 kΩ. VREF R R 2R R 2R The AD7545 may be operated with any supply voltage in the range 5 ≤ VDD ≤ 15 volts. With VDD = +15 V the input logic levels are CMOS compatible only, i.e., 1.5 V and 13.5 V. R 2R 2R 2R 2R BASIC APPLICATIONS Figures 4 and 5 show simple unipolar and bipolar circuits using the AD7545. Resistor R1 is used to trim for full scale. The “G” versions (AD7545GLN, AD7545GCQ, AD7545GUD) have a guaranteed maximum gain error of ± 1 LSB at +25°C (VDD = +5 V), and in many applications it should be possible to dispense with gain trim resistors altogether. Capacitor C1 provides phase compensation and helps prevent overshoot and ringing when using high speed op amps. Note that all the circuits of Figures 4, 5 and 6 have constant input impedance at the VREF terminal. RFB OUT 1 AGND DB11 (MSB) DB10 DB9 DB1 DB0 (LSB) Figure 1. Simplified D/A Circuit of AD7545 The binary weighted currents are switched between the OUT1 bus line and AGND by N-channel switches, thus maintaining a constant current in each ladder leg independent of the switch state. The circuit of Figure 1 can either be used as a fixed reference D/A converter so that it provides an analog output voltage in the range 0 to –VIN (note the inversion introduced by the op amp), or VIN can be an ac signal in which case the circuit behaves as an attenuator (2-Quadrant Multiplier). VIN can be any voltage in the range –20 ≤ VIN + 20 volts (provided the op amp can handle such voltages) since VREF is permitted to exceed VDD. Table II shows the code relationship for the circuit of Figure 4. The capacitance at the OUT1 bus line, COUT1, is code dependent and varies from 70 pF (all switches to AGND) to 200 pF (all switches to OUT1). One of the current switches is shown in Figure 2. The input resistance at VREF (Figure 1) is always equal to RLDR (RLDR is the R/2R ladder characteristic resistance and is equal to value “R”). Since RIN at the VREF pin is constant, the reference terminal can be driven by a reference voltage or a reference current, ac or dc, of positive or negative polarity. (If a current source is used, a low temperature coefficient external RFB is recommended to define scale factor.) VDD VIN R1* R2* 18 20 VDD RFB 19 VREF C1 33pF OUT1 1 VOUT AD7545 AGND 2 AD544L (SEE TEXT) DGND 3 ANALOG COMMON TO LADDER DB11–DB0 FROM INTERFACE LOGIC *REFER TO TABLE I Figure 4. Unipolar Binary Operation AGND Table I. Recommended Trim Resistor Values vs. Grades for VDD = +5 V OUT 1 Figure 2. N-Channel Current Steering Switch Trim Resistor J/A/S K/B/T L/C/U GL/GC/GU R1 R2 500 Ω 150 Ω 200 Ω 68 Ω 100 Ω 33 Ω 20 Ω 6.8 Ω CIRCUIT INFORMATION—DIGITAL SECTION Figure 3 shows the digital structure for one bit. The digital signals CONTROL and CONTROL are generated from CS and WR. Table II. Unipolar Binary Code Table for Circuit of Figure 4 TO AGND SWITCH VIN Binary Number in DAC Register Analog Output TO OUT1 SWITCH 1111 1111 1111 4095 –VIN 4096 Figure 3. Digital Input Structure 1000 0000 0000 The input buffers are simple CMOS inverters designed so that when the AD7545 is operated with VDD = 5 V, the buffers convert TTL input levels (2.4 V and 0.8 V) into CMOS logic levels. When VIN is in the region of 2.0 volts to 3.5 volts, the input buffers operate in their linear region and draw current from the 2048 –VIN 4096 = –1/2 VIN 0000 0000 0001 0000 0000 0000 1 –VIN 4096 0 Volts INPUT BUFFERS CONTROL CONTROL –4– REV. A AD7545 Figure 5 and Table III illustrate the recommended circuit and code relationship for bipolar operation. The D/A function itself uses offset binary code and inverter U1 on the MSB line converts twos complement input code to offset binary code. If appropriate; inversion of the MSB may be done in software using an exclusive –OR instruction and the inverter omitted. R3, R4 and R5 must be selected to match within 0.01% and they should be the same type of resistor (preferably wire-wound or metal foil), so their temperature coefficients match. Mismatch of R3 value to R4 causes both offset and full-scale error. Mismatch of R5 and R4 and R3 causes full-scale error. VDD R1* VIN R2* C1 33pF 18 20 VDD RFB 19 VREF AGND 2 VOUT ANALOG COMMON *FOR VALUES OF R1 AND R2 SEE TABLE I. DATA INPUT Figure 5. Bipolar Operation (Twos Complement Code) Table III. Twos Complement Code Table for Circuit of Figure 5 Data Input 1111 Analog Output 1111 2047 +VIN × 2048 0000 0000 0001 1 +VIN × 2048 0000 0000 0000 0 Volts 1111 1111 1111 1 –VIN × 2048 1000 0000 0000 2048 –VIN × 2048 R1* 19 VREF RFB OUT1 1 AD7545 R3 10kΩ A1 AGND 2 DB11–DB0 10% AD544L 3 VOUT A2 AD544J 1/2 AD7592JN ANALOG COMMON 12 1 1111 1111 1111 4095 – VIN × 4096 Another cause of digital glitches is capacitive coupling from the digital lines to the OUT1 and AGND terminals. This should be minimized by screening the analog pins of the AD7545 (Pins 1, 2, 19, 20) from the digital pins by a ground track run between Pins 2 and 3 and between Pins 18 and 19 of the AD7545. Note how the analog pins are at one end of the package and separated from the digital pins by VDD and DGND to aid screening at the board level. On-chip capacitive coupling can also give rise to crosstalk from the digital-to-analog sections of the AD7545, particularly in circuits with high currents and fast rise and fall times. This type of crosstalk is minimized by using R5 20kΩ R4 20kΩ C1 33pF 20 VDD VIN 0000 0000 0000 0000 0000 0000 Digital Glitches: When WR and CS are both low the latches are transparent and the D/A converter inputs follow the data inputs. In some bus systems, data on the data bus is not always valid for the whole period during which WR is low and as a result invalid data can briefly occur at the D/A converter inputs during a write cycle. Such invalid data can cause unwanted glitches at the output of the D/A converter. The solution to this problem, if it occurs, is to retime the write pulse WR so that it only occurs when data is valid. R2* 18 0 1 4095 + VIN × 4096 0 Volts 0 Volts General Ground Management: AC or transient voltages between AGND and DGND can cause noise injection into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7545. In more complex systems where the AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AD7545 AGND and DGND pins (IN914 or equivalent). Figure 6 shows an alternative method of achieving bipolar output. The circuit operates with sign plus magnitude code and has the advantage of giving 12-bit resolution in each quadrant, compared with 11-bit resolution per quadrant for the circuit of Figure 5. The AD7592 is a fully protected CMOS change-over switch with data latches. R4 and R5 should match each other to 0.01% to maintain the accuracy of the D/A converter. Mismatch between R4 and R5 introduces a gain error. VDD 1111 1111 1111 Output Offset: (CMOS D/A converters exhibit a code dependent output resistance which, in turn, causes a code dependent amplifier noise gain. The effect is a code dependent differential nonlinearity term at the amplifier output that depends on VOS where VOS is the amplifier input offset voltage. To maintain monotonic operation it is recommended that VOS be no greater than 25 × 10–6) (VREF) over the temperature range of operation. Suitable op amps are AD517L and AD544L. The AD517L is best suited for fixed reference applications with low bandwidth requirements: it has extremely low offset (50 µV) and in most applications will not require an offset trim. The AD544L has a much wider bandwidth and higher slew rate and is recommended for multiplying and other applications requiring fast settling. An offset trim on the AD544L may be necessary in some circuits. AD544J 11 12 0111 0 Analog Output, VOUT APPLICATIONS HINTS A2 R6 5kΩ AD544L 10% U1 (SEE TEXT) Binary Number in DAC MSB LSB A1 DB10–DB0 4 Sign Bit Note: Sign bit of “0” connects R3 to GND. R5 20kΩ R3 10kΩ OUT1 1 AD7545 DB11 R4 20kΩ Table IV. 12-Plus Sign Magnitude Code Table for Circuit of Figure 6 SIGN BIT *FOR VALUES OF R1 AND R2 SEE TABLE I. Figure 6. 12-Bit Plus Sign Magnitude D/A Converter REV. A –5– AD7545 V DD = +5 volts. However, great care should be taken to ensure that the +5 V used to power the AD7545 is free from digitally induced noise. +2 Temperature Coefficients: The gain temperature coefficient of the AD7545 has a maximum value of 5 ppm/°C and a typical value of 2 ppm/°C. This corresponds to worst case gain shifts of 2 LSBs and 0.8 LSBs respectively over a 100°C temperature range. When trim resistors Rl and R2 are used to adjust fullscale range, the temperature coefficient of R1 and R2 should also be taken into account. The reader is referred to Analog Devices Application Note “Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs,” Publication Number E630–10–6/81. DNL – LSB +1 0 –1 –2 0 SINGLE SUPPLY OPERATION 10 5 15 VDD – Volts The ladder termination resistor of the AD7545 (Figure 1) is connected to AGND. This arrangement is particularly suitable for single supply operation because OUT1 and AGND may be biased at any voltage between DGND and VDD. OUT1 and AGND should never go more than 0.3 volts less than DGND or an internal diode will be turned on and a heavy current may flow which will damage the device. (The AD7545 is, however, protected from the SCR latch-up phenomenon prevalent in many CMOS devices.) Figure 8. Differential Nonlinearity vs. VDD for Figure 7 Circuit. Reference Voltage = 2.5 Volts. Shaded Area Shows Range of Values of Differential Nonlinearity that Typically Occur for L, C and U Grades. 0.5 Figure 7 shows the AD7545 connected in a voltage switching mode. OUT1 is connected to the reference voltage and AGND is connected to DGND. The D/A converter output voltage is available at the VREF pin and has a constant output impedance equal to R. RFB is not used in this circuit. DNL – LSB 0.0 –0.5 –1.0 +15V 18 REFERENCE VOLTAGE –1.5 VDD 1 OUT1 2 AGND DGND AD7545 3 VREF 19 VO –2.0 DB11–DB0 0 5 VREF – Volts 10 12 Figure 9. Differential Nonlinearity vs. Reference Voltage for Figure 7 Circuit. VDD = 15 Volts. Shaded Area Shows Range of Values of Differential Nonlinearity that Typically Occur for L, C and U Grades. 15 VOLT CMOS DIGITAL INPUTS Figure 7. Single Supply Operation Using Voltage Switching Mode The circuits of Figures 4, 5 and 6 can all be converted to single supply operation by biasing AGND to some voltage between VDD and DGND. Figure 10 shows the twos complement bipolar circuit of Figure 5 modified to give a range from +2 V to +8 V about a “pseudo-analog ground” of 5 V. This voltage range would allow operation from a single VDD of +10 V to +15 V. The AD584 pin-programmable reference fixes AGND at +5 V. VIN is set at +2 V by means of the series resistors R1 and R2. There is no need to buffer the VREF input to the AD7545 with an amplifier because the input impedance of the D/A converter is constant. Note, however, that since the temperature coefficient of the D/A reference input resistance is typically –300 ppm/°C; applications that experience wide temperature variations may require a buffer amplifier to generate the +2.0 V at the AD7545 VREF pin. Other output voltage ranges can be obtained by changing R4 to shift the zero point and (R1 + R2) to change the slope, or gain, of the D/A transfer function. VDD must be kept at least 5 V above OUT1 to ensure that linearity is preserved. The loading on the reference voltage source is code dependent and the response time of the circuit is often determined by the behavior of the reference voltage with changing load conditions. To maintain linearity, the voltages at OUT1 and AGND should remain within 2.5 volts of each other, for a VDD of 15 volts. If VDD is reduced from 15 V, or the differential voltage between OUT1 and AGND is increased to more than 2.5 V, the differential nonlinearity of the DAC will increase and the linearity of the DAC will be degraded. Figures 8 and 9 show typical curves illustrating this effect for various values of reference voltage and VDD. If the output voltage is required to be offset from ground by some value, then OUT1 and AGND may be biased up. The effect on linearity and differential nonlinearity will be the same as reducing VDD by the amount of the offset. –6– REV. A AD7545 VDD = +10V TO +15V 18 +2V VDD 19 VREF R1 10KΩ MSB 4 RFB R3 10kΩ OUT1 1 AD7545 DB10–DB0 R5 20kΩ C1 33pF 20 A1 2 AGND DGND +5V 3 1 2 DATA AD544J R6 5kΩ VDD R2 2kΩ AD584J VO A2 AD544L R4 33.3kΩ 8 Figure 12 shows an alternative approach for use with 8-bit processors which have a full 16-bit wide address bus such as 6800, 8080, Z80 This technique uses the 12 lower address lines of the processor address bus to supply data to the DAC, thus each AD7545 connected in this way uses 4k bytes of address locations. Data is written to the DAC using a single memory write instruction. The address field of the instruction is organized so that the lower 12 bits contain the data for the DAC and the upper 4 bits contain the address of the 4k block at which the DAC resides. 4 A15 CMOS DATA BUS VDD = +10V TO +15V 16-BIT ADDRESS BUS A0 4 Figure 10. Single Supply “Bipolar” Twos Complement D/A Converter ADDRESS DECODE CPU MICROPROCESSOR INTERFACING OF THE AD7545 WR DATA BUS D0 Figure 12. Connecting the AD7545 to 8-Bit Processors via the Address Bus SUPPLEMENTAL APPLICATION MATERIAL ADDRESS BUS For further information on CMOS multiplying D/A converters the reader is referred to the following texts: A0 CPU CS Application Guide to CMOS Multiplying D/A converters available from Analog Devices, Publication Number G479. CS Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACS—Application Note, Publication Number E630–10–6/81 available from Analog Devices. DB11 LATCH 4 4 DB8 WR AD7545 WR WR DB7 8 DB0 D7 8-BIT DATA BUS 8 D0 * Q0 = DECODED ADDRESS FOR DAC Q1 = DECODED ADDRESS FOR LATCH Figure 11. 8-Bit Processor to AD7545 Interface REV. A WR D7 A15 Q1* AD7545 CS A typical interface circuit for an 8-bit processor is shown in Figure 11. This arrangement uses two memory addresses, one for the lower eight bits of data to the DAC and one for the upper four bits of data into the DAC via the latch. Q0* DB0 Q0 The AD7545 can directly interface to both 8- and 16-bit microprocessors via its 12-bit wide data latch using standard CS and WR control signals. ADDRESS DECODE DB11 12 –7– AD7545 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Plastic DIP (N-20) 20-Terminal Leadless Ceramic Chip Carrier (LCCC) (E-20A) C670d–0–6/97 20-Lead Cerdip (Q-20) PRINTED IN U.S.A. 20-Lead Plastic Leaded Chip Carrier (PLCC) (P-20A) –8– REV. A