TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 D D D D D D D Four 8-Bit D/A Converters With Individual References Direct Bipolar Operation Without an External Level-Shift Amplifier Microprocessor Compatible TTL/CMOS Compatible Single Supply Operation Possible Simultaneous Update Facility Binary Input Coding applications D D D Process Control Automatic Test Equipment Automatic Calibration of Large System Parameters e.g., Gain/Offset DW PACKAGE (TOP VIEW) OUTB OUTA VSS REFB REFA AGND DGND LDAC (MSB) DB7 DB6 DB5 DB4 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 OUTC OUTD VDD REFC REFD A0 A1 WR DB0 (LSB) DB1 DB2 DB3 description The TLC7225 consists of four 8-bit voltage-output digital-to-analog converters (DACs), with output buffer amplifiers and interface logic with double register-buffering. Separate on-chip latches are provided for each of the DACs. Data is transferred into one of these data latches through a common 8-bit TTL/CMOS-compatible (5 V) input port. Control inputs A0 and A1 determine which DAC is loaded when WR goes low. Only the data held in the DAC registers determines the analog outputs of the converters. The double register buffering allows simultaneous update of all four outputs under control of LDAC. All logic inputs are TTL- and CMOS-level compatible and the control logic is speed compatible with most 8-bit microprocessors. Each DAC includes an output buffer amplifier capable of driving up to 5 mA of output current. The TLC7225 performance is specified for input reference voltages from 2 V to VDD – 4 V with dual supplies. The voltage-mode configuration of the DACs allow the TLC7225 to be operated from a single power-supply rail at a reference of 10 V. The TLC7225 is fabricated in a LinBiCMOS process that has been specifically developed to allow high-speed digital logic circuits and precision analog circuits to be integrated on the same chip. The TLC7225 has a common 8-bit data bus with individual DAC latches. This provides a versatile control architecture for simple interface to microprocessors. All latch-enable signals are level triggered. Combining four DACs, four operational amplifiers, and interface logic into a small, 0.3-inch wide, 24-terminal SOIC allows significant reduction in board space requirements and offers increased reliability in systems using multiple converters. The pinout optimizes board layout with all of the analog inputs and outputs at one end of the package and all of the digital inputs at the other. The TLC7225C is characterized for operation from 0°C to 70°C. The TLC7225I is characterized for operation from – 40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 AVAILABLE OPTIONS PACKAGED DEVICES TA SMALL OUTLINE (DW) 0°C to 70°C TLC7225CDW – 40°C to 85°C TLC7225IDW functional block diagram REFA 5 _ Input Latch A DAC Latch A DAC A Input Latch B DAC Latch B DAC B 8 Input Latch C DAC Latch C DAC C 8 Input Latch D DAC Latch D DAC D 8 REFB 4 2 _ 8 9–16 DB0 – DB7 21 REFC 8 OUTA + 1 + OUTB _ REFD LDAC 20 24 _ + 8 17 WR 19 A0 18 A1 Control Logic schematic of outputs EQUIVALENT ANALOG OUTPUT VDD Output 100 µA 450 µA VSS 2 POST OFFICE BOX 655303 OUTC + • DALLAS, TEXAS 75265 23 OUTD TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 Terminal Functions TERMINAL NAME NO. AGND 6 A0, A1 18, 19 DGND 7 DB0 – DB7 9 – 16 I/O DESCRIPTION Analog ground I DAC select inputs Digital ground I Digital DAC data inputs LDAC 8 Load DAC. A high level simultaneously loads all four DAC registers. DAC registers are transparent when LDAC is low. OUTA 2 O DACA output OUTB 1 O DACB output OUTC 24 O DACC output OUTD 23 O DACD output REFA 5 I Voltage reference input to DACA REFB 4 I Voltage reference input to DACB REFC 21 I Voltage reference input to DACC REFD 20 I Voltage reference input to DACD VDD VSS 22 Positive supply voltage 3 Negative supply voltage WR 17 I Write input selects DAC transparency or latch mode absolute maximum ratings over operating free-air temperature range (unless otherwise note)† Supply voltage range, VDD: to AGND or DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 17 V to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 24 V Supply voltage range, VSS: to AGND or DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 7 V to VDD Voltage range between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD Input voltage range, VI (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Reference voltage range, Vref (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD Output voltage range, VO (to AGND) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD Continuous total power dissipation at (or below) TA = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . 500 mW Operating free-air temperature range: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Output voltages may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit current to AGND is 50 mA. 2. For operation above TA = 75°C derate linearly at the rate of 2.0 mW/°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 recommended operating conditions MIN MAX UNIT Supply voltage, VDD 11.4 16.5 V Supply voltage, VSS – 5.5 0 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 Reference voltage, Vref 2 Load resistance, RL 2 Operating free-air free air temperature, temperature TA C suffix I suffix VDD – 4 V V kΩ 0 70 °C – 40 85 °C MAX UNIT timing requirements (see Figure 1) PARAMETER TEST CONDITIONS MIN tsu(AW) Setup time, address valid before WR↓ 0 ns tsu(DW) Setup time, data valid before WR↑ VDD = 11.4 V to 16.5 V, VSS = 0 or – 5 V 45 ns th(AW) Hold time, address valid after WR↑ VDD = 11.4 V to 16.5 V, VSS = 0 or – 5 V 0 ns th(DW) Hold time, data valid after WR↑ VDD = 11.4 V to 16.5 V, VSS = 0 or – 5 V 10 ns tw1 Pulse duration, WR low VDD = 11.4 V to 16.5 V, VSS = 0 or – 5 V 50 ns tw2 Pulse duration, LDAC low VDD = 11.4 V to 16.5 V, VSS = 0 or – 5 V 50 ns 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 electrical characteristics over recommended operating free-air temperature range reference inputs (all supply ranges) PARAMETER ri Ci TEST CONDITIONS Input resistance, REFA, REFB, REFC, REFD Input In ut capacitance ca acitance, REFA REFA, REFB REFB, REFC REFC, REFD ac feedthrough TYP 1.5 4 DAC loaded with all 1s DAC loaded with all 0s Channel-to-channel isolation MIN Vreff = 10 Vpp sine wave at 10 kHz MAX UNIT kΩ 300 pF 65 pF 60 dB 70 dB dual power supply over recommended supply and reference voltage ranges, AGND = DGND = 0 V (unless otherwise noted) PARAMETER II IDD Input current, digital ISS Supply current, VSS Supply current, VDD Input capacitance MIN VI = VIL or VIH, No load ∆VDD = ± 5% Power supply sensitivity Ci TEST CONDITIONS VI = 0 or VDD VI = VIL or VIH, No load TYP MAX UNIT ±1 µA 10 16 mA 4 10 mA 0.01 %/% Digital inputs 8 pF single power supply, VDD = 14.25 V to 15.75 V, VSS = AGND = DGND = 0 V, Vref (A, B, C, D) = 10 V PARAMETER II IDD Ci Input current, digital TEST CONDITIONS Supply current, VDD VI = 0 or VDD VI = VIL or VIH, No load Power supply sensitivity ∆VDD = ± 5% Input capacitance Digital inputs MIN TYP MAX ±1 5 • DALLAS, TEXAS 75265 µA 13 mA 0.01 %/% 8 POST OFFICE BOX 655303 UNIT pF 5 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 operating characteristics over recommended operating free-air temperature range dual power supply over recommended supply and reference voltage ranges, AGND = DGND = 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS Slew rate ts MIN Positive full scale MAX Settling time to 1/2 LSB Negative full scale UNIT V/µs 5 Vref(A, f(A B, B C, C D) = 10 V 7 Resolution 8 µs Bits VDD = 15 V ± 5%, VDD = 15 V ± 5%, Vref(A, B, C, D) = 10 V Vref(A, B, C, D) = 10 V ±2 LSB ±1 LSB Vref(A, B, C, D) = 10 V Vref(A, B, C, D) = 10 V ±1 LSB Full-scale error VDD = 15 V ± 5%, VDD = 15 V ± 5%, ±2 LSB Gain error VDD = 15 V ± 5%, Vref(A, B, C, D) = 10 V Total unadjusted error Integral nonlinearity (INL) Differential nonlinearity (DNL) EFS EG TYP 2.5 Temperature coefficient of gain Full-scale error Zero-code error VDD = 14 V to 16.5 16 5 V, V ± 0.25 Vref(A, f(A B, B C, C D) = 10 V ppm/°C ± 50 ± 20 Zero-code error Digital crosstalk or feedthrough glitch impulse area LSB ± 20 Vref(A, B, C, D) = 0 µV/°C ± 80 50 mV nV– s single power supply, VDD = 14.25 V to 15.75 V, VSS = AGND = DGND = 0 V, Vref(A, B, C, D) = 10 V (unless otherwise noted) PARAMETER TEST CONDITIONS Slew rate ts Settling time to 1/2 LSB TYP UNIT V/µs Positive full scale 5 Negative full scale 20 8 µs Bits Total unadjusted error ±2 LSB Full-scale error ±2 LSB Temperature coefficient of g gain Full-scale error VDD = 14 V to 16.5 V, Vref(A, B, C, D) = 10 V ± 20 ppm/°C ± 50 Zero-code error µV/°C ±1 Differential nonlinearity error (DNL) Digital crosstalk or feedthrough glitch impulse area 6 MAX 2 Resolution EFS MIN POST OFFICE BOX 655303 50 • DALLAS, TEXAS 75265 LSB nV– s TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION VDD Address 0V th(AW) tsu(AW) tw1 VDD WR 0V tw2 VDD LDAC 0V th(DW) tsu(DW) VDD Data Valid Data In 0V NOTES: A. tr = tf = 20 ns over VDD range. B. The timing-measurement reference level is equal to VIH + VIL divided by 2. C. If LDAC is activated prior to the rising edge of WR, then it must remain low for at least tw2 after WR goes high. Figure 1. Write-Cycle Voltage Waveforms TYPICAL CHARACTERISTICS OUTPUT CURRENT vs OUTPUT VOLTAGE OUTPUT CURRENT (SINK) vs OUTPUT VOLTAGE 200 700 I O – Output Current – mA I O – Output Current (Sink) – µ A VDD = 15 V 150 Source Current Short-Circuit Limiting 100 50 0 – 0.1 TA = 25°C VSS = – 5 V DB0– DB7 = 0 V – 0.2 TA = 25°C VDD = 15 V 600 500 VSS = – 5 V 400 VSS = 0 300 200 100 – 0.3 Sinking Current Source – 0.4 –2 –1 0 1 2 0 0 1 VO – Output Voltage – V 2 3 4 5 6 7 8 9 10 VO – Output Voltage – V Figure 2 Figure 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 APPLICATION INFORMATION specification ranges For the TLC7225 to operate to rated specifications, the input reference voltage must be at least 4 V below the power supply voltage at the VDD terminal. This voltage differential is the overhead voltage required by the output amplifiers. The TLC7225 is specified to operate over a VDD range from 12 V ± 5% to 15 V ± 10% (i.e., from 11.4 V to 16.5 V) with a VSS of – 5 V ± 10%. Operation is also specified for a single supply with a VDD of 15 V ± 5%. Applying a VSS of – 5 V results in improved zero-code error, improved output sink capability with outputs near AGND, and improved negative-going settling time. Performance is specified over the range of reference voltages from 2 V to (VDD – 4 V) with dual supplies. This allows a range of standard refence generators to be used such as the TL1431, with an adjustable 2.5-V bandgap reference. Note that an output voltage range of 0 V to 10 V requires a nominal 15 V ± 5% power supply voltage. DAC section The TLC7225 contains four, identical, 8-bit voltage-mode DACs. Each converter has a separate reference input. The output voltages from the converters have the same polarity as the reference voltages, thus allowing single supply operation. The simplified circuit diagram for channel A is shown in Figure 4. Note that AGND (terminal 6) is common to all four DACs. _ R R R + 2R 2R DB0 2R 2R 2R DB5 DB6 DB7 OUTA REFA AGND Shown For All 1s On DAC Figure 4. DAC Simplified-Circuit Diagram The input impedance at any of the reference inputs is code dependent and can vary from 1.4 kΩ minimum to an open circuit. The lowest input impedance at any reference input occurs when that DAC is loaded with the digital code 01010101. Therefore, it is important that the reference source presents a low output impedance under changing load conditions. The nodal capacitance at the reference terminals is also code dependent and typically varies from 60 pF to 300 pF. Each OUTx terminal can be considered as a digitally programmable voltage source with an output voltage of: VOUTx = Dx × VREFx where Dx is the fractional representation of the digital input code and can vary from 0 to 255/256. The output impedance is that of the output buffer amplifier. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 APPLICATION INFORMATION output buffer Each voltage-mode DAC output is buffered by a unity-gain noninverting amplifier. This buffer amplifier is capable of developing 10 V across a 2-kΩ load and can drive capacitive loads of 3300 pF. The TLC7225 can be operated as a single or dual supply; operating with dual supplies results in enhanced performance in some parameters which cannot be achieved with a single-supply operation. In a single supply operating (VSS = 0 V = AGND) the sink capability of the amplifier, which is normally 400 µA, is reduced as the output voltage nears AGND. The full sink capability of 400 µA is maintained over the full output voltage range by tying VSS to – 5 V. This is indicated in Figure 3. Settling time for negative-going output signals approaching AGND is similarly affected by VSS. Negative-going settling time for single supply operation is longer than for dual supply operation. Positive-going settling-time is not affected by VSS. Additionally, the negative VSS gives more headroom to the output amplifiers which results in better zero code performance and improved slew rate at the output than can be obtained in the single-supply mode. digital inputs The TLC7225 digital inputs are compatible with either TTL or 5-V CMOS levels. To minimize power supply currents, it is recommended that the digital input voltages be driven as close to the supply rails (VDD and DGND) as practically possible. interface logic information The TLC7225 contains two registers per DAC, an input register and a DAC register. Address lines A0 and A1 select which input register accepts data from the input port. When the WR signal is low, the input latches of the selected DAC are transparent. The data is latched into the addressed input register on the rising edge of WR. Table 1 shows the addressing for the input registers on the TLC7225. Table 1. TLC7225 Addressing CONTROL INPUTS A1 SELECTED INPUT REGISTER A0 L L DAC A input register L H DAC B input register H L DAC C input register H H DAC D input register Only the data held in the DAC register determines the analog output of the converter. The LDAC signal is common to all four DACs and controls the transfer of information from the input registers to the DAC registers. Data is latched into all four DAC registers simultaneously on the rising edge of LDAC. The LDAC signal is level triggered and, therefore, the DAC registers may be made transparent by tying LDAC low (the outputs of the converters responds to the data held in their respective input latches). LDAC is an asynchronous signal and is independent of WR. This is useful in many applications. However, in systems where the asynchronous LDAC can occur during a write cycle (or vice versa) care must be taken to ensure that incorrect data is not latched through to the output. In other words, if LDAC is activated prior to the rising edge of WR (or WR occurs during LDAC), then LDAC must stay low for a time of tw2 or longer after WR goes high to ensure that the correct data is latched through to the output. Table 2 shows the truth table for TLC7225 operation. Figure 5 shows the input control logic for the device and the write cycles timing diagram is shown in Figure 1. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 APPLICATION INFORMATION Table 2. TLC7225 Truth Table CONTROL INPUTS FUNCTION WR LDAC H H No operation. Device not selected L H Input register of selected DAC is transparant. ↑ H Input register of selected DAC is latched. H L All four DAC registers are transparent (i.e., outputs respond to data held in respective input registers) input registers are latched. H ↑ All four DAC registers are latched. L L DAC registers and selected input register are transparent. Output follows input data for selected channel. A0 A1 19 To Latch A 18 To Latch B To Latch C WR To Latch D 17 Figure 5. Input Control Logic 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 APPLICATION INFORMATION ground management and layout The TLC7225 contains four reference inputs that can be driven from ac sources (see multiplying DAC using ac input to the REF terminals section) so careful layout and grounding is important to minimize analog crosstalk between the four channels. The dynamic performance of the four DACs depends upon the optimum choice of board layout. Figure 6 shows the relationship between input frequency and channel-to-channel isolation. Figure 7 shows a printed circuit board layout that minimizes crosstalk and feedthrough. The four input signals are screened by AGND. Vref was limited between 2 V and 3.24 V to avoid slew-rate limiting effects from the output amplifier during measurements. – 80 TA = 25°C VDD = 15 V VSS = – 5 V Isolation – dB – 70 – 60 Vref = 1.24 VPP – 50 – 40 – 30 – 20 10 k 20 k 50 k 100 k 200 k 500 k 1M fI – Input Frequency – Hz Figure 6. Channel-to-Channel Isolation ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ System GND Terminal 1 OUTB OUTA VSS REFB REFA AGND DGND MSB OUTC OUTD VDD REFC REFD LSB Figure 7. Suggested PCB Layout (Top View) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 APPLICATION INFORMATION unipolar output operation The unipolar output operation is the basic mode of operation for each channel of the TLC7225, with the output voltages having the same positive polarity as Vref. The TLC7225 can be operated with a single supply (VSS = AGND) or with positive or negative supplies. The voltage at Vref must never be negative with respect to DGND to prevent parasitic transistor turn-on. Connections for the unipolar output operation are shown in Figure 8. The transfer values are shown in Table 3. _ REFA 5 2 OUTA + DAC A _ REFB 4 1 _ REFC 21 OUTB + DAC B 24 OUTC + DAC C _ 23 REFD 20 OUTD + DAC D VSS AGND DGND Figure 8. Unipolar Output Circuit Table 3. Unipolar Code DAC LATCH CONTENTS MSB LSB Ǔ Ǔ Ǔ+) Ǔ ) Ǔ ) Ǔ+ ǒ Ǔ +ǒ 1111 1111 1000 0001 1000 0000 ) Vref ) Vref ) Vref 0111 1111 V 127 ref 256 0000 0001 V 1 ref 256 0000 0000 NOTE 3 : 1 LSB 12 ǒ ǒ ǒ ǒ ǒ ANALOG OUTPUT 255 256 129 256 128 256 0V V ref POST OFFICE BOX 655303 2– 8 V 1 ref 256 • DALLAS, TEXAS 75265 V ref 2 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 APPLICATION INFORMATION AGND bias for direct bipolar-output operation The TLC7225 can be used in bipolar operation without adding additional external operational amplifiers by biasing AGND to VSS as shown in Figure 9. This configuration provides an excellent method for providing a direct bipolar output with no additional components. The transfer values are shown in Table 4. 5 REFA (Vref = 5 V) 22 VDD = 10 to 15 V TLC7225† _ OUTA 2 AGND Output range (5 V to – 5 V) + DAC A 6 3 7 VSS DGND –5 V † Digital inputs omitted for clarity. Figure 9. AGND Bias for Direct Bipolar-Output Operation Table 4. Bipolar (Offset Binary) Code DAC LATCH CONTENTS MSB LSB 1111 1111 ) Vref 1000 0001 ) Vref 1000 0000 0111 1111 0000 0001 0000 0000 POST OFFICE BOX 655303 ǒ ǒ ǒ ǒ Ǔ Ǔ Ǔ Ǔ ANALOG OUTPUT 127 128 1 128 0V * Vref * Vref –V 1 128 127 128 ǒ Ǔ+* 128 ref 128 • DALLAS, TEXAS 75265 V ref 13 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 APPLICATION INFORMATION AGND bias for positive output offset The TLC7225 AGND terminal can be biased above or below the system ground terminal, DGND, to provide an offset-zero analog-output voltage level. Figure 10 shows a circuit configuration to achieve this for channel A of the TLC7225. The output voltage, VO at OUTA, can be expressed as: V O + Vbias ) DA ǒǓ V I where DA is a fractional representation of the digital input word (0 ≤ D ≤ 255/256). 5 Vref 22 VDD TLC7225† VI _ 2 AGND + DAC A VO(OUTA) 6 3 Vbias 7 VSS DGND † Digital inputs omitted for clarity. Figure 10. AGND Bias Circuit Increasing AGND above system ground reduces the output range. VDD – Vref must be at least 4 V to ensure specified operation. Since the AGND terminal is common to all four DACs, this method biases up the output voltages of all the DACs in the TLC7225. Supply voltages VDD and VSS for the TLC7225 should be referenced to DGND. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 APPLICATION INFORMATION bipolar-output operation using external amplifier Each of the DACs of the TLC7225 can also be individually configured to provide bipolar output operation using an external amplifier and two resistors per channel. Figure 11 shows a circuit used to implement offset binary coding (bipolar operation) with DAC A of the TLC7225. In this case (see equation 1): V O + 1 ) R2 R1 ǒ D + R2 V + 2D * 1 A O ǒ with R1 where D A Ǔ A V V Ǔ* ǒ Ǔ ref R2 R1 V (1) ref ref is a fractional representation of the digital word in latch A. Mismatch between R1 and R2 causes gain and offset errors. Therefore, these resistors must match and track over temperature. The TLC7225 can be operated with a single supply or from positive and negative supplies. REFA R1† R2† 5 15 V TLC7225 _ _ 2 VO + + DAC A – 15 V † R1 = R2 = 10 kΩ ± 0.1% Figure 11. Bipolar-Output Circuit multiplying DAC using ac input to the REF terminals The TLC7225 can be used as a multiplying DAC when the reference signal is maintained between 2 V and VDD – 4 V. When this configuration is used, VDD should be 14.25 V to 15.75 V. A low output-impedance buffer should be used so that the input signal is not loaded by the resistor ladder. Figure 12 shows the general schematic. 15 V 15 V 15 V _ + AC Reference Input Signal VDD 1/4 TLC7225 R1 REF (A, B, C, D) 5, 4, 21, 20 OP - 15 _ DAC AGND 6 VO + DGND 7 R2 Figure 12. AC Signal-Input Scheme POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 APPLICATION INFORMATION digital word multiplication Since each DAC of the TLC7225 has a separate reference input, the output of one DAC can be used as the reference input for another. Therefore, multiplication of digital words can be performed (with the result given in analog form). For example, when the output from DAC A is applied to REFB then the output from DAC B, VOUTB, can be expressed as given in equation 2: VOUTB = (DA) (DB) (VREFA) (2) where DA and DB are the fractional representations of the digital words in DAC latches A and B respectively. If DA = DB = D then the result is D2 (VREFA) In this manner, the four DACs can be used on their own or in conjunction with an external summing amplifier to generate complex waveforms. Figure 13 shows one such application with the output waveform, Y, which is represented by equation 3: Y = –(x4 + 2x3 + 3x2 + 2x + 4) VI (3) where x is the digital code that is applied to all four DAC latches. 15 V VI REFA 25 kΩ 50 kΩ VDD _ OUTA TLC7225† 33 kΩ REFB OUTB REFC OUTC REFD OUTD 50 kΩ 100 kΩ AGND DGND VSS † Digital inputs omitted for clarity Figure 13. Complex-Waveform Generation 16 100 kΩ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Y + TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 APPLICATION INFORMATION microprocessor interface Figures 14, 15, 16, and 17 show the hardware interface to some of the standard processors. A15 Address Bus A8 A0 A1 8085/8088 Address Decode LDAC TLC7225† WR WR DB7 Latch ALE EN DB0 AD7 Address Data Bus AD0 † Linear circuitry omitted for clarity Figure 14. TLC7225 to 8085A/8088 Interface, Double-Buffered Mode A15 Address Bus A8 A0 8085/8088 R/W Address Decode A1 LDAC EN TLC7225† WR E or φ2 DB7 DB0 AD7 Data Bus AD0 † Linear circuitry omitted for clarity Figure 15. TLC7225 to 6809/6502 Interface, Single-Buffered Mode POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 APPLICATION INFORMATION A15 Address Bus A8 A0 Z-80 A1 MREQ Address Decode EN LDAC TLC7225† WR WR DB7 DB0 AD7 Data Bus AD0 † Linear circuitry omitted for clarity Figure 16. TLC7225 to Z-80 Interface, Double-Buffered Mode A23 Address Bus A1 A0 68008 AS Address Decode EN A1 TLC7225† WR R/W LDAC DTACK DB7 DB0 AD7 Data Bus AD0 † Linear circuitry omitted for clarity Figure 17. TLC7225 to 68008 Interface, Single-Buffered Mode 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC7225C, TLC7225I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS109A – OCTOBER 1996 – REVISED APRIL 1997 APPLICATION INFORMATION linearity, offset, and gain error using single-ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, since the most negative supply rail is ground, the output cannot drive below ground. So with this output offset voltage, the output voltage remains at zero until the input-code value produces a sufficient output voltage to overcome the inherent offset voltage, resulting in a transfer function shown in Figure 18. Output Voltage 0V DAC Code Negative Offset Figure 18. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below ground. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale is adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity in the unipolar mode is measured between full-scale code and the lowest code, which produces a positive output voltage. The code is calculated from the maximum specification for the zero offset error. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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