INTEGRATED CIRCUITS PCA9561 Quad 6-bit multiplexed I2C EEPROM Product data 2002 May 24 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 The PCA9561 typically resides between the CPU and Voltage Regulator Module (VRM) when used for CPU VID (Voltage IDentification code) configuration. It is used to bypass the CPU–defined VID values and provide a different set of VID values to the VRM, if an increase in the CPU voltage is desired. An increase in CPU voltage combined with an increase in CPU frequency leads to a performance boost of up to 7.5%. Lower CPU voltage reduces power consumption. The main advantage of the PCA9561 over older devices, such as the PCA9559 or PCA9560, is that it contains four internal non–volatile EEPROM registers instead of just one or two, allowing five independent settings which allows a more accurate CPU voltage tuning depending on specific applications. FEATURES • Selection of non-volatile register_n as source to MUX_OUT pins The PCA9561 has 2 address pins, allowing up to 4 devices to be placed on the same I2C bus or SMBus. via I2C-bus • I2C-bus can override MUX_SELECT pin in selecting output source PIN CONFIGURATION • 6-bit 5-to-1 multiplexer • 4 internal non-volatile registers • Internal non-volatile registers programmable and readable via SCL 1 20 VDD SDA 2 19 WP A0 3 18 A1 MUX_IN_A 4 17 MUX_OUT_A I2C-bus • 6 open drain multiplexed outputs • 400 kHz maximum clock frequency • Operating supply voltage 3.0 V to 3.6 V • 5 V and 2.5 V tolerant inputs • Useful for Speed Step configuration of laptop • 2 address pins, allowing up to 4 devices on the I2C-bus • MUX_IN values readable via I2C-bus • ESD protection exceeds 200 V HBM per JESD22-A114, 200 V MUX_IN_B 5 16 MUX_OUT_B MUX_IN_C 6 15 MUX_OUT_C MUX_IN_D 7 14 MUX_OUT_D MUX_IN_E 8 13 MUX_OUT_E MUX_IN_F 9 12 MUX_OUT_F GND 10 11 MUX_SELECT SW00823 PIN DESCRIPTION MM per JESD22-A115, and 1000 V CDM per JESD22-C101 • Latch-up testing is done to JESDEC Standard JESD78 which PIN exceeds 100 mA. DESCRIPTION The PCA9561 is a 20–pin CMOS device consisting of four 6–bit non–volatile EEPROM registers, 6 hardware pin inputs and a 6–bit multiplexed output. It is used for DIP switch–free or jumper–less system configuration and supports Mobile and Desktop VID Configuration, where 5 preset values (4 sets of internal non–volatile registers and 1 set of external hardware pins) set processor voltage for operation in various performance or battery conservation sleep modes. The PCA9561 is also useful in server and telecom/networking applications when used to replace DIP switches or jumpers, since the settings can be easily changed via I2C/SMBus without having to power down the equipment to open the cabinet. The non–volatile memory retains the most current setting selected before the power is turned off. SYMBOL 1 I2C 2 I2C SDA 3 A0 4–9 MUX_IN_A–F 10 GND 11 MUX_SELECT 12–17 MUX_OUT_F–A SCL FUNCTION Serial I2C-bus clock Serial bi-directional I2C-bus data A0 address External inputs to multiplexer Ground Selects MUX_IN inputs or register contents for MUX_OUT outputs Open drain multiplexed outputs 18 A1 A1 address 19 WP Non-volatile register write-protect 20 VDD Power supply: +3.0 to +3.6 V ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 20-Pin Plastic SO 0 to +70 °C PCA9561D SOT163-1 20-Pin Plastic TSSOP 0 to +70 °C PCA9561PW SOT360-1 Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging. Speed Step is a registered trademark of Intel 2002 May 24 2 853-2348 28311 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 BLOCK DIAGRAM PCA9561 WRITE PROTECT 6 NON-VOLATILE REGISTER 1 6-BIT EEPROM 6 NON-VOLATILE REGISTER 2 6-BIT EEPROM 6 NON-VOLATILE REGISTER 3 6-BIT EEPROM 6-BIT 4 TO 1 DEMULTIPLEXER NON-VOLATILE REGISTER 0 6-BIT EEPROM 6 8 A0 2 A1 SCL SDA INPUT FILTER 6 2 I C LOGIC VDD MUX_OUT_A POWER-ON RESET GND 4 MUX_OUT_B 6-BIT 2 TO 1 DEMULTIPLEXER MUX_IN_A MUX_IN_B MUX_OUT_C MUX_OUT_D MUX_OUT_E MUX_IN_C MUX_OUT_E MUX_IN_D 6 MUX_IN_E MUX_IN_F MUX_SELECT SELECT LOGIC SW00842 2002 May 24 3 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 FUNCTION TABLE MUX_SELECT MUX_OUT OUTPUT 1 MUX_IN input2 0 Non-volatile register chosen by I2C command byte NOTE: 1. X = Don’t Care. 2. Unless overridden by I2C control register I2C INTERFACE Communicating with this device is initiated by sending a valid address on the I2C bus. The address format (see FIgure 1) has 5 fixed bits and two user-programmable bits followed by a 1-bit read/write value which determines the direction of the data transfer. MSB LSB 1 0 0 1 1 A1 R/W# A0 SW00824 Figure 1. I2 C address byte MSB LSB LSB MSB 0000 0000 access EEPROM Byte 0 0000 0001 access EEPROM Byte1 0000 0010 access EEPROM Byte 2 0000 0011 access EEPROM Byte 3 1111 DCBA See Table From 0000 0100 to 1110 1111 is reserved SW00833 Figure 2. I2C command byte COMMAND BYTE 1111 DCBA 1111 2002 May 24 Special case read MUX_IN values 00X1 MUX_SELECT pin selects between MUX_IN and non-volatile register 0 as data source to MUX_OUT 01X1 MUX_SELECT pin selects between MUX_IN and non-volatile register 1 as data source to MUX_OUT 10X1 MUX_SELECT pin selects between MUX_IN and non-volatile register 2 as data source to MUX_OUT 11X1 MUX_SELECT pin selects between MUX_IN and non-volatile register 3 as data source to MUX_OUT XX10 MUX_SELECT pin is overridden by I2C and MUX_IN is sourced to MUX_OUT 0000 MUX_SELECT pin is overridden I2C and non-volatile register 0 is sourced to MUX_OUT 0100 MUX_SELECT pin is overridden by I2C and non-volatile register 1 is sourced to MUX_OUT 1000 MUX_SELECT pin is overridden by I2C and non-volatile register 2 is sourced to MUX_OUT 1100 MUX_SELECT pin is overridden by I2C and non-volatile register 3 is sourced to MUX_OUT 4 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 Following the address and acknowledge bit with logic 0 in the read/write bit, the first byte written is the command byte. If the command byte is reserved and therefore not valid, it will not be acknowledged. Only valid command bytes will be acknowledged. If the command byte is an EEPROM address, the next byte sent will be programmed into that EEPROM address on the following STOP condition, if the WP is logic 0. If more than one byte is sent sequentially, the second byte will be written in the other-volatile register, on the following STOP condition. Up to four bytes can be sent sequentially. If any more data bytes are sent after the fourth byte, they will not be acknowledged and no bytes will be written to the non-volatile registers. After a byte is read from or written to the EEPROM, the part automatically points to the next non-volatile register. If the command byte is a MUX command byte, any additional data bytes sent after the MUX command code will not be acknowledged. If the read/write bit in the address is a logic 1, then a read operation follows and the data sent out depends on the previously stored command code. If the command code was FFH, the MUX_IN values are sent with the two MSBs padded with zeroes as shown in Figure 3. If the command code was 00H, then the non-volatile register 1 is sent, and if the command code was 01H, then the non-volatile register 1 is sent, if the command code was 02H, then the third non-volatile register is sent, and if the command code was 03H, then the fourth non-volatile register is sent. After a valid I2C write operation to the EEPROM, the part cannot be addressed via the I2C for 3.6 ms. If the part is addressed prior to this time, the part will not acknowledge its address. NOTE: 1. To ensure data integrity, the non-volatile register must be internally write protected when VDD to the I2C bus is powered down or VDD to the component is dropped below normal operating levels. MSB LSB 0 0 MUX_IN DATA F MUX_IN DATA E MUX_IN DATA D MUX_IN DATA C MUX_IN DATA B MUX_IN DATA A SW00825 Figure 3. I2C read on MUX_IN values POWER-ON RESET When power is applied to VDD, an internal power-on reset holds the PCA9561 in a reset state until VDD has reached VPOR. At that point, the reset condition is released and the PCA9561 registers and state machine will initialize to their default states. 2002 May 24 5 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 DEVICE ADDRESS Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9561 is shown in Figure 1. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. The last bit of the slave address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write operation. MSB LSB 1 0 0 1 1 A1 FIXED A0 R/W# PROGRAMMABLE SW00955 Figure 1. Slave address CONTROL REGISTER Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9561, which will be stored in the control register. This register can be written and read via the I2C bus. D7 D6 D5 D4 D3 D2 D1 D0 SW00954 Figure 2. Control Register CONTROL REGISTER DEFINITION Following the address and acknowledge bit with logic 0 in the read/write bit, the first byte written is the command byte. If the command byte is reserved and therefore not valid, it will not be acknowledged. Only valid command bytes will be acknowledged. Table 1. Register Addresses REGISTER NAME REGISTER FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 EEPROM 0 Read/Write EEPROM byte 0 register 0 0 0 0 0 0 0 1 EEPROM 1 Read/Write EEPROM byte 1 register 0 0 0 0 0 0 1 0 EEPROM 2 Read/Write EEPROM byte 2 register 0 0 0 0 0 0 1 1 EEPROM 3 Read/Write EEPROM byte 3 register 1 1 1 1 1 1 1 1 MUX_IN Read MUX_IN values register TYPE Table 2. Commands D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 0 0 0 MUX_OUT from EEPROM byte 0 COMMAND 1 1 1 1 1 1 0 0 MUX_OUT from EEPROM byte 1 1 1 1 1 1 0 X 1 MUX_OUT from EEPROM byte 2 1 1 1 1 1 1 X 1 MUX_OUT from EEPROM byte 3 1 1 1 1 1 X 1 0 MUX_OUT from MUX_IN 1 1 1 1 1 X X 1 MUX_OUT from MUX_SELECT2 NOTE: 1. All other combinations are reserved. 2. MUX_SELECT pins select between MUX_IN and EEPROM to MUX_OUT. 2002 May 24 6 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 REGISTER DESCRIPTION If the command byte is an EEPROM address, the next byte sent will be programmed into that EEPROM address on the following STOP condition, if the WP is logic 0. If more than one byte is sent sequentially, the second byte will be written in the other-volatile register, on the following STOP condition. If any more data bytes are sent after the second byte, they will not be acknowledged and no bytes will be written to the non-volatile registers. After a byte is read from or written to the EEPROM, the part automatically points to the next non-volatile register. If the command code was FFH, the MUX_IN values are sent with the three MSBs padded with zeroes as shown below. If the command codes was 00H, then the non-volatile register 1 is sent, and if the command code was 01H, then the non-volatile register 1 is sent. EEPROM Byte 0 Register D7 D6 D5 D4 D3 D2 D1 D0 Write X X EEPROM 0 Data 5 EEPROM 0 Data 4 EEPROM 0 Data 3 EEPROM 0 Data 2 EEPROM 0 Data 1 EEPROM 0 Data 0 Read 0 0 EEPROM 0 Data 5 EEPROM 0 Data 4 EEPROM 0 Data 3 EEPROM 0 Data 2 EEPROM 0 Data 1 EEPROM 0 Data 0 Default 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Write X X EEPROM 1 Data 5 EEPROM 1 Data 4 EEPROM 1 Data 3 EEPROM 1 Data 2 EEPROM 1 Data 1 EEPROM 1 Data 0 Read 0 0 EEPROM 1 Data 5 EEPROM 1 Data 4 EEPROM 1 Data 3 EEPROM 1 Data 2 EEPROM 1 Data 1 EEPROM 1 Data 0 Default 0 0 0 0 0 0 0 0 EEPROM Byte 1 Register EEPROM Byte 2 Register D7 D6 D5 D4 D3 D2 D1 D0 Write X X EEPROM 2 Data 5 EEPROM 2 Data 4 EEPROM 2 Data 3 EEPROM 2 Data 2 EEPROM 2 Data 1 EEPROM 2 Data 0 Read 0 0 EEPROM 2 Data 5 EEPROM 2 Data 4 EEPROM 2 Data 3 EEPROM 2 Data 2 EEPROM 2 Data 1 EEPROM 2 Data 0 Default 0 0 0 0 0 0 0 0 EEPROM Byte 3 Register D7 D6 D5 D4 D3 D2 D1 D0 Write X X EEPROM 3 Data 5 EEPROM 3 Data 4 EEPROM 3 Data 3 EEPROM 3 Data 2 EEPROM 3 Data 1 EEPROM 3 Data 0 Read 0 0 EEPROM 3 Data 5 EEPROM 3 Data 4 EEPROM 3 Data 3 EEPROM 3 Data 2 EEPROM 3 Data 1 EEPROM 3 Data 0 Default 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 MUX_IN Data E MUX_IN Data D MUX_IN Data C MUX_IN Data B MUX_IN Data A MUX_IN Register Read If the command byte is a MUX command byte, any additional data bytes sent after the MUX command code will not be acknowledged. If the read/write bit in the address is a logic 1, then a read operation follows and the data sent out depends on the previously stored command code. The MUX_SELECT_1 pin can function as the over-ride pin as on the PCA9559 if the non-volatile register 1 is left at all 0s. The NON_MUXED_OUT pin is a latched output. It is latched when MUX_SELECT_0 = 1. It is transparent when the MUX_SELECT_0 = 0. The data sent out on the NON_MUXED_OUT output is the 6th most significant bit of the non-volatile register. Whether this comes from the non-volatile register 0 or non-volatile register 1 depends on the command code or the external mux-select pins. After a valid I2C write operation to the EEPROM, the part cannot be addressed via the I2C for 3.6 ms. If the part is addressed prior to this time, the part will not acknowledge its address. NOTE: 1. To ensure data integrity, the non-volatile register must be internally write protected when VDD to the I2C bus is powered down or VDD to the component is dropped below normal operating levels. 2002 May 24 7 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 CONVERSION FROM THE PCA9559 TO THE PCA9561 The PCA9561 is a drop in replacement to the PCA9559 with no software modifications. The PCA9559 has only one MUX_SELECT pin to choose between the MUX_IN values and the single non-volatile register. Since the PCA9561 has two internal non-volatile registers, if Register 1 is left to all 0’s (default condition) then the MUX_SELECT_1 pin can function the same as the PCA9559 OVERIRIDE pin and MUX_SELECT_0 pin can function the same as the PCA9559 MUX_IN pin. The PCA9561 can read the MUX_IN_X values via I2C that the PACA9559 cannot do. Another difference is that the MUX_SELECT_X control pins can be overridden by I2C. To replace the PCA9559 with the PCA9561, the function table for the MUX_OUT outputs and the NON_MUXED_OUT output must stay the same and the MUX_SELECT pin functions should not be overridden by I2C. EXTERNAL CONTROL SIGNALS The Write Protect (WP) input is used to control the ability to write the content of the non-volatile registers. If the WP signal is logic 0, the I2C bus will be able to write the contents of the non-volatile registers. If the WP signal is logic 1, data will not be allowed to be written into the non-volatile registers. In this case, the slave address and the command code will be acknowledged but the following data bytes will not be acknowledged and the EEPROM is not updated. The factory default for the contents of the non-volatile register are all logic 0. These stored values can be read or written using the I2C-bus (described in the next section). The WP, MUX_IN*, and MUX_SELECT_n signals have internal pull-up resistors. See the DC and AC Characteristics for hysteresis and signal spike suppression figures. Function Table1 WP MUX_SELECT_0 COMMANDS 0 X Write to the non-volatile registers through I2C bus allowed 1 X Write to the non-volatile registers through I2C bus not allowed X 0 MUX_OUT from EEPROM byte 0–3 X 1 MUX_OUT from MUX_IN inputs NOTE: 1. This table is valid when not overridden by I2C control register. 2002 May 24 8 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 3). SDA SCL data line stable; data valid change of data allowed SW00363 Figure 3. Bit transfer Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 4). System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device initiates a transfer is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 5). SDA SDA SCL SCL S P START condition STOP condition SW00365 Figure 4. Definition of start and stop conditions SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C MULTIPLEXER SLAVE SW00366 Figure 5. System configuration 2002 May 24 9 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 Acknowledge The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition SW00368 Figure 6. Acknowledgement on the 2002 May 24 10 I2C-bus Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 Bus Transactions Data is transmitted to the PCA9561 registers using Write Byte transfers (see Figures 7 and 8). Data is read from the PCA9561 registers using Read and Receive Byte transfers (see Figure 9). control register write on EEPROM byte 0 slave address 1 S 0 1 0 1 A1 A0 0 0 A 0 0 0 0 0 EEPROM byte 0 data 0 0 X A X D5 D4 D3 D2 D1 D0 A P R/W stop condition start condition acknowledge from slave acknowledge from slave acknowledge from slave SW00956 Figure 7. WRITE on 1 EEPROM — assuming WP = 0 control register write on EEPROM byte 0 slave address S 1 0 1 0 1 A1 A0 0 A 0 0 0 0 0 0 0 EEPROM byte 1 data EEPROM byte 0 data 0 A X X D5 D4 D3 D2 D1 D0 A X X D5 D4 D3 D2 D1 D0 A P R/W start condition acknowledge from slave acknowledge from slave stop condition SW00957 Figure 8. WRITE on 2 EEPROMs — assuming WP = 0 control register read MUX_IN values slave address S 1 0 0 1 1 A1 A0 0 A 1 1 1 1 1 1 1 data from MUX_IN slave address 1 A S 1 0 0 1 1 A1 A0 1 A 0 0 0 4 3 2 1 0 NA P R/W R/W restart start condition acknowledge from master acknowledge from master acknowledge from master no acknowledge from master stop condition SW00958 Figure 9. READ MUX_IN register 2002 May 24 11 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). PARAMETER SYMBOL VDD CONDITIONS DC supply voltage VI VOUT Tstg RATING UNIT –0.5 to +4.6 V DC input voltage Note 3 –1.5 to VDD +1.5 V DC output voltage Note 3 –0.5 to VDD +0.5 V –60 to +150 °C Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER VDD DC supply voltage VIL SCL SDA SCL, MUX_IN, _ , MUX_SELECT_0 _ _ MUX_SELECT_1 MUX OUT MUX_OUT 2002 May 24 CONDITIONS LIMITS UNIT MIN MAX — 3.0 3.6 V IOL= 3 mA –0.5 0.9 V VIH IOL= 3 mA 2.7 4.0 V VOL IOL= 3 mA — 0.4 V VOL IOL= 6 mA — 0.6 V V VIL — –0.5 0.8 VIH — 2.0 4.0 V IOL — — 8 mA IOH — — 100 µA dt/dv Input transition rise or fall time — 0 10 ns/V Tamb Operating temperature — 0 70 °C 12 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 DC CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION UNIT MIN. TYP. MAX. 3 — 3.6 V Supply VDD Supply Voltage IDDL Supply Current Operating mode ALL inputs = 0 V — 0.6 1 mA IDDH Supply Current Operating mode ALL inputs = VDD — — 600 µA VPOR Power-on Reset Voltage no load; VI = VDD or GND — 2.3 2.7 V Input SCL; Input/Output SDA VIL Low Level Input Voltage –0.5 — 0.8 V VIH High Level Input Voltage 2 — VDD + 0.5 V IOL Low Level Output Current VOL = 0.4 3 — — mA IOL Low Level Output Current VOL = 0.6 6 — — mA IIH Leakage Current High VI = VDD –1 — 1 µA IIL Leakage Current Low VI = GND –1 — 1 µA CI Input Capacitance — 3 6 pF WP and Mux_Select IIH Leakage Current High VI = VDD –1 — 1 µA IIL Leakage Current Low VI = GND –20 — –50 µA CI Input Capacitance — 2.5 5 pF Mux A → F IIH Leakage Current High VI = VDD –1 — 1 mA IIL Leakage Current Low VI = GND –20 — –50 mA CI Input Capacitance — 2.5 5 pF A0 and A1 Inputs IIH Leakage Current High VI = VDD –1 — 1 µA IIL Leakage Current Low VI = GND –20 — –50 µA CI Input Capacitance — 2 4 pF Mux_Outputs VOL Low Level Output Voltage (IOL = 100 µA) — — 0.4 V VOL Low Level Output Voltage (IOL = 4 mA) — — 0.7 V IOH High Level Output Current VOH = VDD — — 100 µA NOTES: 1. VHYS is the hysteresis of Schmitt-Trigger inputs NON-VOLATILE STORAGE SPECIFICATIONS PARAMETER 2002 May 24 SPECIFICATION Memory cell data retention 10 years min Number of memory cell write cycles 3,000 cycles min 13 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 AC CHARACTERISTICS SYMBOL LIMITS PARAMETER UNIT MIN. TYP. MAX. tPLH — 28 40 ns tPHL — 8 15 ns — 30 43 ns MUX_in ⇒ MUX_out Select ⇒ MUX_out tPLH tPHL — 10 15 ns Output rise time 1.0 — 3 ns/V tF Output fall time 1.0 — 3 ns/V CL Test load capacitance on outputs — — — pF tR SYMBOL STANDARD-MODE I2C-BUS PARAMETER MIN MAX FAST-MODE I2C-BUS MIN MAX UNIT fSCL SCL clock frequency 0 100 0 400 kHz tBUF Bus free time between a STOP and START condition 4.7 — 1.3 — µs Hold time (repeated) START condition After this period, the first clock pulse is generated 4.0 — 0.6 — µs tLOW LOW period of the SCL clock 4.7 — 1.3 — µs tHIGH HIGH period of the SCL clock 4.0 — 0.6 — µs tSU;STA Set-up time for a repeated START condition 4.7 — 0.6 — µs tHD;DAT Data hold time 01 3.45 01 0.9 µs tSU;DAT Data set-up time tHD;STA 250 — 100 — ns tr Rise time of both SDA and SCL signals — 1000 20 + 0.1Cb2 300 ns tf Fall time of both SDA and SCL signals — 300 20 + 0.1Cb2 300 ns Set-up time for STOP condition 4.0 — 0.6 — µs Cb Capacitive load for each bus line — 400 — 400 pF tSP Pulse width of spikes which must be suppressed by the input filter — 50 — 50 ns tSU;STO NOTES: 1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 2. Cb = total capacitance of one bus line in pF. SDA tBUF tLOW tR tF tHD;STA tSP SCL tHD;STA P S tSU;STA tHD;DAT tHIGH tSU;DAT Sr tSU;STO P SU00645 2002 May 24 14 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 VCC MUX INPUT VM tPLZ tPHL MUX OUTPUT VO VM VOUT VIN VO PULSE GENERATOR RL D.U.T. VM RT VOL + 0.3V CL VOL Test Circuit for Open Drain Outputs SW00500 DEFINITIONS Waveform 1. Open drain output enable and disable times RL = Load resistor; 1 kΩ CL = Load capacitance includes jig and probe capacitance; 10 pF RT = Termination resistance should be equal to ZOUT of pulse generators. SW00510 2002 May 24 15 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 SO20: plastic small outline package; 20 leads; body width 7.5 mm 2002 May 24 16 SOT163-1 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 2002 May 24 17 SOT360-1 Philips Semiconductors Product data Quad 6-bit multiplexed I2C EEPROM PCA9561 Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 05-02 For sales offices addresses send e-mail to: [email protected]. Document order number: 2002 May 24 18 9397 750 09888