ETC PI6C180V

PI6C180
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Precision 1-18 Clock Buffer
Product Features
Description
• High-speed, to 125 MHz (PI6C180A)
The PI6C180 is a high-speed low-noise 1-18 noninverting buffer
designed for SDRAM clock buffer applications.
• Low-noise non-inverting 1-18 buffer
• Supports up to four SDRAM DIMMs
PI6C180 can operate up to 100 MHz, whereas PI6C180A is rated at
125 MHz.
• Low skew (< 250ps) between any two output clocks
At power up all SDRAM output are enabled and active. The I2C
Serial control may be used to individually activate/deactivate any
of the 18 output drivers.
• I2C Serial Configuration interface
• Multiple VDD, VSS pins for noise reduction
The output enable (OE) pin may be pulled low to put all outputs in a
Hi-Z state.
• 3.3V power supply voltage
• Separate Hi-Z pin for testing
• 48-pin SSOP package (V)
Note:
Purchase of I2C components from Pericom conveys a license to
use them in an I2C system as defined by Philips.
Logic Block Diagram
Product Pin Configuration
NC
NC
SDRAM0
VDD0
SDRAM0
SDRAM1
VSS0
VDD1
SDRAM2
SDRAM3
VSS1
BUF_IN
VDD2
SDRAM4
SDRAM5
VSS2
VDD3
SDRAM6
SDRAM7
VSS3
VDD4
SDRAM16
VSS4
VDDIIC
SDATA
SDRAM1
BUF_IN
SDRAM2
SDRAM3
SDRAM17
OE
SDATA
I2C
SCLOCK
I/O
1
1
2
3
4
5
6
7
8
9
10 48-Pin
11
V
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
VDD9
SDRAM15
SDRAM14
VSS9
VDD8
SDRAM13
SDRAM12
VSS8
OE
VDD7
SDRAM11
SDRAM10
VSS7
VDD6
SDRAM9
SDRAM8
VSS6
VDD5
SDRAM17
VSS5
VSSIIC
SCLOCK
PS8141C
01/18/01
PI6C180
Precision 1-18 Clock Buffer
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Product Pin Description
Pin
Symbol
Type
Qty
De s cription
4,5,8,9
SDRAM[0- 3]
O
4
SDRAM Byte 0 clock output
13,14,17,18
SDRAM[4- 7]
O
4
SDRAM Byte 1 clock output
31,32,35,36
SDRAM[8- 11]
O
4
SDRAM Byte 2 clock output
40,41,44,45
SDRAM[12- 15]
O
4
SDRAM Byte 3 clock output
21,28
SDRAM[16- 17]
O
4
SDRAM clock outputs usable for feedback
11
BUF_IN
I
1
Input for 1- 18 buffer
38
OE
I
1
Hi- Z all outputs when held LOW. Has a >100kΩ internal
pull- up resistor
24
SDATA
I/O
1
Data pin for I2C circuitry. Has a >100kΩ internal pull- up resistor
25
SCLOCK
I/O
1
Clock pin I2C circuitry. Has a >100kΩ internal pull- up resistor
3,7,12,16,20,
VDD[0- 9]
29,33,37,42,46
Power
10
3.3V power supply for SDRAM buffers
6,10,15,19,22,
VSS[0- 9]
27,30,34,39,43
Ground
10
Ground for SDRAM buffers
23
VDDIIC
Power
1
3.3V power supply for I2C circuitry
26
VSSIIC
Ground
1
Ground for I2C circuitry
1,2,47,48
NC
Reserved
4
Reserved for future modification. No connects
OE Functionality
PI6C180 Serial Configuration Map
OE
SDRAM [0-17]
Note
0
Hi- Z
1
1
BUF_IN
2
Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Used for test purposes only
2. Buffers are non-inverting
Bit
Pin #
Bit 7
18
SDRAM7
(Active/Inactive)
Bit 6
17
SDRAM6
(Active/Inactive)
Bit 5
14
SDRAM5
(Active/Inactive)
Bit 4
13
SDRAM4
(Active/Inactive)
Bit 3
9
SDRAM3
(Active/Inactive)
Bit 2
8
SDRAM2
(Active/Inactive)
Bit 1
5
SDRAM1
(Active/Inactive)
Bit 0
4
SDRAM0
(Active/Inactive)
PI6C180 I2C Address Assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0
2
De s cription
Note:
Inactive means outputs are
held LOW and are disabled
from switching.
PS8141C
01/18/01
PI6C180
Precision
1-18
Clock
Buffer
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2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock
output and test mode enable.
Each data transfer is initiated with a start condition and ended with
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW= write to addressed device). If the device’s
own address is detected, PI6C180 generates an acknowledge by
pulling SDATA line LOW during ninth clock pulse, then accepts
the following data bytes until another start or stop condition is
detected.
The PI6C180 is a slave receiver device. It can not be read back.
Sub addressing is not supported. All preceding bytes must be sent
in order to change one of the control bytes.
Every bite put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
During normal data transfers SDATA changes only when SCLOCK
is LOW. Exceptions: A HIGH to LOW transition on SDATA while
SCLOCK is HIGH indicates a “start” condition. A LOW to HIGH
transition on SDATAwhile SCLOCK is HIGH is a “stop” condition
and indicates the end of a data transfer cycle.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte, and
2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
Byte2: Optional Register for Possible Future
Requirements (1 = enable, 0 = disable)
Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
SDRAM15 (Act ive/Ina ct ive)
Bit 7
28
SDRAM17 (Act ive/Ina ct ive)
44
SDRAM14 (Act ive/Ina ct ive)
Bit 6
21
SDRAM16 (Act ive/Ina ct ive)
Bit 5
41
SDRAM13 (Act ive/Ina ct ive)
Bit 5
(Reser ved)
Bit 4
40
SDRAM12 (Act ive/Ina ct ive)
Bit 4
(Reser ved)
Bit 3
36
SDRAM11 (Act ive/Ina ct ive)
Bit 3
(Reser ved)
Bit 2
35
SDRAM10 (Act ive/Ina ct ive)
Bit 2
(Reser ved)
Bit 1
32
SDRAM9 (Act ive/Ina ct ive)
Bit 1
(Reser ved)
Bit 0
31
SDRAM8 (Act ive/Ina ct ive)
Bit 0
(Reser ved)
Bit
Pin #
Bit 7
45
Bit 6
De s cription
De s cription
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................. –65°C to +150°C
Ambient Temperature with Power Applied .............................. –0°C to +70°C
3.3V Supply Voltage to Ground Potential .............................. –0.5V to +4.6V
DC Input Voltage .................................................................... –0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
Supply Current (VDD = +3.465V, CLOAD = Max.)
Symbol
Parame te r
Te s t Condition
M in.
Typ.
M ax.
IDD
Supply Current
BUF_IN = 0 MHz
IDD
Supply Current
BUF_IN = 66.66 MHz
230
IDD
Supply Current
BUF_IN = 100.0 MHz
360
Units
3
3
mA
PS8141C
01/18/01
PI6C180
Precision 1-18 Clock Buffer
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DC Operating Specifications (VDD = +3.3V ±5%, TA = 0°C - 70°C)
Symbol
Parame te r
Te s t Condition
M in.
M ax.
Units
VDD
2.0
VDD +0.3
VSS - 0.3
0.8
0 < VIN < VDD
-5
+5
2.4
Input Voltage
VIH
Input high voltage
VIL
Input low voltage
IIL
Input leakage current
V
mA
VDD[0-9] = 3.3V ±5%
VOH
Output high voltage
IOH = - 1mA
VOL
Output low voltage
IOL = 1mA
COUT
Output pin capacitance
6
CIN
Input pin capacitance
5
LPIN
Pin Inductance
7
nH
70
°C
TA
V
0.4
pF
Ambient Temperature
No Airflow
0
SDRAM Clock Buffer Operating Specification
Symbol
Parame te r
Te s t Conditions M in. Typ.
IOHMIN
Pull- up current
VOUT = 2.0V
IOHMAX
Pull- up current
VOUT = 3.135V
IOLMIN
Pull- down current
VOUT = 1.0V
IOLMAX
Pull- down current
VOUT = 0.4V
tRHSDRAM
Output rise edge rate
SDRAM only
3.3V ±5%
@04V- 2.4V
1.5
tTHSDRAM
Output fall edge rate
SDRAM only
3.3V ±5%
@2.4V- 0.4V
1.5
M ax.
Units
- 46
mA
- 54
54
53
4
V/ns
4
AC Timing
PI6C180A
Symbol
Parame te r
66 M Hz
100 M Hz
133 M Hz
M in.
M a x.
M in.
M ax.
M in.
M ax.
15.5
10.0
10.5
7.5
7.8
Units
tSDKP
SDRAM CLK period
15.0
tSDKH
SDRAM CLK high time
5.6
3.3
1.0
tSDKL
SDRAM CLK low time
5.3
3.1
1.0
tSDRISE
SDRAM CLK rise time
1. 5
4.0
1.5
4.0
1.5
4.0
tSDFALL
SDRAM CLK fall time
1.5
4.0
1.5
4.0
1.5
4.0
tPLH
SDRAM Buffer LH prop delay
1.0
5.0
1.0
5.0
1.0
5.0
tPHL
SDRAM Buffer HL prop delay
1. 0
5.0
1.0
5.0
1.0
5.0
tPZL,tPZH
SDRAM Buffer Enable delay
1.0
8.0
1.0
8.0
1.0
8.0
tPLZ,tPHZ
SDRAM Buffer Disable delay
1.0
8.0
1.0
8.0
1.0
8.0
Duty Cycle
Measured at 1.5V
45
55
45
55
45
55
%
tSDSKW
SDRAM Output to Output Skew
250
ps
ns
V/ns
ns
250
250
4
PS8141C
01/18/01
PI6C180
Precision
1-18
Clock
Buffer
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Test
Output
Point
Buffer
Test Load
tSDKP
tSDKH
3.3V
Clocking
Interface
(TTL)
2.4
1.5
0.4
tSDKL
tSDRISE
Input
tSDFALL
1.5V
1.5V
Waveform
tphl
tplh
Output
1.5V
Waveform
1.5V
Figure 1. Clock Waveforms
Minimum and Maximum Expected Capacitive Loads
Clock
SDRAM
M in. Load M ax. Load
20
30
Units
Note s
pF
SDRAM DIMM Specification
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall
time are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
5
PS8141C
01/18/01
PI6C180
Precision 1-18 Clock Buffer
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PCB Layout Suggestion
1
48
2
47
3
46
4
45
5
44
VSS
6
43
VSS
VDD
7
42
VDD
8
41
9
40
10
39
11
38
12
37
13
36
14
35
VSS
15
34
VSS
VDD
16
33
VDD
17
32
18
31
VSS
19
30
VSS
VDD
20
29
VDD
21
28
VSS
22
27
VSS
VDD
23
26
VSS
24
25
C1
VDD
C2
VSS
C3
VDD
C4
C5
C6
C11
VDD
Ferrite Bead
VCC
C12
C10
22uF
VSS
C9
VDD
C8
C7
Via to GND Plane
Via to VDD Plane
Void in Power Plane
Note:
This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C1-C11 should be placed as close as possible
to their respective VDD.
Recommended capacitor values:
C1-C11 .............. 0.1µF, ceramic
C12 ................. 22µF
6
PS8141C
01/18/01
PI6C180
Precision
1-18
Clock
Buffer
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PI6C180
100/66 MHz
Clock from
18
22
Ω
SDRAM
SDRAM
DIMM
CI
Chipset
Spec.
Figure 2. Design Guidelines
48-Pin SSOP Package Data
48
.291
.299
7.39
7.59
.395
.420
10.03
10.67
Gauge Plane
.010 0.25
.02 0.51
.04 1.01
1
.620
.630
15.75
16.00
.015 0.381 x 45˚
.025 0.635
.008
0.20
Nom.
.110 2.79 Max
.008 0.20
.0135 0.34
.025 BSC
0.635
.008 0.20
.016 0.40
0-8˚
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Table of Dimensions
Body
E (Width)
D (Le ngth)
A (He ight)
e (Pin-to-Pin pitch)
48 pins
Min.
0.291
0 .6 2 0
0.095
0.025
(300 mil)
Ma x.
0.299
0.630
0.110
-
Ordering Information
P/N
De s cription
PI6C180V
48- pin SSOP Package
PI6C180AV
48- pin SSOP Package
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
7
PS8141C
01/18/01