ETC TPS2301PWR

TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
features
D
D
D
D
D
D
D
D
D
D
D OR PW PACKAGE
(TOP VIEW)
Single-Channel High-Side MOSFET Driver
Input Voltage: 3 V to 13 V
Inrush Current Limiting With dv/dt Control
Circuit-Breaker Control With Programmable
Current Limit and Transient Timer
Power-Good Reporting With Transient
Filter
CMOS- and TTL-Compatible Enable Input
Low 5-µA Standby Supply Current . . . Max
Available in 14-Pin SOIC and TSSOP
Package
– 40°C to 85°C Ambient Temperature Range
Electrostatic Discharge Protection
1
2
3
4
5
6
7
GATE
DGND
TIMER
VREG
VSENSE
AGND
ISENSE
14
13
12
11
10
9
8
DISCH
ENABLE
PWRGD
FAULT
ISET
AGND
IN
NOTE: Terminal 13 is active high on TPS2331.
typical application
VO
+
VIN
3 V – 13 V
IN
ISET
ISENSE
DISCH
GATE
VSENSE
VREG
applications
D
D
D
AGND
Hot-Swap/Plug/Dock Power Management
Hot-Plug PCI, Device Bay
Electronic Circuit Breaker
TPS2330
PWRGD
DGND
FAULT
TIMER
ENABLE
description
The TPS2330 and TPS2331 are single-channel hot-swap controllers that use external N-channel MOSFETs
as high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP),
inrush-current control, output-power status reporting, and separation of load transients from actual load
increases, are critical requirements for hot-swap applications.
The TPS2330/31 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure
the device is off at start-up and confirm the status of the output voltage rails during operation. An internal charge
pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel
MOSFETs. The charge pump controls both the rise times and fall times (dv/dt) of the MOSFETs, reducing power
transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent
conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during
power-state transitions, to disregard transients for a programmable period.
AVAILABLE OPTIONS
TA
– 40°C to 85°C
PACKAGES
PIN
COUNT
ENABLE
ENABLE
Dual-channel with independent OCP and adjustable PG
20
TPS2300IPW
TPS2301IPW
Dual-channel with interdependent OCP and adjustable PG
20
TPS2310IPW
TPS2311IPW
Dual-channel with independent OCP
16
TPS2320ID
TPS2320IPW
TPS2321ID
TPS2321IPW
Single-channel with OCP and adjustable PG
14
TPS2330ID
TPS2330IPW
TPS2331ID
TPS2331IPW
HOT SWAP CONTROLLER DESCRIPTION
HOT-SWAP
† The packages are available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TPS2331IPWR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
functional block diagram
IN
ISET
ISENSE
GATE
PREREG
VREG
DISCH
Clamp
dv/dt Rate
Protection
50 µA
Charge
Pump
Circuit
Breaker
Pulldown FET
Circuit Breaker
UVLO and
Power-Up
AGND
75 µA
VSENSE
PWRGD
20-µs Deglitch
DGND
ENABLE
FAULT
Logic
50-µs Deglitch
TIMER
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
6,9
I
Analog ground, connects to DGND as close as possible
DGND
2
I
Digital ground
DISCH
14
O
Discharge transistor
ENABLE/ ENABLE
13
I
Active low (TPS2330) or active high enable (TPS2331)
FAULT
11
O
Overcurrent fault, open-drain output
GATE
1
O
Connects to gate of high-side MOSFET
IN
8
I
Input voltage
ISENSE
7
I
Current-sense input
ISET
10
I
Adjusts circuit-breaker threshold with resistor connected to IN
PWRGD
12
O
Open-drain output, asserted low when VSENSE voltage is less than reference.
TIMER
3
O
Adjusts circuit-breaker deglitch time
VREG
4
O
Connects to bypass capacitor, for stable operation
VSENSE
5
I
Power-good sense input
2
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TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
detailed description
DISCH – DISCH should be connected to the source of the external N-channel MOSFET transistor connected
to GATE. This pin discharges the load when the MOSFET transistor is disabled. They also serve as
reference-voltage connection for internal gate-voltage-clamp circuitry.
ENABLE or ENABLE – ENABLE for TPS2330 is active low. ENABLE for TPS2331 is active high. When the
controller is enabled, GATE voltage will power up to turn on the external MOSFETs. When the ENABLE pin is
pulled high for TPS2330 or the ENABLE pin is pulled low for TPS2331 for more than 50 µs, the gate of the
MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the
output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when
enabled and shuts down PREREG when disabled so that total supply current is much less than 5 µA.
FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition is sustained long
enough to charge TIMER to 0.5 V, the device latches off and pulls FAULT low.
GATE – GATE connects to the gate of the external N-channel MOSFET transistor. When the device is enabled,
internal charge-pump circuitry pulls this pin up by sourcing approximately 15 µA. The turnon slew rates depend
upon the capacitance present at the GATE terminal. If desired, the turnon slew rates can be further reduced
by connecting capacitors between this pin and ground. These capacitors also reduce inrush current and protect
the device from false overcurrent triggering during powerup. The charge-pump circuitry will generate
gate-to-source voltages of 9 V–12 V across the external MOSFET transistor.
IN – IN should be connected to the power source driving the external N-channel MOSFET transistor connected
to GATE. The TPS2330/31 draws its operating current from IN, and will remain disabled until the IN power supply
has been established. The device has been constructed to support 3-V, 5-V, or 12-V operation.
ISENSE, ISET – ISENSE in combination with ISET implements overcurrent sensing for GATE. ISET sets the
magnitude of the current that generates an overcurrent fault, through a external resistor connected to ISET. An
internal current source draws 50 µA from ISET. With a sense resistor from IN to ISENSE, which is also connected
to the drain of the external MOSFET, the voltage on the sense resistor reflects the load current. An overcurrent
condition is assumed to exist if ISENSE is pulled below ISET.
PWRGD – PWRGD signals the presence of undervoltage conditions on VSENSE. The pin is an open-drain
output and is pulled low during an undervoltage condition. To minimize erronous PWRGD responses from
transients on the voltage rail, the voltage sense circuit incorporates a 20-µs deglitch filter. When VSENSE is
lower than the reference voltage (about 1.23 V), PWRGD will be active low to indicate an undervoltage condition
on the power-rail voltage.
TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning
off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which
charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker
latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled
to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly
recommended from TIMER to ground, to prevent any false triggering.
VREG – The VREG pin is the output of an internal low-dropout voltage regulator. This regulator draws current
from IN. A 0.1-µF ceramic capacitor should be connected between VREG and ground. VREG can be connected
to IN or to a separated power supply through a low-resistance resistor. However, the voltage on VREG must
be less than 5.5 V.
VSENSE – VSENSE can be used to detect undervoltage conditions on external circuitry. If VSENSE senses
a voltage below approximately 1.23 V, PWRGD is pulled low.
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3
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Input voltage range: VI(IN), VI(ISENSE), VI(VSENSE),VI(ISET), VI(ENABLE) . . . . . . . . . . . . . . . –0.3 V to 15 V
Output voltage range: VO(GATE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V
VO(DISCH), VO(PWRGD), VO(FAULT), VO(VREG), VO(TIMER) . . . . . . . –0.3 V to 15V
Sink current range: IGATE, IDISCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 100 mA
IPWRGD, ITIMER, IFAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 10 mA
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are respect to DGND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PW-14
755 mW
10.07 mW/°C
302 mW
151 mW
D-14
613 mW
8.18 mW/°C
245 mW
123 mW
recommended operating conditions
MIN
Input voltage, VI
NOM
MAX
UNIT
VI(IN), VI(ISENSE), VI(VSENSE), VI(ISET)
VREG voltage, VO(VREG), when VREG is directly connected to IN
3
13
V
2.95
5.5
V
Operating virtual junction temperature, TJ
–40
100
°C
4
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TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
electrical characteristics over recommended operating temperature range (–40°C < TA < 85°C),
3 V ≤ VI(IN) ≤13 V (unless otherwise noted)
general
PARAMETER
TEST CONDITIONS
II(IN)
Input current
current, IN
VI(ENABLE) = 5 V (TPS2331),
VI(ENABLE) = 0 V (TPS2330)
II(stby)
Standby current (sum of currents into IN ISENSE and ISET)
VI(ENABLE) = 0 V (TPS2331),
VI(ENABLE) = 5 V (TPS2330)
MIN
TYP
MAX
0.5
1
75
200
5
UNIT
mA
µA
GATE
PARAMETER
TEST CONDITIONS
VG(GATE_3V)
VG(GATE_4.5V)
VI(IN) = 3 V
II(GATE) = 500 nA,
nA
DISCH o
en
open
Gate voltage
VG(GATE_10.8V)
MIN
TYP
MAX
UNIT
9
11.5
VI(IN) = 4.5 V
10.5
14.5
VI(IN) = 10.8 V
16.8
21
9
10
12
V
V
VC(GATE)
Clamping voltage, GATE to
DISCH
IS(GATE)
Source current, GATE
3 V ≤ VI(IN) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE) = VI(IN) + 6 V
10
14
20
µA
Sink current, GATE
3 V ≤ VI(IN) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE) = VI(IN)
50
75
100
µA
Rise time, GATE
Cg to GND = 1 nF (see Note 2)
tr(GATE)
(
)
VI(IN) = 3 V
VI(IN) = 4.5 V
0.5
VI(IN) = 10.8 V
VI(IN) = 3 V
tf(GATE)
(
)
Fall time, GATE
Cg to GND = 1 nF (see Note 2)
ms
0.6
1
0.1
VI(IN) = 4.5 V
VI(IN) = 10.8 V
ms
0.12
0.2
NOTE 2: Specified, but not production tested.
TIMER
PARAMETER
VOT(TIMER)
TEST CONDITIONS
Threshold voltage, TIMER
Charge current, TIMER
VI(TIMER) = 0 V
VI(TIMER) = 1 V
Discharge current, TIMER
MIN
TYP
MAX
0.4
0.5
0.6
UNIT
35
50
65
1
2.5
MIN
TYP
MAX
50
60
mV
0.1
5
µA
V
µA
mA
circuit breaker
PARAMETER
VIT(CB)
IIB(ISENSE)
tpd(CB)
TEST CONDITIONS
Undervoltage voltage, circuit breaker
RISET = 1 kΩ
40
Input bias current, ISENSE
Discharge current,
current GATE
VO(GATE) = 4 V
VO(GATE) = 1 V
Propagation (delay) time, comparator inputs to
gate output
Cg = 50 pF,
(50% to 10%)
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10 mV overdrive,
CO(timer) = 50 pF
• DALLAS, TEXAS 75265
400
800
25
150
1.3
UNIT
mA
µs
5
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
electrical characteristics over recommended operating temperature range (–40°C < TA < 85°C),
3 V ≤ VI(IN) ≤13 V (unless otherwise noted) (continued)
ENABLE, active low (TPS2330)
PARAMETER
VIH(ENABLE)
VIL(ENABLE)
TEST CONDITIONS
MIN
High-level input voltage, ENABLE
TYP
MAX
2
V
Low-level input voltage, ENABLE
RI(ENABLE)
Input pullup resistance,
ENABLE
See Note 3
td_off(ENABLE)
Turnoff delay time, ENABLE
VI(ENABLE) increasing above stop threshold; 100
ns rise time, 20 mV overdrive (see Note 2)
td_on(ENABLE)
Turnon delay time, ENABLE
VI(ENABLE) decreasing below start threshold;
100 ns fall time, 20 mV overdrive (see Note 2)
100
UNIT
200
0.8
V
300
kΩ
60
µs
125
µs
NOTES: 2. Specified, but not production tested.
3. Test IO of ENABLE at VI(ENABLE) = 1 V and 0 V, then RI(ENABLE) =
I
* O_1V
1 V
I
O_ 0V
ENABLE, active high (TPS2331)
PARAMETER
VIH(ENABLE)
VIL(ENABLE)
TEST CONDITIONS
High-level input voltage, ENABLE
MIN
TYP
MAX
2
UNIT
V
Low-level input voltage, ENABLE
0.7
V
300
kΩ
RI(ENABLE)
Input pulldown resistance,
ENABLE
td_on(ENABLE)
Turnon delay time, ENABLE
VI(ENABLE) increasing above start threshold;
100 ns rise time, 20 mV overdrive (see Note 2)
85
µs
td_off(ENABLE)
Turnoff delay time, ENABLE
VI(ENABLE) decreasing below stop threshold;
100 ns fall time, 20 mV overdrive (see Note 2)
100
µs
100
150
NOTE 2: Specified, but not production tested.
PREREG
PARAMETER
TEST CONDITIONS
VREG
PREREG output voltage
4.5 ≤ VI(IN) ≤ 13 V
Vdrop_PREREG
PREREG dropout voltage
VI(IN) = 3 V
MIN
TYP
MAX
3.5
4.1
5.5
UNIT
V
0.1
V
VREG UVLO
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.95
V
VOT(UVLOstart)
VOT(UVLOstop)
Output threshold voltage, start
2.75
2.85
Output threshold voltage, stop
2.65
2.78
Vhys(UVLO)
Hysteresis
50
75
UVLO sink current, GATE
VI(GATE) = 2 V
6
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10
V
mV
mA
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
electrical characteristics over recommended operating temperature range (–40°C < TA < 85°C),
3 V ≤ VI(IN1) ≤13 V, 3 V ≤ VI(IN2) ≤ 5.5 V (unless otherwise noted) (continued)
PWRGD
PARAMETER
TEST CONDITIONS
VIT(ISENSE)
Trip threshold, VSENSE
VI(VSENSE) decreasing
Vhys
Hysteresis voltage, power-good
comparator
VO(sat)(PWRGD)
VO(VREGmin)
Output saturation voltage PWRGD
IIB
Ilkg(PWRGD)
Input bias current, power-good comparator
Minimum VO(VREG) for valid power-good
Leakage current, PWRGD
tdr
Delay time, rising edge, PWRGD
tdf
Delay time, falling edge, PWRGD
MIN
TYP
MAX
UNIT
1.2
1.225
1.25
V
20
30
40
mV
0.2
0.4
V
IO = 2 mA
IO = 100 µA, VO(PWRGD) = 1 V
VI(VSENSE) = 5.5 V
VO(PWRGD) = 13 V
VI(VSENSE) increasing,
Overdrive = 20 mV, tr = 100 ns,
See Note 2
VI(VSENSE) decreasing,
Overdrive = 20 mV, tr = 100 ns,
See Note 2
1
V
1
µA
1
µA
25
µs
2
µs
NOTE 2: Specified, but not production tested.
FAULT output
PARAMETER
VO(sat)(FAULT)
Ilkg(FAULT)
TEST CONDITIONS
Output saturation voltage, FAULT
Leakage current, FAULT
MIN
TYP
IO = 2 mA
VO(FAULT) = 13 V
MAX
UNIT
0.4
V
1
µA
DISCH
PARAMETER
TEST CONDITIONS
IDISCH
VIH(DISCH)
Discharge current, DISCH
VI(DISCH) = 1.5 V, VI(VIN) = 5 V
VIL(DISCH)
Discharge on low-level input voltage
Discharge on high-level input voltage
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MIN
TYP
5
10
MAX
mA
2
V
1
• DALLAS, TEXAS 75265
UNIT
V
7
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
Load 12 Ω
Load 12 Ω
VI(ENABLE)
5 V/div
VI(ENABLE)
5 V/div
VO(GATE)
10 V/div
VO(DISCH)
5 V/div
VO(GATE)
10 V/div
VO(DISCH)
5 V/div
t – Time – 10 ms/div
Figure 1. Turnon Voltage Transition
No Capacitor
on Timer
VI(ENABLE)
5 V/div
t – Time – 10 ms/div
Figure 2. Turnoff Voltage Transition
VI(ENABLE)
5 V/div
VO(GATE)
10 V/div
No Capacitor
on Timer
VO(GATE)
10 V/div
VO(FAULT)
10 V/div
VO(FAULT)
10 V/div
IO(OUT)
2 A/div
IO(OUT)
2 A/div
t – Time – 1 ms/div
t – Time – 5 ms/div
Figure 3. Overcurrent Response: Enabled
Into Overcurrent Load
8
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Figure 4. Overcurrent Response: an Overcurrent
Load Plugged Into the Enabled Board
• DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
No Capacitor
on Timer
VI(ENABLE)
5 V/div
No Capacitor
on Timer
VI(IN)
10 V/div
VO(GATE)
10 V/div
VO(GATE)
10 V/div
VO(FAULT)
10 V/div
VO(OUT)
10 V/div
IO(IN)
2 A/div
IO(OUT)
1 A/div
t – Time – 1 ms/div
t – Time – 5 ms/div
Figure 5. Enabled Into Short Circuit
Figure 6. Hot Plug
VI(IN)
10 V/div
No Capacitor
on Timer
VO(GATE)
10 V/div
VO(OUT)
10 V/div
IO(OUT)
1 A/div
t – Time – 1 ms/div
Figure 7. Hot Removal
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9
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT (ENABLED)
vs
VOLTAGE
SUPPLY CURRENT (DISABLED)
vs
VOLTAGE
52
15
IN = 5 V to 13 V
51
TA = 85°C
14
TA = 25°C
13
TA = 25°C
49
I I – Input Current – nA
I I – Input Current – µ A
50
48
47
TA = 0°C
46
TA = –40°C
TA = –40°C
12
TA = 0°C
11
10
45
9
44
8
43
7
4
5
6
7
8
9
10 11
VI– Input Voltage – V
12
13
14
4
5
6
7
8
9
10 11
VI – Input Voltage – V
13
14
9
3
6
CL(GATE) – GATE Load Capacitance – nF
12
GATE VOLTAGE
vs
INPUT VOLTAGE
GATE VOLTAGE RISE TIME
vs
GATE LOAD CAPACITANCE
22
20
18
IN = 12 V
TA = 25°C
TA = 85°C
TA = 25°C
TA = 0°C
18
TA = –40°C
16
14
12
10
2
3
4
9
5
6
7
8
VI – Input Voltage – V
10
11
12
t r – GATE Voltage Rise Time – ms
CL(GATE) = 1000 pF
12
Figure 9
Figure 8
VO – GATE Output Voltage – V
TA = 85°C
IN = 5 V to 13 V
15
12
9
6
3
0
0
Figure 10
10
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Figure 11
• DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
TYPICAL CHARACTERISTICS
GATE VOLTAGE FALL TIME
vs
GATE LOAD CAPACITANCE
GATE OUTPUT CURRENT
vs
GATE VOLTAGE
4
15
14.5
3
I – GATE Current – µ A
– GATE Voltage Fall Time
IN = 12 V
TA = 25°C
2
1
14
TA = –40°C
13.5
TA = 85°C
TA = 25°C
13
TA = 0°C
12.5
tf
12
IN = 13 V
11.5
0
0
3
6
9
11
12
14 15
CL(GATE) – GATE Load Capacitance – nF
16
17 18 19 20 21
V – GATE Voltage
Figure 12
23
24
Figure 13
CIRCUIT-BREAKER RESPONSE
vs
TIMER CAPACITANCE
LOAD VOLTAGE DISCHARGE TIME
vs
LOAD CAPACITANCE
12
320
IN = 12 V
TA = 25°C
IN = 12 V
IO = 0 A
TA = 25°C
280
9
t – Discharge Time – ms
t res – Circuit Braker Response Time –µ s
22
6
3
240
200
160
120
80
40
0
0
0.2
0.4
0.6
0.8
C(timer) – TIMER Capacitance – nF
1
0
0
Figure 14
500
Figure 15
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400
100
200
300
CL – Load Capacitance – µF
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11
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
TYPICAL CHARACTERISTICS
UVLO START AND STOP THRESHOLDS
vs
TEMPERATURE
PWRGD THRESHOLD
vs
TEMPERATURE
1.27
2.88
2.86
Start
2.84
2.82
2.8
2.78
Stop
2.76
2.74
2.72
2.7
–45–35–25–15 –5 5 15 25 35 45 55 65 75 85 95
TA – Temperature – °C
VIT – Input Threshold Voltage PWRGD – V
V ref – Reference Voltage UVLO Threshold – V
2.9
1.26
1.25
1.24
1.23
Down
1.22
1.21
1.20
–45–35–25 –15 –5 5 15 25 35 45 55 65 75 85 95
TA – Temperature – °C
Figure 17
Figure 16
12
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TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
APPLICATION INFORMATION
typical application diagram
This diagram shows a typical dual hot-swap application. The pullup resistors at PWRGD and Fault should be
relatively large (e.g. 100 kΩ) to reduce power loss unless they are required to drive a large load.
System
Board
RSENSE
3 V ∼ 13 V IN
1 µF ∼ 10 µF
+
RVSENSE_TOP
VO
RISET
RVSENSE_BOTTOM
0.1 µF
VREG IN ISET
ENABLE
ENABLE
DGND
AGND
ISENSE GATE DISCH VSENSE
TPS2331
FAULT
PWRGD
FAULT
PWRGD
TIMER
Figure 18. Typical Hot-Swap Application
input capacitor
A 0.1-µF ceramic capacitor in parallel with a 1-µF ceramic capacitor should be placed on the input power
terminals near the connector on the hot-plug board to help stabilize the voltage rails on the cards. The
TPS2330/31 does not need to be mounted near the connector or these input capacitors. For applications with
more severe power environments, a 2.2-µF or higher ceramic capacitor is recommended near the input
terminals of the hot-plug board. A bypass capacitor for IN should be placed close to the device.
output capacitor
A 0.1-µF ceramic capacitor is recommended per load on the TPS2330/31; these capacitors should be placed
close to the external FETs and to TPS2330/31. A larger bulk capacitor on the load is also recommended. The
value of the bulk capacitor should be selected based on the power requirements and the transients generated
by the application.
external FET
To deliver power from the input sources to the loads, the controller needs an external N-channel MOSFET. A
few widely used MOSFETs are shown in Table 1. But many other MOSFETs on the market can also be used
with TPS23xx in hot-swap systems.
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TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
APPLICATION INFORMATION
Table 1. Some Available N-Channel MOSFETs
CURRENT RANGE
(A)
PART NUMBER
0 to 2
2 to 5
5 to 10
DESCRIPTION
MANUFACTURER
IRF7601
N-channel, rDS(on) = 0.035 Ω, 4.6 A, Micro-8
International Rectifier
MTSF3N03HDR2
N-channel, rDS(on) = 0.040 Ω, 4.6 A, Micro-8
ON Semiconductor
IRF7101
Dual N-channel, rDS(on) = 0.1 Ω, 2.3 A, SO-8
International Rectifier
MMSF5N02HDR2
Dual N-channel, rDS(on) = 0.04 Ω, 5 A, SO-8
ON Semiconductor
IRF7401
N-channel, rDS(on) = 0.022 Ω, 7 A, SO-8
International Rectifier
MMSF5N02HDR2
N-channel, rDS(on) = 0.025 Ω, 5 A, SO-8
ON Semiconductor
IRF7313
Dual N-channel, rDS(on) = 0.029 Ω, 5.2 A, SO-8
International Rectifier
SI4410
N-channel, rDS(on) = 0.020 Ω, 8 A, SO-8
Vishay Dale
IRLR3103
N-channel, rDS(on) = 0.019 Ω, 29 A, d-Pak
International Rectifier
IRLR2703
N-channel, rDS(on) = 0.045 Ω, 14 A, d-Pak
International Rectifier
timer
For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. This
capacitor should be connected between TIMER and ground. The presence of an overcurrent condition on of
the TPS2330/31 causes a 50-µA current source to begin charging this capacitor. If the overcurrent condition
persists until the capacitor has been charged to approximately 0.5 V, the TPS2330/31 will latch off the transistor
and will pull the FAULT pin low. The timer capacitor can be made as large as desired to provide additional time
delay before registering a fault condition.
output-voltage slew-rate control
When enabled, the TPS2330/TPS2331 controllers supply the gate of an external MOSFET transistor with a
current of approximately 15 µA. The slew rate of the MOSFET source voltage is thus limited by the gate-to-drain
capacitance Cgd of the external MOSFET capacitor to a value approximating:
dvs
dt
+ 15C mA
gd
If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external
MOSFET and ground.
VREG capacitor
The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-µF
or 0.22-µF ceramic capacitor is recommended.
14
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TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
APPLICATION INFORMATION
gate drive circuitry
The TPS2330/TPS2331 includes four separate features associated with each gate-drive terminal:
D
A charging current of approximately 15 µA is applied to enable the external MOSFET transistor. This current
is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH)
of 9 V–12 V. DISCH must be connected to the external MOSFET source terminal to ensure proper operation
of this circuitry.
D
A discharge current of approximately 75 µA is applied to disable the external MOSFET transistor. Once the
transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO
discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while
ensuring that the gate of the external MOSFET transistor remain at a low voltage.
D
D
During a UVLO condition, the gate of the MOSFET transistor is pulled down by an internal PMOS transistor.
This transistor continues to operate even if the voltage at IN is 0 V. This circuitry also helps hold the external
MOSFET transistor off when power is suddenly applied to the system.
During an overcurrent fault condition, the external MOSFET transistor that exhibited an over-current
condition will be rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at
4 V) from the pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and
the UVLO driver is enabled instead.
setting the current-limit circuit-breaker threshold
The current sensing resistor RISENSE and the current limit setting resistor RISET determine the current limit of
the channel, and can be calculated by the following equation:
I LMT
+ RISETR
10 –6
50
ISENSE
Typically RISENSE is usually very small (0.001 Ω to 0.1 Ω). If the trace and solder-junction resistances between
the junction of RISENSE and ISENSE and the junction of RISENSE and RISET are greater than 10% of the RISENSE
value, then these resistance values should be added to the RISENSE value used in the calculation above.
Table 2 shows some of the current sense resistors available in the market.
Table 2. Some Current Sense Resistors
CURRENT RANGE
(A)
PART NUMBER
DESCRIPTION
0 to 1
WSL-1206, 0.05 1%
0.05 Ω, 0.25 W, 1% resistor
1 to 2
WSL-1206, 0.025 1%
0.025 Ω, 0.25 W, 1% resistor
2 to 4
WSL-1206, 0.015 1%
0.015 Ω, 0.25 W, 1% resistor
4 to 6
WSL-2010, 0.010 1%
0.010 Ω, 0.5 W, 1% resistor
6 to 8
WSL-2010, 0.007 1%
0.007 Ω, 0.5 W, 1% resistor
8 to 10
WSR-2, 0.005 1%
0.005 Ω, 0.5 W, 1% resistor
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MANUFACTURER
Vishay Dale
15
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
APPLICATION INFORMATION
setting the power-good threshold voltage
The two feedback resistors RVSENSE_TOP and RVSENSE_BOT connected between VO and ground form a
resistor divider setting the voltage at the VSENSE pins. VSENSE voltage equals to
VI(SENSE) = VO × RVSENSE_BOT/(RVSENSE_TOP + RVSENSE_BOT)
This voltage is compared to an internal voltage reference (1.225 V ±2%) to determine whether the output voltage
level is within a specified tolerance. For example, given a nominal output voltage at VO, and defining VO_min
as the minimum required output voltage, then the feedback resistors are defined by:
R VSENSE_TOP
+
V O_min
* 1.225
1.225
R VSENSE_BOT
Start the process by selecting a large standard resistor value for RVSENSE_BOT to reduce power loss. Then
RVSENSE_TOP can be calculated by inserting all of the known values into the equation above. When VO is lower
than VO_min, PWRGD will be low as long as the controller is enabled.
undervoltage lockout (UVLO)
The TPS2330/TPS2331 includes an undervoltage lockout (UVLO) feature that monitors the voltage present on
the VREG pin. This feature will disable the external MOSFET if the voltage on VREG drops below 2.78 V
(nominal) and will re-enable normal operation when it rises above 2.85 V (nominal). Since VREG is fed from
IN through a low-dropout voltage regulator, the voltage on VREG will track the voltage on IN within 50 mV. While
the undervoltage lockout is engaged, GATE is held low by an internal PMOS pulldown transistor, ensuring that
the external MOSFET transistor remain off at the times, even if the power supply has fallen to 0 V.
power-up control
The TPS2330/TPS2331 includes a 500 µs (nominal) startup delay that ensures that internal circuitry has
sufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered only
upon the rapid application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockout
circuitry will provide adequate protection against undervoltage operation.
3-channel hot-swap application
Some applications require hot-swap control of up to three voltage rails, but may not explicitly require the sensing
of the status of the output power on all three of the voltage rails. One such application is device bay, where dv/dt
control of 3.3 V, 5 V, and 12 V is required. By using TPS2330/TPS2331 to drive all three power rails, as is shown
below, TPS2330/31 can deliver three different voltages to three loads while monitoring the status of one of the
loads.
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TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
APPLICATION INFORMATION
System
Board
3.3 V IN2
1 µF ∼ 10 µF
+
VO2
Rg2
Rg3
5 V IN3
1 µF ∼ 10 µF
+
VO3
RSENSE
12 V IN1
1 µF ∼ 10 µF
+
RVSENSE_TOP
VO1
RISET
RVSENSE_BOTTOM
Rg1
0.1 µF
Vreg IN ISET
ISENSE GATE
ENABLE
DGND
AGND
ENABLE
DISCH VSENSE
FAULT
PWRGD
TPS2331
FAULT
PWRGD
TIMER
Figure 19. Three-Channel Application
Figure 29 shows ramp-up waveforms of the three output voltages.
VO – Output Voltage – 2 V/div
VO1
VO3
VO2
t – Time – 2.5 ms/div
Figure 20
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17
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
18
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TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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19
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  2000, Texas Instruments Incorporated
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