ETC U4091BM-MFN

U4091BM
Programmable Telephone Audio Processor
Description
The programmable telephone audio processor U4091BM
is a linear integrated circuit for use in feature phones,
answering machines and fax machines. It contains the
speech circuit, tone-ringer interface with DC/DC
converter, sidetone equivalent and ear-protection
rectifiers. The circuit is line-powered and contains all
components necessary for signal amplification and
adaptation to the line. The U4091BM can also be supplied
via an external power supply. An integrated voice switch
with loudspeaker amplifier enables hands-free or
loudhearing operation. With an anti-feedback function,
acoustical feedback during loudhearing can be reduced
significantly. The generated supply voltage is suitable for
a wide range of peripheral circuits.
Features
Benefits
D Speech circuit with anti-clipping
D No piezoelectric transducer for tone ringing necessary
D Tone-ringer interface with DC/DC converter
D Complete system integration of analog signal processing on one chip
D Speaker amplifier with anti-distortion
D Power-supply management (regulated, unregulated)
and a special supply for electret microphone
D Voice switch
D Interface for answering machine and cordless phone
D Very few external components
Applications
Feature phone, answering machine, fax machine, speaker
phone, cordless phone
Block Diagram
Speech
circuit
Voice
switch
Audio
amplifier
Clock
Data
Reset
Serial
bus
MCU
Tone
ringer
DTMF
Ordering Information
Extended Type Number
Package
U4091BM-MFN
SSO44
U4091BM-MFNG3
SSO44
Rev. A3, 27-Oct-00
Remarks
Taped and reeled
1 (32)
2
43
44
1
39
42
38
9
10
8
17
TXACL
15
5
Power
supply
STBAL
16
4
12
AGATX
3
11
MICRO
AGARX
V MIC
TXA
30
Figure 1. Detailed block diagram
Offset
canceler
40
DTMF/
melody
22
Offset
canceler
Filter
AGCO
AMPB
LRX
DTMF
MIC
21
Ringing
power
converter
MUX
19
ADC
AGCI
AMREC
EPO RXLS
V RING
20
Switch matrix
AGC
LTX
LIDET
VMP
RFDO
41
7
6
18
REG
POR
BIDIR
serial
bus
1/8/16/32
DIV.
RA
AFS
control
SACL
SA
OSC.
3.58 MHz
Rev. A3, 27-Oct-00
14
13
35 34
37
36 33
31
32
24 25 23
26
27 29 28
µC
RECO1
MICO
V MP
U4091BM
Detailed Block Diagram
2 (32)
VL
U4091BM
Pin Description
Pin
Symbol
Function
Pin
Symbol
Function
1
RECIN
Receive amplifier input
19
VRING
Input for ringer supply
2
TXACL
Time-constant adjustment for
transmit anti-clipping
20
IMPA
Input for adjusting the ringer input
impedance
3
MIC3
Microphone input for hands-free
operation
21
COSC
70-kHz oscillator for ringing power
converter
4
MIC2
Input of symmetrical microphone
amplifier with high common-mode
rejection ratio
22
23
INT
Interrupt line for serial bus
5
MIC1
Input of symmetrical microphone
amplifier with high common-mode
rejection ratio
24
SCL
Clock input for serial bus
25
SDA
Data line for serial bus
SWOUT Output for driving the external
switch resistor
6
RECO2
Output of the receive amplifier
26
OSCIN
Input for 3.58-MHz oscillator
7
RECO1
Output of the receive amplifier, also
used for sidetone network
27
OSCOUT
Clock output for the microcontroller
8
IND
The internal equivalent inductance
of the circuit is proportional to the
value of the capacitor at this pin. A
resistor connected to ground may be
used to adjust the DC mask.
28
RESET
Reset output for the microcontroller
29
ES
Input for external supply indication
30
ADIN
Input of A/D converter
31
BNMR
9
VL
Positive supply-voltage input to the
device in speech mode
Output of background-noise
monitor receive
32
BNMT
10
SENSE
Input for sensing the available line
current
Output of background-noise
monitor transmit
33
CT
11
GND
Ground, reference point for DCand AC signals
34
TLDR
12
VB
Unstabilized supply voltage for
speech network
Time constant of receive-level
detector
35
INLDR
Input of receive-level detector
13
SAO2
Negative output of speaker
amplifier (push-pull only)
36
INLDT
Input of transmit-level detector
14
SAO1
Positive output of speaker amplifier
(single ended and push-pull
operation)
37
TLDT
Time constant of transmit-level
detector
38
IMPSW
Unregulated supply voltage for the
microcontroller (via series regulator
to VMP)
39
MICO
Microphone preamplifier output
40
AMPB
Input for playback signal of
answering machine
41
15
VMPS
16
VMP
Regulated output voltage for
supplying the microcontroller
(typ. 3.3 V/ 6 mA in speech mode)
17
VMIC
Reference node for microphone
amplifier, supply for electret
microphones
18
TSACL
Time constant for speaker amplifier
anti-clipping
Time constant for mode switching
of voice switch
Switch for aditional line impedance
AMREC Output for recording signal of
answering machine
42
STO
Output for connecting the sidetone
network
43
STC
Input for sidetone network
44
STRC
Input for sidetone network
Remark: The protection device at Pin RECIN is disconnected.
Rev. A3, 27-Oct-00
3 (32)
U4091BM
DC Line Interface and
Supply-Voltage Generation
RECIN
1
44
STRC
TXACL
2
43
STC
MIC3
3
42
STO
MIC2
4
41
AMREC
MIC1
5
40
AMPB
RECO2
6
39
MICO
RECO1
7
38
IMPSW
IND
8
37
TLDT
VL
9
36
INLDT
SENSE
10
35
INLDR
The U4091BM contains two identical series regulators
which provide a supply voltage VMP of 3.3 V suitable for
a microprocessor. In speech mode, both regulators are
active because VMPS and VB are charged
simultaneously by the DC line interface. The output
current is 6 mA. The capacitor at VMPS is used to provide
the microcomputer with sufficient power during long line
interruptions. Thus, long flash pulses can be bridged or an
LCD display can be turned on for more than 2 seconds
after going on-hook. When the system is in ringing mode,
VB is charged by the on-chip ringing power converter. In
this mode, only one regulator is used to supply VMP with
maximum 3 mA.
GND
11
34
TLDR
Supply Structure of the Chip
VB
12
33
CT
A main benefit of the U4091BM is the easy implementation of various applications due to the flexible system
structure of the chip.
SAO2
13
32
BNMT
Possible applications:
SAO1
14
31 BNMR
VMPS
15
30 ADIN
VMP
16
29 ES
VMIC
17
28
TSACL
18
27 OSCOUT
VRING
19
26 OSCIN
IMPA
20
25 SDA
COSC
21
24
SCL
SWOUT
22
23
INT
L=2
RSENSE
CIND
(RDC
R30) / (RDC + R30)
D Group listening phone
D Hands-free phone
Figure 2. Pinning
4 (32)
The DC line interface consists of an electronic inductance
and a dual-port output stage which charges the capacitors
at VMPS and VB. The value of the equivalent inductance
is given by:
RESET
D Phones which feature ringing with the built-in speaker
amplifier
D Answering machine with external supply
The special supply topology for the various functional
blocks is illustrated in figure 3.
There are four major supply states:
1.
2.
3.
4.
Speech condition
Power down (pulse dialing)
Ringing
External supply
1. In speech condition, the system is supplied by the line
current. If the LIDET-block detects a line voltage
above approximately 2 V, the internal signal VLON is
activated. This is detected via the serial bus, all the
blocks which are needed have to be switched on via
the serial bus.
Rev. A3, 27-Oct-00
U4091BM
For line voltages below 2 V, the switches remain in
quiescent state as shown in the diagram.
2. When the chip is in power-down mode (Bit
LOMAKE), e.g., during pulse dialing, all internal
blocks are disabled via the serial bus. In this condition,
the voltage regulators and their internal bandgap are
the only active blocks.
3. During ringing, the supply for the system is fed into
VB via the Ringing Power Converter (RPC).
Normally, the speaker amplifier in single-ended mode
is used for ringing. The frequency for the melody is
generated by the DTMF/Melody generator.
4. In an answering machine, the chip is powered by an
external supply via Pin VB. The answering machine
connections can be directly put to U4091BM. The
answering machine is connected to the Pin AMREC.
For the output AMREC, an AGC function is selectable via the serial bus. The output of the answering
machine will be connected to the Pin AMPB, which is
directly connected to the switching matrix, and thus
enables the signal to be switched to every desired
output.
VL RSENSE
10 Ω
5.5 V
C
470µF
1 µF
IND
R
VMPS
–
+
–
+
R
300 kΩ
+
–
3.3 V
5.5 V
VMP
47 µF
VB
V
220µF
Figure 3. Supply generator
Ringing Frequency Detector (RFD)
The U4091BM provides an output signal for the
microcontroller. This output signal is always double the
value of the input signal (ringing frequency). It is
generated by a current comparator with hysteresis. The
levels for the on-threshold are programmable in 16 steps;
the off-level is fixed. Every change of the comparator
output generates a high level at the interrupt output INT.
The information can then be read out by means of a serial
bus with either normal or fast read mode. The block RFD
is always enabled.
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Clock Output Divider Adjustment
RINGTH[0:3]
VRING
0
7V
15
22 V
step
1V
The Pin OSCOUT is a clock output which is derived from
the crystal oscillator. It can be used to drive a microcontroller or another remote component and thereby
reduces the number of crystals required. The oscillator
frequency can be divided by 1, 8, 16, 32. During power-on
reset, the divider will be reset to 1 until it is changed by
setting the serial bus.
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Serial Bus Interface
CLK[0:1]
Divider
Frequency
0
1
3.58 MHz
1
8
447 kHz
2
16
224 kHz
3
32
112 kHz
The circuit is controlled by an external microcontroller
through the serial bus.
The serial bus is a bi-directional system consisting of a
one-directional clock line (SCL) which is always driven
by the microcontroller, and a bi-directional data-signal
line. It is driven by the microcontroller as well as from the
U4091BM (see figure 23).
Ringing Power Converter (RPC)
The serial bus requires external pull-up resistors as only
pull-down transistors (Pin SDA) are integrated.
The RPC transforms the input power at VRING (high
voltage/ low current) into an equivalent output power at
VB (low voltage/ high current) which is capable of
driving the low-ohmic loudspeaker. The input impedance
at VRING is adjustable from 3 kΩ to 12 kΩ by RIMPA
(ZRING = RIMPA / 100) and the efficiency of the stepdown converter is approximately 65%.
WRITE:
Rev. A3, 27-Oct-00
The data is a 12-bit word:
A0 – A3: address of the destination register (0 to 15)
D0 – D7: content of the register
The data line must be stable when the clock is high. Data
must be shifted serially. After 12 clock periods, the write
indication is sent. Then, the transfer to the destination register is (internally) generated by a strobe signal transition
of the data line when the clock is high.
5 (32)
U4091BM
READ:
There is a normal and a fast-read cycle.
In the normal read cycle, the microcontroller sends a 4-bit
address followed by the read indicator, then an 8-bit word
is read out. The U4091BM drives the data line.
The fast read cycle is indicated by a strobe signal. With
the following two clocks the U4091BM reads out the status bits RFDO and LIDET which indicate that a ringing
signal or a line signal is present (see figures 4, 5 and 6).
DTMFF[2:3]
in DTMF
Mode
Frequency
Error / %
0
00
1209
–0.110
1
01
1336
0.123
2
10
1477
–0.020
3
11
1633
–0.182
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DTMF Dialing
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Melody – Confidence Tone Generation ÁÁ
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The DTMF generator sends a multi-frequency signal
through the matrix to the line. The signal is the result of
the sum of two frequencies and is internally filtered. The
frequencies are chosen from a low and a high frequency
group.
The circuit conforms to the CEPT recommendation
concerning DTMF option.
Two different levels for the low level group and two
different pre-emphasis (2.5 dB and 3.5 dB) can be chosen
by means of the serial bus (rec. T/CF 46–03).
Melody/confidence tone frequencies are given in the
table below.
The frequencies are provided at the DTMF input of the
switch matrix. A sinus wave, a square wave or a pulsed
wave can be selected by the serial bus. Square signal
means the output is half of frequency cycle high and half
low. Pulsed signal means between the high and low
phases are high impedance phases of 1/6 of the period.
0
1
2
3
4
5
6
7
0
DTMFM[0:2]
000
001
010
011
100
101
110
111
DTMF generator OFF
Confidence tone melody
on (sinus)
Ringer melody (pulse)
Ringer melody
(square signal)
DTMF (high level)
DTMF (low level)
DTMFF[0:1]
in DTMF
Mode
Frequency
00
697
Error / %
–0.007
1
01
770
–0.156
2
10
852
0.032
3
11
941
0.316
6 (32)
0
DTMFF
[0:4]
f
Hz
ToneName
Error/%
DTMF
Key
00000
440.0
a1
–0.008
697
1209
1
1
00001
466.2
b1
–0.016
770
1209
4
2
00010
493.9
h1
–0.003
852
1209
7
3
00011
523.2
c2
0.014
941
1209
*
4
00100
554.4
des2
0.018
697
1336
2
–0.023
770
1336
5
–0.129
852
1336
8
5
00101
587.3
d2
6
00110
622.3
es2
7
00111
659.3
e2
0.106
941
1336
0
8
01000
698.5
f2
–0.216
697
1477
3
9
01001
740.0
ges2
–0.222
770
1477
6
10
01010
784.0
g2
0.126
852
1477
9
11
01011
830.0
as2
–0.169
941
1477
#
12
01100
880.0
a2
0.288
697
1633
A
13
01101
932.3
b2
–0.014
770
1633
B
14
01110
987.8
h2
–0.004
852
1633
C
15
01111
1046.5
c3
–0.335
941
1633
D
16
10000
1108.7
des3
–0.355
697
1209
1
–0.023
770
1209
4
–0.129
852
1209
7
17
10001
1174.7
d3
18
10010
1244.5
es3
19
10011
1318.5
e3
0.106
941
1209
*
20
10100
1396.9
f3
–0.214
697
1336
2
21
10101
1480.0
ges3
–0.222
770
1336
5
22
10110
1568.0
g3
0.126
852
1336
8
1661.2
as3
–0.241
941
1336
0
23
10111
24
11000
1760.0
a3
–0.302
697
1477
3
25
11001
1864.6
b3
–0.014
770
1477
6
26
11010
1975.5
h3
0.665
852
1477
9
27
11011
2093.0
c4
0.367
941
1477
#
0.387
697
1633
A
0.771
770
1633
B
28
11100
2217.5
des4
29
11101
2349.3
d4
30
11110
2663.3
–––
852
1633
C
31
11111
2983.0
–––
941
1633
D
Rev. A3, 27-Oct-00
U4091BM
DTMFF4 in DTMF mode
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Pre-Emphasis Selection
0
2.5 dB
1
3.5 dB
Write cycle
CLOCK
DATA
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0 R/W=0
Data fromµP
Strobe
fromµP
Figure 4. Write cycle
Normal read cycle
CLOCK
DATA
A3
A2
A1
A0
R/W=1
Data fromµP
D7
D6
Strobe
fromµP
D5
D4
D3
D2
D1
D0
Data from U4091BM
Figure 5. Normal read cycle
Fast read cycle
CLOCK
DATA
D7=IZC D6=IVE
Strobe
from µP
Data from U4091BM
Figure 6. Fast read cycle
Rev. A3, 27-Oct-00
7 (32)
U4091BM
Table 1. Names and functions of the serial bus registers
Register
R0
R1
R2
R3
R4
8 (32)
Group
Enables
Enables
Matrix
Matrix
Matrix
No
Name
Description
Status
R0B0
ENRING
Enable ringer
R0B1
ERX
Enable receive part
0
1
R0B2
ETX
Enable transmit part
0
R0B3
ENVM
Enable VM–generator
R0B4
ENMIC
Enable microphone
0
R0B5
ENSTBAL
Enable sidetone
0
R0B6
MUTE
Muting earpiece amplifier
0
R0B7
ENRLT
Enable POR low threshold
R1B0
ENSACL
Enable anti-clipping for speaker amplifier
0
R1B1
ENSA
Enable speaker amplifier and AFS
0
R1B2
ENSAO
Enable output stage speaker amplifier
0
R1B3
ENAM
Enable answering machine connections
0
R1B4
ENAGC
Enable AGC for answering machine
0
R1B5
free
0
R1B6
free
0
R1B7
FOFFC
Speed up offset canceller
0
R2B0
I1O1
Switch on MIC / LTX
0
R2B1
I1O2
Switch on MIC / SA
0
R2B2
I1O3
Switch on MIC / EPO
0
R2B3
I1O4
Switch on MIC / AMREC
0
R2B4
I1O5
Switch on MIC / AGCI
0
R2B5
I2O1
Switch on DTMF / LTX
0
R2B6
I2O2
Switch on DTMF / SA
0
R2B7
I2O3
Switch on DTMF / EPO
0
R3B0
I2O4
Switch on DTMF / AMREC
0
R3B1
I2O5
Switch on DTMF / AGCI
0
R3B2
I3O1
Switch on LRX / LTX
0
R3B3
I3O2
Switch on LRX / SA
0
R3B4
I3O3
Switch on LRX / EPO
0
R3B5
I3O4
Switch on LRX / AMREC
0
R3B6
I3O5
Switch on LRX / AGCI
0
R3B7
I4O1
Switch on AMPB / LTX
0
R4B0
I4O2
Switch on AMPB / SA
0
R4B1
I4O3
Switch on AMPB / EPO
0
R4B2
I4O4
Switch on AMPB / AMREC
0
R4B3
I4O5
Switch on AMPB / AGCI
0
R4B4
I5O1
Switch on AGCO / LTX
0
R4B5
I5O2
Switch on AGCO / SA
0
R4B6
I5O3
Switch on AGCO / EPO
0
R4B7
I5O4
Switch on AGCO / AMREC
0
1
1
Rev. A3, 27-Oct-00
U4091BM
Register
R5
R6
R7
R8
Group
Name
Description
Status
R5B0
EAFS
Enable AFS block
0
MICLIM
R5B1
AGATX0
Gain transmit AGA LSB
0
R5B2
AGATX1
Gain transmit AGA
0
R5B3
AGATX2
Gain transmit AGA MSB
0
R5B4
MICHF
Select RF-microphone input
0
R5B5
DBM5
Max. transmit level for anti-clipping
0
R5B6
MIC0
Gain microphone amplifier LSB
0
R5B7
MIC1
Gain microphone amplifier MSB
0
Shut down
R6B0
SD
Shut down
0
Sidetone
R6B1
free
R6B2
SL0
Slope adjustment for sidetone LSB
0
R6B3
SL1
Slope adjustment for sidetone MSB
0
R6B4
LF0
Low frequency adjustment for sidetone LSB
0
R6B5
LF1
Low frequency adjustment for sidetone
0
R6B6
LF2
Low frequency adjustment for sidetone
0
R6B7
LF3
Low frequency adjustment for sidetone MSB
0
Sidetone
R7B0
P0
Pole adjustment for sidetone LSB
0
AGARX
R7B1
P1
Pole adjustment for sidetone
0
R7B2
P2
Pole adjustment for sidetone
0
R7B3
P3
Pole adjustment for sidetone
0
R7B4
P4
Pole adjustment for sidetone MSB
0
R7B5
AGARX0
Gain receive AGC LSB
0
R7B6
AGARX1
Gain receive AGC
0
R7B7
AGARX2
Gain receive AGC MSB
0
R8B0
EA0
Gain earpiece amplifier LSB
0
EARA
Line imp.
R9
No
AGATX
AFS
Rev. A3, 27-Oct-00
0
R8B1
EA1
Gain earpiece amplifier
0
R8B2
EA2
Gain earpiece amplifier
0
R8B3
EA3
Gain earpiece amplifier
0
R8B4
EA4
Gain earpiece amplifier MSB
0
R8B5
IMPH
Line impedance selection (1 = 1 kΩ)
0
R8B6
LOMAKE
Short circuit during pulse dialing
0
R8B7
AIMP
Switch for additional external line impedance
0
R9B0
AFS0
AFS gain adjustment LSB
0
R9B1
AFS1
AFS gain adjustment
0
R9B2
AFS2
AFS gain adjustment
0
R9B3
AFS3
AFS gain adjustment
0
R9B4
AFS4
AFS gain adjustment
0
R9B5
AFS5
AFS gain adjustment MSB
0
R9B6
AFS4PS
Enable 4–point sensing
0
R9B7
free
0
9 (32)
U4091BM
Register
R10
R11
R12
R13
R14
10 (32)
Group
SA
ADC
DTMF
No
Name
Description
Status
R10B0
SA0
Gain speaker amplifier LSB
0
R10B1
SA1
Gain speaker amplifier
0
R10B2
SA2
Gain speaker amplifier
0
R10B3
SA3
Gain speaker amplifier
0
R10B4
SA4
Gain speaker amplifier MSB
0
R10B5
SE
Speaker amplifier single-ended mode
0
R10B6
LSCUR0
Speaker amplifier charge-current adjustment LSB
0
R10B7
LSCUR1
Speaker amplifier charge-current adjustment MSB
0
R11B0
ADC0
Input selection ADC
0
R11B1
ADC1
Input selection ADC
0
R11B2
ADC2
Input selection ADC
0
R11B3
ADC3
Input selection ADC
0
R11B4
NWT
Network tuning
0
R11B5
SOC
Start of ADC conversion
0
R11B6
ADCR
Selection of ADC range
0
R11B7
MSKIT
Mask for interrupt bits
0
R12B0
DTMFF0
DTMF frequency selection
0
R12B1
DTMFF1
DTMF frequency selection
0
R12B2
DTMFF2
DTMF frequency selection
0
R12B3
DTMFF3
DTMF frequency selection
0
R12B4
DTMFF4
DTMF frequency selection
0
R12B5
DTMFM0
Generator mode selection
0
R12B6
DTMFM1
Generator mode selection
0
R12B7
DTMFM2
Generator mode selection
0
CLK
R13B0
CLK0
Selection clock frequency for µC
0
RTH
R13B1
CLK1
Selection clock frequency for µC
0
TM
R13B2
RTH0
Ringer threshold adjustment LSB
0
R13B3
RTH1
Ringer threshold adjustment
0
R13B4
RTH2
Ringer threshold adjustment
0
R13B5
RTH3
Ringer threshold adjustment MSB
0
R13B6
TME0
Test mode enable (low active)
0
R13B7
TME1
Test mode enable (high active)
0
TM
R14B0
TME2
Test mode enable (high active)
0
CLOR
R14B1
TME3
Test mode enable (low active)
0
R14B2
free
R14B3
CLOR0
Adjustment for calculated receive log amp LSB
0
R14B4
CLOR1
Adjustment for calculated receive log amp
0
R14B5
CLOR2
Adjustment for calculated receive log amp
0
R14B6
CLOR3
Adjustment for calculated receive log amp
0
R14B7
CLOR4
Adjustment for calculated receive log amp MSB
0
0
Rev. A3, 27-Oct-00
U4091BM
Register
R15
Group
CLOT
No
Name
0
R15B1
free
0
R15B2
free
0
R15B3
CLOT0
Adjustment for calculated transmit log amp LSB
0
R15B4
CLOT1
Adjustment for calculated transmit log amp
0
R15B5
CLOT2
Adjustment for calculated transmit log amp
0
R15B6
CLOT3
Adjustment for calculated transmit log amp
0
R15B7
CLOT4
Adjustment for calculated transmit log amp MSB
0
To avoid undefined states of the system when it is
powered on, an internal reset clears the internal registers.
The system (U4091BM + microcontroller) is woken up
by any of the following conditions:
VMP > 2.75 V and VB > 2.95 V
line voltage (VL)
or
ringer (VRING)
or
external supply (ES)
Rev. A3, 27-Oct-00
Status
free
Power-on Reset
and
Description
R15B0
The power-down of the circuit is caused by a shut-down
sent by the serial bus (SD = 1), low-voltage reset or by the
watchdog function (see figures 8, 9 and 10).
Watchdog Function
To avoid the system operating the microcontroller in a
wrong condition, the circuit provides a watchdog
function. The watchdog has to be retriggered every
second by triggering the serial bus (sending information
to the IC or other remoted components at the serial bus).
If there has been no bus transmission for more than one
second, the watchdog initiates a reset.
The watchdog provides a reset for the external µC, but
does not change the U4091BM’s registers.
11 (32)
U4091BM
Acoustic Feedback Suppression
Acoustical feedback from the loudspeaker to the handsfree microphone may cause instability of the system. The
U4091BM has a very efficient feedback-suppression
circuit which offers a 4-point- or alternatively a 2-pointsignal-sensing topology (see figure 7).
under all operating conditions.
Two attenuators (TXA and SAI) reduce the critical loop
gain via the serial bus either in the transmit or in the
receive path. The overall loop gain remains constant
The voice-switch topology can be selected by the serial
bus. In 2-point-sensing mode, AFSCON is controlled
directly by the LOG outputs.
The LOGs produce a logarithmically-compressed signal
of the TX- and RX-envelope curve. The block AFSCON
determines whether the TX or the RX signal has to be
attenuated.
MICRO
AGATX
TXA
MICO
STO
CTU
CTLO
CBNMT
TLDT
BNMT
RTU
INLDT
LOG
CALCT
LOG
BNM
Mode
control
Line
BNM
AGARX
LOG
CALCR
LOG
INLDR
CT
BNMR
TLDR
RRU
CCT
CBNMR CRLO
CRU
RECO1
AFSCON
HV
DTD
SA
RECO2
SAI
Figure 7. Basic system configurations.
12 (32)
Rev. A3, 27-Oct-00
U4091BM
Line
LID
IVDD
OSCOUT
ton
VMP
Reset
trt
trt – ton = 4.5 ms
ton = start–up oscillator
Figure 8. Power-on reset (line)
VRING
VB
IVDD
VMP
OSCOUT
Reset
ton
trt
Figure 9. Power-on reset (ringing)
Line
LID
VMP
LVI
LVR
LVI
Reset
OSCOUT
Figure 10. Power-on reset (low voltage reset)
Rev. A3, 27-Oct-00
13 (32)
U4091BM
Dial-Tone Detector
D The output of the receive log (LOGR)
– designated I2
The dial-tone detector is a comparator with one side
connected to the speaker amplifier input and the other to
VM with a 35-mV offset (see figure 11). If the circuit is in
idle mode, and the incoming signal is greater than 35 mV
(25 mVrms), the comparator’s output will change
disabling the receive idle mode. This circuit prevents the
dial tone (which would be considered as continuous
noise) from fading away as the circuit would have the
tendency to switch to idle mode. By disabling the receive
idle mode, the dial tone remains at the normally expected
full level.
D The output of the transmit background-noise monitor
(BNMT) – designated I3
Background-Noise Monitors
This circuit distinguishes speech (which consists of
bursts) from background noise (a relatively constant
signal level). There are two background-noise monitors
* one for the receive path and the other for the transmit
path. The receive background-noise monitor is operated
on by the receive level detector, while the transmit
background noise monitor is operated on by the transmit
level detector (see figure 12). They monitor the
background noise by storing a DC voltage representative
of the respective noise levels in capacitors at CBNMR and
CBNMT. The voltages at these pins have slow rise times
(determined by the internal current source and an external C), but fast decay times. If the signal at TLDR (or
TLDT) changes slowly, the voltage at BNMR (or BNMT)
will remain more positive than the voltage at the noninverting input of the monitor’s output comparator. When
speech is present, the voltage at the non-inverting input
of the comparator will rise quicker than the voltage at the
inverting input (due to the burst characteristic of speech),
causing its output to change. This output is sensed by the
mode-control block.
4-Point Sensing
In 4-point sensing mode, the receive- and the transmitsensing path include additional CLOGs (Calculated
Logarithmical amplifier). The block MODECON
compares the detector output signals and decides whether
receive-, transmit- or idle mode has to be activated.
Depending on the mode decision, MODECON generates
a differential voltage to control AFSCON.
The MODECON block has seven inputs:
D The output of the transmit log (LOGT)
the comparison of LOGT, CLOGR
D The output of the receive clog (CLOGR)
– designated I1
D The output of the transmit clog (CLOGT)
the comparison of CLOGT, LOGR
14 (32)
D The output of the receive background-noise monitor
(BNMR) – designated I4
D The output of the dial-tone detector
The differential output (AFST, AFSR) of the block
MODECON controls AFSCON. The effect of I1-I4 is as
follows:
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Inputs
Output
I1
I2
I3
I4
Mode
T
T
S
X
Transmit
T
R
Y
Y
Change mode
R
T
Y
Y
Change mode
R
R
X
S
Receive
T
T
N
X
Idle
T
R
N
N
Idle
R
T
N
N
Idle
R
R
X
N
Idle
X = don’t care; Y = I3 and I4 are not both noise.
LOGT > CLOGR
LOGT < CLOGR
LOGR < CLOGT
LOGR > CLOGT
BNMT detects speech
BNMT detects noise
BNMR detects speech
BNMR detects noise
I1=T
I1=R
I2=T
I2=R
I3=S
I3=N
I4=S
I4=N
Term Definitions
1. ‘Transmit’ means the transmit attenuator is fully on,
and the receive attenuator is at maximum attenuation.
2. ‘Receive’ means the receive attenuator is fully on, and
the transmit attenuator is at maximum attenuation.
3. In ‘Idle’ mode, the transmit- and receive attenuator
are at the half of their maximum attenuation.
a) ‘Change mode’ means both transmit and receive
speech are present in approximately equal levels.
The attenuators are quickly switched (30 ms) to
the opposite mode until one speech level
dominates the other.
b) ‘Idle’ means speech has ceased in both transmit
and receive paths. The attenuators are then
slowly switched (1.5 seconds) to idle mode.
4. Switching to the full transmit or receive modes from
idle mode is at the fast rate (30 ms).
Rev. A3, 27-Oct-00
U4091BM
Summary of the Truth Table
1. The circuit will switch to transmit mode if
a) Both transmit level detectors sense higher signal
levels than the respective receive level detectors
and
b) The transmit background-noise monitor indicates the presence of speech.
2. The circuit will switch to receive mode if
a) Both receive level detectors sense higher signal
levels than the respective transmit level
detectors, and
D To switch to receive mode, IRX is turned on (ITX is
off), increasing the voltage on the capacitor to
+240 mV with respect to VM.
D To switch to reverse mode, the current sources ITX,
IRX are turned off, and the current source IFI is
switched on, discharging the capacitor to VM.
D To switch to idle mode, the current sources ITX, IRX,
IFI are turned off, and the current source ISI is charging the capacitor to VM.
b) The receive background-noise monitor indicates
the presence of speech.
IN
+
–
3. The circuit will switch to the reverse mode if the level
detectors disagree on the relative strengths of the
signal levels, and at least one of the backgroundnoise monitors indicates speech.
OUT
35 mV
VM
to mode
control
I4
DTD
Figure 11. Dial tone detector
4. The circuit will switch to idle mode when
a) Both talkers are quiet (no speech present), or
b) When one talker’s speech level is continuously
overridden by noise at the other speaker’s
location.
The time required to switch the circuit between transmit,
receive and idle is determined by internal current sources
and the capacitor at Pin CT. A diagram of the CT circuitry
is shown in figure 13. It operates as follows:
V
B
BNMR
(BNMT)
TLDR
(TLDT)
D To switch to transmit mode, ITX is turned on (IRX is
off), charging the external capacitor to –240 mV
below VM. (An internal clamp prevents further
charging of the capacitor.)
C
CT
36 mV
I4
(I3)
VM
Figure 12. Background noise monitor
AFS
control
CT
–
+
56 k Ω
33 k Ω
D CCT is typically 4.7 µF.
1 µF
–
+
+
–
to
attenuators
I
RX
10µA I
TX
10µA IFI
Control
circuit
4
I
1–4
I
SI
Dial tone det.
V
M
V
M
Figure 13. Generation of control voltage (CT) for mode switching
Rev. A3, 27-Oct-00
15 (32)
U4091BM
TXA
MICRO
LOG
Line
AFS
control
LOG
SA
SAI
Figure 14. Block diagram hands-free mode U4091BM 2-point signal sensing
TXA
MICRO
CLOGT
LOGT
BNMT
Line
Mode
control
BNMR
CLOGR
LOGR
CT
CCT
AFS
control
DTD
SA
SAI
Figure 15. Block diagram hands-free mode U4091BM 4-point signal sensing
16 (32)
Rev. A3, 27-Oct-00
U4091BM
Analog-to-Digital Converter ADC
This circuit is a 7-bit successive approximation analogto-digital converter in switched capacitor technique. An
internal bandgap circuit generates a 1.25-V reference
voltage which is the equivalent of 1 MSB.
1LSB = 19.5 mV. The possible input voltage at ADIN is
0 to 2.48 V.
The ADC needs an SOC (Start Of Conversion) signal. In
the ‘High’ phase of the SOC signal, the ADC is reset.
50 µs after the beginning of the ‘Low’ phase of the SOC
signal, the ADC generates an EOC (End Of Conversion)
signal which indicates that the conversion is finished. The
rising edge of EOC generates an interrupt at the INT
output. The result can be read out by the serial bus.
SOC
50 µs
EOC
Figure 16. Timing of ADC
SOC
IL 20mV/(1mA S)
Voltages higher than 2.45 V have to be divided. The
signal which is connected to the ADC is determined by
5 bits: ADC0, ADC1, ADC2, ADC3 and NWT.
TLDR/TLDT measuring is possible relative to a preceding reference measurement. The current range of IL can
be doubled by ADCR. If ADCR is ‘High’, S has the value
0.5, otherwise S = 1.
The source impedance at ADIN must be lower than
250 kΩ.
Accuracy: 1 LSB + 3%
ADIN
0.4 VB
MSB
0.4 VMPS
BIT5
0.75 VMP
BIT4
ADC
8 (TLDR–REF)
BIT3
8 (TLDT–REF)
BIT2
0.4 SAO1
BIT1
0.4 OFF1
LSB
0.4 OFF2
0.4 OFF3
EOC
Figure 17. ADC input selection
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
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Table 2 Input selection AD converter
ADC[1:4]
Value
0
00000
OFF
1
00001
IL
I1 = S
2
00010
ADIN extern
V2 = 2.5 V
3
00011
VB
V3 = (2.5 V / 0.4)
D / 127
4
00100
VMPS
V4 = (2.5 V / 0.4)
D / 127
5
00101
VMP
V5 = (2.5 V / 0.75)
6
00110
TLDR
V6 = 8
(Vp – Ref)
D / 127
7
00111
TLDT
V7 = 8
(Vp – Ref)
D / 127
8
01000
free
9
01001
SAO1
10
01010
Offcan1
11
01011
Offcan2
12
01100
Offcan3
13
01101
free
14
01110
free
15
01111
free
16–31
1XXXX
127 mA
D / 127
D / 127 (max. 2.5 V)
V4 = (2.5 V / 0.4)
D / 127
D / 127
Atmel Wireless & Microcontrollers
internal use
NWT (TLDR)
D = measured digital word (0 < = D < = 127)
S = programmable gain 0.5 or 1
Vp = peak value of the measured signal
Rev. A3, 27-Oct-00
17 (32)
U4091BM
Switch Matrix
The switch matrix has 5 inputs and 5 outputs. Every pair
of input and output except AGCO and AGCIN can be
connected. The inputs and outputs used must be enabled.
If 2 or more inputs are switched to an output, the sum of
the inputs is available at the output.
The inputs MIC and LRX have offset cancellers with a
3-dB corner frequency of 270 Hz. AMPB has a 60-kΩ
input impedance. The TXO output has a digitallyprogrammable gain stage with a gain of 2, 3 to 9 dB
depending on AGATX0 (LSB), AGATX1, AGATX2
(MSB) and a first order low-pass filter with 0.5 dB
damping at 3300 Hz and 3 dB damping at 9450 Hz. The
outputs RXLS, EPO and AMREC have a gain of 0 dB.
The offset at the outputs of the matrix is less than 30 mV.
If a switch is open, the path has a damping of more than
60 dB.
AGCO
AMPB LRX DTMF MIC
Offset
canceller
I5
I4
I3
I2
Offset
canceller
Lowpass
O4
O3
O2
O1
2.9 dB
AGCI
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R2
R3
R4
I1
AGC
O5
Table 3 Table of bits and corresponding switches
Register
No.
Name
Description
LTX
AMREC EPO RXLS
AGATX0
AGATX1
AGATX2
R2B0
I1O1
Switch on MIC / LTX
R2B1
I1O2
Switch on MIC / RXLS
R2B2
I1O3
Switch on MIC / EPO
R2B3
I1O4
Switch on MIC / AMREC
R2B4
I1O5
Switch on MIC / AGCI
R2B5
I2O1
Switch on DTMF / LTX
R2B6
I2O2
Switch on DTMF / RXLS
R2B7
I2O3
Switch on DTMF / EPO
R3B0
I2O4
Switch on DTMF / AMREC
R3B1
I2O5
Switch on DTMF / AGCI
R3B2
I3O1
Switch on LRX / LTX
R3B3
I3O2
Switch on LRX / RXLS
R3B4
I3O3
Switch on LRX / EPO
R3B5
I3O4
Switch on LRX / AMREC
R3B6
I3O5
Switch on LRX / AGCI
R3B7
I4O1
Switch on AMPB / LTX
R4B0
I4O2
Switch on AMPB / RXLS
R4B1
I4O3
Switch on AMPB / EPO
R4B2
I4O4
Switch on AMPB/ AMREC
R4B3
I4O5
Switch on AMPB / AGCI
R4B4
I5O1
Switch on AGCO / LTX
R4B5
I5O2
Switch on AGCO / RXLS
R4B6
I5O3
Switch on AGCO / EPO
R4B7
I5O4
Switch on AGCO / AMREC
TXO
–10 dB
STO
Figure 18. Diagram for switch matrix
18 (32)
Rev. A3, 27-Oct-00
U4091BM
Sidetone System
LINE
LTX
8dB
CK
LRX
0–7dB
+ DIFF1
–
AGARX
STO_DIFF
9dB
MOD
–10dB
STO
AMP1
–10dB
STOAMP
AMP2
STO
8.2 kΩ
Sidetone balancing
g
ZL
RECIN
LF
STRC
P
CTO
33 nF
SL
STC
f
LF
P
SL
Figure 19. Principle circuit of the sidetone balancing
The SideTone Balancing (STB) has the task of reducing
the crosstalk from LTX (microphone) to LRX (earpiece)
in the frequency range of 0.3 to 3.4 kHz. The LTX signal
is converted into a current in the MOD block. This current
is transformed into a voltage signal (LINE) by the line
impedance ZL. The LINE signal is fed into the summing
amplifier DIFF1 via capacitor CK and attenuator AMP1.
On the other hand the LTX buffered by STOAMP drives
an external lowpass filter (RST, CST). The external lowpass filter and the internal STB have the transfer function
drawn in the STB box. The amplified STB-output signal
drives the negative input of the summing block. If both
signals at the DIFF1 block are equal in level and phase,
we have good suppression of the LTX signal. In this
condition, the frequency and phase response of the STB
block will represent the frequency curve on line.
In real life the line impedance ZL varies strongly for
different users. To obtain good suppression with one
application for all different line impendances, the STB
function is programmable.
Rev. A3, 27-Oct-00
The 3 programmable parameters are:
1. LF (gain at low frequency)
LF has 15 programming steps of 0.5 dB. LF(0) gives
–2 dB gain, LF(15) gives 5.5 dB gain.
STO_DIFF(LF) = (–10 dB – 2 dB + 0.5 dB
LF + 9 dB)
LTX
2. P (the pole position of the lowpass)
The P adjustment has 31 steps. P(0) means the
lowpass determined by the external application
(RST, CST). The internally processed lowpass
frequency is fixed by this equation
1
f(P) +
1.122 P
2 Pi CST RST
3. SL
(sidetone slope; the pole frequency of the highpass)
The SL has 3 steps. SL(0) is a lower frequency of the
highpass. SL(3) is a higher frequency of the highpass.
With SL, can be influenced the suppression at high
frequencies.
19 (32)
U4091BM
–10dB
Offset
cancel
–3dB ... –10dB and 7dB (NWT)
ST
Line
7dB→0dB and
20dB (NWT)
Sidetone
balancing
VL
32dB→ –23dB
Offset
cancel
LRX
SAO1
RXLS
Loud–
speaker
6dB
1.5dB steps
1dB steps
SAO2
26dB→ –3dB and
–10dB (DTMF)
DTMF
generator
Filter
MIC1
Handset
micro–
phone
Answering
machine
< –24dBm/
–22dBm >
→
0dB
30dB→12dB
Offset
cancel
RECO1
EPO
DTMF
Switching
matrix
7dB→ –48dB
MIC2
Intercom
micro–
phone
DTMF
1dB steps
RECO2
VL
8dB
1dB steps
MIC3
6dB steps
0dB
DTMF
< –34dBm/
–32dBm >
9dB→2dB
LTX
MIC
Earpiece
Line
MOD
1dB steps
0dB
AMPB
AMREC
0dB
0dB
AGCO
AGCI
0dB
AMREC Answering
machine
AMPB
AGC
Figure 20. Audio frequency signal management U4091BM
Absolute Maximum Ratings
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Parameter
Symbol
Value
Unit
Line current
IL
140
mA
DC line voltage
VL
12
V
IRING
15
mA
Junction temperature
Tj
125
°C
Ambient temperature
Tamb
–25 to +75
°C
Tstg
–55 to +150
°C
Ptot
0.9
W
Maximum input current
Storage temperature
Total power dissipation,
Tamb = 60°C
Thermal Resistance
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Parameter
Junction ambient
20 (32)
SSO44
Symbol
Value
Unit
RthJA
70
K/W
Rev. A3, 27-Oct-00
U4091BM
Electrical Characteristics
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100 Ω,
RLS = 50 Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Parameter
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Fig.
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DC characteristics
DC voltage drop-over cir- IL = 2 mA
cuit
IL = 14 mA
IL = 60 mA
IL = 100 mA
VL
4.4
8.6
1.6
4.8
7.2
9.2
9.8
V
V
V
V
47.7
dB
0
dB
5.2
Transmission amplifier, IL = 14 mA, VMIC = 2 mV, MICG[0:1] = 2, AGATX[0:2] = 7
ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, (GT = 48 dB)
Transmit amplification
MICG[0:1] = 2
AGATX[0:2] = 7
GT
45.3
Frequency response
due to internal filters)
IL ≥ 14 mA,
f = 1 kHz to 3.4 kHz
∆GT
–1
Gain change with
current
IL = 14 to 100 mA
∆GT
±0.5
dB
Gain deviation
Tamb = –10 to +60°C
∆GT
±0.5
dB
CMRR of microphone
amplifier
CMRR
Input resistance of MIC
amplifier
Ri
60
80
dB
50
kΩ
Input resistance of MIC3
amplifier
MICHF = 1
Ri
Gain difference
between MIC1, MIC2 to
MIC3
MICHF = 1
Distortion at line
IL ≥ 14 mA
VL = 700 mVrms
Maximum output voltage
IL ≥ 19 mA, d < 5%
VMIC = 10 mV
CTXA = 1 µF
DBM5 = 0
VLmax
1.8
Maximum output voltage
DBM5 = 1
VLmax
4.8
Maximum output voltage
VMIC = 20 m
MICG[0:1] = 3
Noise at line psophometrically weighted
IL ≥ 14 mA, MICG[0:1] =
2
AGATX[0:2] = 7
no
– 73
Anti-clipping:
attack time
release time
CTXA = 1 µF
each 3 dB overdrive
ta
tr
2
80
Rev. A3, 27-Oct-00
300
kΩ
∆GT
±0.4
dB
dt
2
%
3.0
4.2
dBm
6.0
6.6
dBm
VMICOm
75
46.5
150
–4.2
dBm
ax
– 70
dBmp
ms
ms
21 (32)
U4091BM
Electrical Characteristics (continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100 Ω,
RLS = 50 Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
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Parameter
Test Conditions / Pins
Symbol
Min.
45
Gain at low operating
current
IL = 8 mA, IMP = 1 mA
VMIC = 0.5 mV
IVMIC = 300 µA
GT
Distortion at low
operating current
IL = 8 mA, IMP = 1 mA
VMIC = 5 mV
IVMIC = 300 µA
dt
Typ.
Max.
Unit
48
dB
5
%
+17
dB
1
17
dB
dB
0
dB
Fig.
Receiving amplifier
IL = 14 mA, VGEN = 300 mV, ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1,
SL[0:1] = 0, LF[0:3] = 1, P[0:4] = 31, AFS[0:5] = 54, AGARX[0:2] = 0
Adjustment range of
receiving gain
Single ended,
IL ≥ 14 mA, Mute = 1,
EA[0:4] = 2 – 31
AGARX[0:2] = 0 – 7
Receiving amplification
Differential
AGARX[0:2] = 0
EA[0:4] = 15
EA[0:4] = 31
GR
–19
GR
–1
15
0
16
IL ≥ 14 mA,
f = 1 kHz to 3.4 kHz
∆GRF
Gain change with
current
IL = 14 to 100 mA
∆GR
±0.5
dB
Gain deviation
Tamb = –10 to +60°C
∆GR
±0.5
dB
EP
3
Vrms
Frequency response
Ear protection differential IL ≥ 14 mA,
VGEN = 11 Vrms
EA[0:4] = 21
MUTE suppression
IL = 14 mA, I101 = 0
(earpiece disconnect from
matrix)
Output voltage
d < 2% differential
IL = 14 mA
Zear = 68 nF + 100 Ω
EA[0:4] = 11
Maximum output
current d < 2%
Zear = 100 Ω
EA[0:4] = 31
Receiving noise
psophometrically
weighted
IL = 14 mA
Zear = 68 nF + 100 Ω
EA[0:4] = 15
Sidetone suppression
Z = 600 Ω
Output resistance
Each output against GND
22 (32)
∆GR
Iout
–1
60
dB
0.775
Vrms
4
mAp
– 79
– 76
20
Ro
dBmp
dB
10
Ω
Rev. A3, 27-Oct-00
U4091BM
Electrical Characteristics (continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100 Ω,
RLS = 50 Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
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Parameter
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Gain at low operating
current (receive only)
IL = 6.5 mA, IMP = 1 mA
IM = 300 µA
VGEN = 200 mV
EA[0:4] = 21,
ENMIC = ETX = I101 =
0
GR
–2
0
2
dB
Distortion at low
operating current
IL = 6.5 mA, IMP = 1 mA
IM = 300 , EA[0:4] = 15,
ENMIC = ETX = I101 =
0
dR
5
%
Adjustment step:
earpiece amplifier
∆EA[0:4] = 1
for EA[0:4] = 2 ... 3
0.8
1
1.2
dB
Adjustment step:
AGARX
∆AGARX[0:2] = 1
0.8
1
1.2
dB
Gain for DTMF signal
AMPB → RECO1/2
EA[0:4] = 1
AC impedance
IMPH = 0
IMPH = 1
–10
Zimpl
Zimph
595
980
625
1030
Fig.
dB
655
1080
Ω
Ω
Receiving amplifier
IL = 14 mA, VGEN = 300 mV, ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1,
SL[0:1] = 0, LF[0:3] = 1, P[0:4] = 31, AFS[0:5] = 54, AGARX[0:2] = 0
Adjustment range of
receiving gain
Single ended,
IL ≥ 14 mA, Mute = 1,
EA[0:4] = 2 – 31
AGARX[0:2] = 0 – 7
Receiving amplification
Differential
AGARX[0:2] = 0
EA[0:4] = 15
EA[0:4] = 31
GR
–19
GR
–1
15
0
16
+17
dB
1
17
dB
dB
0
dB
IL ≥ 14 mA,
f = 1 kHz to 3.4 kHz
∆GRF
Gain change with
current
IL = 14 to 100 mA
∆GR
±0.5
dB
Gain deviation
Tamb = –10 to +60°C
∆GR
±0.5
dB
EP
3
Vrms
Frequency response
Ear protection differential IL ≥ 14 mA,
VGEN = 11 Vrms
EA[0:4] = 21
MUTE suppression
IL = 14 mA, I101 = 0
(earpiece disconnect from
matrix)
Output voltage
d < 2% differential
Rev. A3, 27-Oct-00
IL = 14 mA
Zear = 68 nF + 100 Ω
EA[0:4] = 11
∆GR
–1
60
dB
0.775
Vrms
23 (32)
U4091BM
Electrical Characteristics (continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100 Ω,
RLS = 50 Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
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Parameter
Test Conditions / Pins
Symbol
Min.
Iout
4
Maximum output
current d < 2%
Zear = 100 Ω
EA[0:4] = 31
Receiving noise
psophometrically
weighted
IL = 14 mA
Zear = 68 nF + 100 Ω
EA[0:4] = 15
Sidetone suppression
Z = 600 Ω
Output resistance
Each output against GND
Ro
Gain at low operating
current (receive only)
IL = 6.5 mA, IMP = 1 mA
IM = 300 µA
VGEN = 200 mV
EA[0:4] = 21,
ENMIC = ETX = I101 =
0
GR
Distortion at low
operating current
IL = 6.5 mA, IMP = 1 mA
IM = 300 , EA[0:4] = 15,
ENMIC = ETX = I101 =
0
dR
Adjustment step:
earpiece amplifier
∆EA[0:4] = 1
for EA[0:4] = 2 ... 3
0.8
Adjustment step:
AGARX
∆AGARX[0:2] = 1
0.8
Gain for DTMF signal
AMPB → RECO1/2
EA[0:4] = 1
AC impedance
IMPH = 0
IMPH = 1
Typ.
Max.
Unit
mAp
– 79
– 76
dBmp
20
–2
dB
10
Ω
2
dB
5
%
1
1.2
dB
1
1.2
dB
0
–10
Zimpl
Zimph
595
980
Fig.
625
1030
dB
Ω
Ω
655
1080
DTMF, IL = 14 mA, ETX = I201 = 1, AGATX[0:2] = 7, DTMFM[0:2] = 4, DTMFF[0:4] = 0
Max. level at line
Sum level, 600 Ω
DTMFM[0:2] = 4
–5.1
–3.6
–2.1
dBm
DTMF level at line (low
gain)
Sum level, 600 Ω
DTMFM[0:2] = 5
–7.6
–6.1
–4.6
dBm
Pre-emphasis
600 Ω DTMFF4 = 0
DTMFF4 = 1
2
3
2.5
3.5
3
4
dBm
dBm
11
mA
38
dB
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Speaker amplifier, differential mode
AMPB → SAO1/2, ENSACL = ENSA = ENSAO = ENAM = I4O2 = 1, SA[0:4] = 31,
ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1
Minimum line current for
operation
ENAM = I4O2 = 0
SE = 0, I3O2 = 1
IMP 1 mA, VGEN = 300
mV
Gain from AMPB to SAO VAMPB = 3 mV, IL =
15 mA, SA[0:4] = 31
SA[0:4] = 0
24 (32)
ILmin
GSA
36
37
–5.5
Rev. A3, 27-Oct-00
U4091BM
Electrical Characteristics (continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100 Ω,
RLS = 50 Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
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Parameter
Test Conditions / Pins
Adjustment step speaker
amplifier
SA[0:4] = –1
Output power single
ended
Load resistance:
RLS = 50 Ω, d < 5%
VAMPB = 40 mV, SE = 1
IL = 15 mA
IL = 20 mA
Max. output power
differential
Load resistance:
RL = 50 Ω, d < 5%
VAMPB = 60 mV, SE = 0
VB = 5 V
Output noise
(input AMPB open)
psophometrically
weighted
IL > 15 mA
Gain deviation
IL = 15 mA
Tamb = –10 to +60°C
Symbol
PSA
PSA
Min.
Typ.
Max.
Unit
1.15
1.35
1.55
dB
3
7
20
mW
mW
150
mW
PSA
nSA
240
mVpsoph
∆GSA
±1
dB
Mute suppression
IL = 15 mA, VL = 0 dBm,
VAMPB = 4 mV
I4O2 = 0
VSAO
–56
dBm
Gain change with
current
IL = 15 to 100 mA
∆GSA
1
dB
Gain change with
frequency
IL = 15 mA
f = 1 kHz to 3.4 kHz
∆GSA
Attack time of
anti-clipping
20 dB over drive
Release time of
anti-clipping
Fig.
dB
–1
0
tr
2
ms
tf
170
ms
Adjustment step of
charge current
ENSAO = 0, SE = 1
∆LSCUR[0:1] = 1
–480
–400
–320
µA
Adjustment step of
discharge current
ENSAO = 0, SE = 0
∆LSCUR[0:1] = 1
320
400
480
µA
Charge current
Pin SAO2
ENSAO = 0, SE = 1
LSCUR[0:1] = 3
ICHA
–1.45
–1.2
–0.95
mA
Discharge current
Pin SAO2
ENSAO = 0, SE = 0
LSCUR[0:1] = 3
IDIS
0.95
1.2
1.45
mA
Microphone amplifier,
VB = 5 V, VMIC = 2 mV, VMIC3 = 2 mV, ENMIC = ENAM = I1O4 = 1, MICHF = 0
Gain MIC amp.:
MIC1/2 → AMREC
MICG[0:1] = 0
17.4
17.9
18.4
dB
Gain MIC amp.:
MICG[0:1] = 1
23.2
23.7
24.2
dB
Gain MIC amp.:
MICG[0:1] = 2
329.1
29.6
30.1
dB
Rev. A3, 27-Oct-00
25 (32)
U4091BM
Electrical Characteristics (continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100 Ω,
RLS = 50 Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
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Parameter
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Gain MIC amp.:
MICG[0:1] = 3
35
35.5
36.0
dB
MIC3 → AMREC
MICHF = 1, MICG[0:1]
=3
35
35.5
36.0
dB
MICG[0:1] = 0, MICHF
=0
60
dB
MIC1/2 → MIC3
MICHF = 1
60
dB
Settling time
offset-cancellers
5 τ, FOFFC = 0
9
12
ms
Settling time offset-cancellers in speed-up mode
5 τ, FOFFC = 1
1.8
2.4
ms
Input suppression:
MIC3 → MIC1/2
Fig.
AGC for answering machine, AMPB → AMREC,
ENAM = ENAGC = I4O5 = I5O4 = 1
Nominal gain
VAMPB = 5 mV
24
26
28
dB
Max. output level
VAMPB = 50 mV, d< 5%
240
300
360
mVp
Attack time
20 dB overdrive
Release time
1
ms
45
ms
Switching matrix,
VL = 0, VB = 5 V, ENAM = I4O4 = 1, VAMPB = 0.6 Vrms
Input impedance AMPB
Gain AMPB →
AMREC
Max. input level AMPB
I4O5 = I5O4 = 1, I4O4 =
0
Max. output level
AMREC
I4O4 = 1
Offset
I4O4: 1 → 0
50
60
70
kΩ
–0.7
–0.3
0.1
dB
600
mV
VB–
600 mV
VPP
±30
mV
∆VAMR
EC
Mute switching matrix
I4O4 = 0
60
dB
Power-on reset
VL = 0, VMP = 3.3 V, VB = 5 V, U4091 in power-down mode
Power-on reset by ES VB
high,
VMP threshold
VB = 4 V, ES = 4 V,
rise VMP until RESET go
to low
Power-on reset by ES
VMP high,
VB threshold
VMP = 3 V, ES = 4 V,
rise VB until RESET go
to low
VMPon
VBon
2.65
2.75
3.2
2.85
V
V
Low-voltage interrupt
VL = 0, VMP = 3.3 V, VB = 0 V
26 (32)
Rev. A3, 27-Oct-00
U4091BM
Electrical Characteristics (continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100 Ω,
RLS = 50 Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
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Parameter
VMP decreasing
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Decrease VMP until INT
returns to high
VLVI
2.5
2.6
2.7
V
VLVR
2.35
2.45
2.55
V
100
150
0.6
0.9
Fig.
Power-off reset
VL = 0, VMP = 3.3 V, VB = 0 V
Low-voltage reset
Decrease VMP until RESET returns to low
Difference voltage
between low-voltage
interrupt and reset
VLVI – VLVR
mV
Logical part
VMP = 3.3 V, VB = 5 V
Output impedance at
OSCOUT
Pins SCL,
SDA (input mode)
Low level
High level
Input leakage current
0 < Vi < VMP
–1
Pins INT,
SDA (output mode)
Output low
(resistance to GND)
150
1.2
kΩ
0.2 VMP
V
V
1
A
350
Ω
5
µA
80
Ω
5
mA
0.8 VMP
230
Switch for additional impedance (Pin IMPSW)
VMP = 3.3 V, VB = 3 V
Switch-off leakage
current
0 < Vi < VMP
IMPSW = 0
Resistance to GND
IMPSW = 1
Max. current
IMPSW = 1
–0.5
50
–5
AFS (Acoustic Feedback Suppression), IL = 14 mA, VGEN = 300 mV,
ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, SL[0:1] = 0, LF[0:3] = 1, P[0:4] = 31, AGARX[0:2] = 0
Adjustment range of attenuation
IL ≥ 15 mA
Attenuation of transmit
gain
IL ≥ 15 mA, IINLDT = 0
µA
IINLDR = 10 µA
∆GT
47
Attenuation of speaker
amplifier
IL ≥ 15 mA, IINLDT = 10
µA
IINLDR = 0 µA
GSA
0
50
dB
50
53
dB
47
50
53
dB
3.1
3.3
3.5
V
5.5
V
Supply voltages, VMIC = 25 mV, Tamb = – 10 to + 60°C
VMP
IL = 14 mA, RDC = 680
kΩ
IMP = 3 mA
VMP
VMPS
IL = 100 mA, RDC = inf.,
IMP = 0 mA
VMPS
Rev. A3, 27-Oct-00
27 (32)
U4091BM
Electrical Characteristics (continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100 Ω,
RLS = 50 Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
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ÁÁÁ
Parameter
Test Conditions / Pins
Symbol
Min.
VMIC
IL 14 mA, RDC = 1.3 MΩ
IM = 700 A
VMIC
1.5
VB
IB = +20 mA, IL = 0 mA
Ringing power converter, IMP = 1 mA, IM = 0
VB
5.5
Max.
Unit
4
V
6.3
V
VRING = 20.6 V
ENSA = ENSAO = SE =
1
Threshold
VRING: high to low
PSA
15
Threshold
low to high,
RINGTH [0:3] = 0
6.0
low to high
RINGTH [0:3] = 15
Adjustment steps threshold
Input impedance
mW
7.4
V
6.7
7.4
V
19
21
23
V
∆RINGTH = 1
0.8
1
1.2
V
VRING = 30 V
4.6
5.8
7.0
kΩ
Max. input voltage
Fig.
RIMPA = 500 kW
Maximum output power
Threshold
Typ.
VRINGm
30
V
ax
Serial bus SCL, SDA, AS, VMP = 3.3 V, RSDA = RSCL = RINT = 12 kW
Input voltage
HIGH
LOW
SDA, SCL,
ViBUS
VDD
1.5
V
V
VO
0.4
V
fSCL
100
kHz
Rise time SDA, SCL
tr
1
µs
Fall time SDA, SCL
tf
300
ns
Output voltage
Acknowledge LOW
INT
SDA
ISDA = 3 mA
Clock frequency
Period of SCL
HIGH
LOW
3.0
0
SCL
HIGH
LOW
tH
tL
4.0
4.7
µs
µs
tsSTA
tsDAT
tsSTOP
twSTA
4.7
250
4.7
4.7
µs
ns
µs
µs
thSTA
thDAT
4.0
0
µs
µs
Setup time
Start condition
Data
Stop condition
Time space 1)
Hold time
Start condition
DATA
1)
This is a space of time where the bus must bee from data transmission and before a new transmission can be started
28 (32)
Rev. A3, 27-Oct-00
Test Circuits
Rev. A3, 27-Oct-00
PWL
sin
V
+
V
PWL
V
A
+
V
+
3.58
MHz
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
U4091BM
Figure 21. Basic test circuit
44
10 Ω
V
C IND
+
R CD
+
V
50 Ω
sin
sin
V
V
29 (32)
U4091BM
V
U4091BM
30 (32)
3.58 MHz
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
PWL
+
+
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
U4091BM
Figure 22. Test circuit for ringing
44
PWL
BC
556
2.2 mH
68 nF
SD103A
V
50 Ω
V
VB
VB
14600
Rev. A3, 27-Oct-00
U4091BM
Bus Timing
SDA
twSTA
tr
tf
thSTA
SCL
P
S thSTA
thDAT
tL
tH
tsSTA
tsSTOP
thDAT
P
P = Stop, S = Start
Figure 23. Bus timing diagram
Package Information
Package SSO44
Dimensions in mm
9.15
8.65
18.05
17.80
7.50
7.30
2.35
0.3
0.25
0.10
0.8
0.25
10.50
10.20
16.8
44
23
technical drawings
according to DIN
specifications
13040
1
Rev. A3, 27-Oct-00
22
31 (32)
U4091BM
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid
their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these
substances.
Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed
in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances
and do not contain such substances.
4.5.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended
or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims,
costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death
associated with such unintended or unauthorized use.
Data sheets can also be retrieved from the Internet:
http://www.atmel–wm.com
Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
32 (32)
Rev. A3, 27-Oct-00