UCC1889 UCC2889 UCC3889 Off-line Power Supply Controller FEATURES • • • • • • • • DESCRIPTION Transformerless Off-line Applications The UCC1889 controller is optimized for use as an off-line, low power, low voltage, regulated bias supply. The unique circuit topology utilized in this device can be visualized as two cascaded flyback converters, each operating in the discontinuIdeal Primary-side Bias Supply ous mode, and both driven from a single external power switch. The significant Efficient BiCMOS Design benefit of this approach is the ability to achieve voltage conversion ratios of 400V to 12V with no transformer and low internal losses. Wide Input Range The control algorithm utilized by the UCC1889 is to force the switch on time to be Fixed or Adjustable inversely proportional to the input line voltage while the switch off time is made inLow Voltage Output versely proportional to the output voltage. This action is automatically controlled by Uses Low Cost SMD Inductors an internal feedback loop and reference. The cascaded configuration allows a voltage conversion from 400V to 12V to be achieved with a switch duty cycle greater Short Circuit Protected than 10%. This topology also offers inherent short circuit protection since as the output voltage falls to zero, the switch off time approaches infinity. Optional Isolation Capability The output voltage can be easily set to 12V or 18V. Moreover, it can be programmed for other output voltages less than 18V with a few additional components. An isolated version can be achieved with this topology as described further in Unitrode Application Note U-149. OPERATION With reference to the application diagram below, when input voltage is first applied, the RON current into TON is directed to VCC where it charges the external capacitor, C3, connected to VCC. As voltage builds on VCC, an internal undervoltage lockout holds the circuit off and the output at DRIVE low until VCC reaches 8.4V. At this time, DRIVE goes high turning on the power switch, Q1, and redirecting the current into TON to the timing capacitor, CT. CT charges to a fixed threshold with a current ICHG=0.8 • (VIN - 4.5V)/RON. Since DRIVE will only be high for as long as CT charges, the power switch on time will be inversely proportional to line voltage. This provides a constant line voltage-switch on time product. TYPICAL APPLICATION Note: This device incorporates patented technology used under license from Lambda Electronics, Inc. 2/95 UDG-93060-1 UCC1889 UCC2889 UCC3889 OPERATION (cont.) At the end of the on time, Q1 is turned off and the RON current into TON is again diverted to VCC. Thus the current through RON, which charges CT during the on time, contributes to supplying control power during the off time. IDCHG = (VOUT - 0.7V) / ROFF As VOUT increases, IDCHG increases resulting in the reduction of off time. The frequency of operation increases and VOUT rises quickly to its regulated value. The power switch off time is controlled by the discharge of CT which, in turn, is programmed by the regulated output voltage. The relationship between CT discharge current, IDCHG, and output voltage is illustrated as follows: 3. In this region, a transconductance amplifier reduces IDCHG in order to maintain VOUT in regulation. 4. If VOUT should rise above its regulation range, IDCHG falls to zero and the circuit returns to the minimum frequency established by RS and CT. The range of switching frequencies is established by RON, ROFF, RS, and CT as follows: Frequency = 1/(TON + TOFF) TON = RON • CT • 4.6 V/(VIN - 4.5V) TOFF (max) = 1.4 • RS • CT Regions 1 and 4 TOFF = ROFF • CT • 3.7V /(VOUT - 0.7V) Region 2, excluding the effects of RS which have a minimal impact on TOFF. 1. When VOUT = 0, the off time is infinite. This feature provides inherent short circuit protection. However, to ensure output voltage startup when the output is not a short, a high value resistor, RS, is placed in parallel with CT to establish a minimum switching frequency. The above equations assume that VCC equals 9V. The voltage at TON increases from approximately 2.5V to 6.5V while CT is charging. To take this into account, VIN is adjusted by 4.5V in the calculation of TON. The voltage at TOFF is approximately 0.7V. 2. As VOUT rises above approximately 0.7V to its regulated value, IDCHG is defined by ROFF, and therefore is equal to: DESIGN EXAMPLE The UCC3889 regulates a 12 volt, 1 Watt nonisolated DC output from AC inputs between 80 and 265 volts. In this example, the IC is programmed to deliver a maximum on time gate drive pulse width of 2.4 microseconds which occurs at 80 VAC. The corresponding switching frequency is approximately 100kHz at low line, and overall efficiency is approximately 50%. Additional design information is available in Unitrode Application Note U-149. UDG-93062-3 2 UCC1889 UCC2889 UCC3889 ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAM ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Current into TON Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5mA Voltage on VOUT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Current into TOFF Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250µA Storage Temperature . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Note: Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specified terminals. DIL-8, SOIC-8 (Top View) N or J, D Package ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications hold for TA = 0°C to 70°C for the UCC3889, -40°C to +85°C for the UCC2889, and -55°C to +125°C for the UCC1889. No load at DRIVE pin (CLOAD=0). PARAMETER General VCC Zener Voltage Startup Current Operating Current I(VOUT) Under-Voltage-Lockout Start Threshold Minimum Operating Voltage after Start Hysteresis Oscillator Amplitude CT to DRIVE high Propagation Delay CT to DRIVE low Propagation Delay Driver VOL VOH Rise Time Fall Time Line Voltage Detection Charge Coefficient: ICHG / I(TON) Minimum Line Voltage for Fault Minimum Current I(TON) for Fault On Time During Fault Oscillator Restart Delay after Fault VOUT Error Amp VOUT Regulated 12V (ADJ Open) VOUT Regulated 18V (ADJ = 0V) Discharge Ratio: IDCHG / I(TOFF) Voltage at TOFF Regulation gm (Note 1) TEST CONDITIONS MIN TYP MAX UNITS ICC < 1.5mA VOUT = 0 VOUT = 11V, F = 150kHz 8.6 9.0 150 1.2 9.3 250 2.5 V µA mA VOUT = 0 VOUT = 0 VOUT = 0 8.0 6.0 1.8 8.4 6.3 8.8 6.6 V V V VCC = 9V Overdrive = 0.2V Overdrive = 0.2V 3.5 3.7 100 50 3.9 200 100 V ns ns 0.15 0.7 8.8 7.8 35 30 0.4 1.8 V V V V ns ns 0.79 80 220 2 0.85 100 I = 20mA, VCC = 9V I = 100mA, VCC = 9V I = −20mA, VCC = 9V I = −100mA, VCC = 9V CLOAD = 1nF CLOAD = 1nF VCT = 3V, DRIVE = High, I(TON) = 1mA RON = 330k RON = 330k CT = 150pF, VLINE = Min − 1V 8.5 6.1 0.73 60 70 60 0.5 ms VCC = 9V, IDCHG = I(TOFF)/2 VCC = 9V, IDCHG = I(TOFF)/2 11.2 16.5 11.9 17.5 12.8 19.5 I(TOFF) = 50µA I(TOFF) = 50µA Max IDCHG = 50µA Max IDCHG = 125µA 0.95 0.6 1.01 0.95 1.0 1.7 1.07 1.3 0.8 V µA µs 2.9 V V V mA/V mA/V ∆IDCHG Note 1: gm is defined as for the values of VOUT when VOUT is in regulation. The two points used to calculate gm are for ∆VOUT IDCHG at 65% and 35% of its maximum value. 3 UCC1889 UCC2889 UCC3889 PIN DESCRIPTIONS resistor connected between VOUT and TOFF. ADJ: The ADJ pin is used to provide a 12V or an 18V regulated supply without additional external components. To select the 12V option, ADJ pin is left open. To select the 18V option, ADJ pin must be grounded. For other output voltages less than 18V, a resistor divider between VOUT, ADJ and GND is needed. Note, however, that for output voltages less than VCC, the device needs additional bootstrapping to VCC from an external source such as the line voltage. If so, precautions must be taken to ensure that total ICC does not exceed 5mA. TON (line voltage control): TON serves three functions. When CT is discharging (off time), the current through TON is routed to VCC. When CT is charging (on time), the current through TON is split 80% to set the CT charge time and 20% to sense minimum line voltage which occurs for a TON current of 220µA. For a minimum line voltage of 80V, RON is 330kΩ. The CT voltage slightly affects the value of the charge current during the on time. During this time, the voltage at the TON pin increases from approximately 2.5V to 6.5V. CT (timing capacitor): The signal voltage across CT has a peak-to-peak swing of 3.7V for 9V VCC. As the voltage on CT crosses the oscillator upper threshold, DRIVE goes low. As the voltage on CT crosses the oscillator lower threshold, DRIVE goes high. VCC (chip supply voltage): The supply voltage of the device at pin VCC is internally clamped at 9V. Normally, VCC is not directly powered from an external voltage source such as the line voltage. In the event that VCC is directly connected to a voltage source for additional bootstrapping, precautions must be taken to ensure that total ICC does not exceed 5mA. DRIVE: This output is a CMOS stage capable of sinking 200mA peak and sourcing 150mA peak. The output voltage swing is 0 to VCC. GND (chip ground): All voltages are measured with respect to GND. VOUT (regulated output): The VOUT pin is directly connected to the power supply output voltage. When VOUT is greater than VCC, VOUT bootstraps VCC. TOFF (regulated output control): TOFF sets the discharge current of the timing capacitor through an external BLOCK DIAGRAM UDG-93064-2 4 UCC1889 UCC2889 UCC3889 TYPICAL WAVEFORMS 5 UCC1889 UCC2889 UCC3889 UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. 603-424-2410 • FAX 603-424-3460 6