UCC1890 UCC2890 UCC3890 Off-Line Battery Charger Circuit FEATURES • Transformerless Off-Line Operation • Low Voltage Operation to 0.8V • Ideal for Battery Trickle Charger Applications • Current Mode Operation With 100mV Shunt • Voltage Mode Operation With Fixed 1.25V Output or Resistor Adjustable Output • Efficient BiCMOS Design • Inherent Short Circuit Protection DESCRIPTION The UCC3890 controller is optimized for use as an off-line, low power, low voltage, regulated current supply, ideally suited for battery trickle charger applications. The unique circuit topology used in this device can be visualized as two cascaded flyback converters; each operating in the discontinuous mode, and both driven from a single external power switch. The significant benefit of this approach is the ability to charge low voltage batteries in off-line applications with no transformer, and low internal losses. The control algorithm used by the UCC3890 forces a switch on time inversely proportional to the input line voltage, while the switch off time is inversely proportional to the output voltage. This action is automatically controlled by an internal feedback loop and reference. The cascaded configuration allows a large voltage conversion ratio with reasonable switch duty cycle. While the UCC3890 is ideally suited for control of constant current battery chargers, provision is also made to operate as a fixed 1.25V regulated supply, or to use a resistor voltage divider to obtain output voltages higher than 1.25V. BLOCK DIAGRAM Note: 3/97 This device incorporates patented technology used under license from Lambda Electronics, Inc. UDG-96052 UCC1890 UCC2890 UCC3890 ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5mA Current into TON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5mA Voltage on VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Current into TOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250µA Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C DIL-8, SOIC-8 (Top View) J, N, or D Packages Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = –55°C to 125°C for UCC1890, –40°C to 85°C for the UCC2890, and 0°C to 70°C for the UCC3890. No load at DRIVE pin (CLOAD = 0), TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 8.3 9.0 1.65 9.4 2.0 V mA General VDD Zener Voltage Minimum Operating Current ITON Undervoltage Lockout Minimum Voltage to Start IDD = 4.75mA,ITON = 0mA IDD = –1mA, F = 150kHz FB = 0 7.8 8.6 9.2 V FB = 0 FB = 0 5.75 1.8 6.3 2.3 6.65 2.6 V V FB = 0 0.2 0.4 0.7 V Amplitude CT to DRIVE High Delay ITON = 3mA; ITOFF = 50µA; VFB = 0V CT = 100pF Overdrive = 200mV 3.1 3.4 80 3.7 200 V ns CT to DRIVE Low Delay Charge Coefficient ICT/ITON Overdrive = 200mV ITON = 3mA; VCT = 3.0V 0.135 50 0.15 ITOFF = 50µA; VCT = 3.0V 0.95 1.00 VOL VOH I = 100mA (Note 1) I = –100mA referred to VDD (Note 1) 0.7 –1.5 1.8 –2.9 V V Rise Time Fall Time CL = 1nF CL = 1nF 35 30 70 60 ns ns 1.5 2.0 mA µA µs Minimum Voltage after Start Hysteresis VDD – VSTART Oscillator Discharge Coefficent ICT/ITOFF Driver Line Voltage Detection Minimum ITON for Fault 1.0 ITON Detector Hysteresis On Time During Fault VOUT Error Amplifier Reference Level 100 ns 0.165 µA/µA 1.05 µA/µA 110 0.5 ITOFF = 50µA, ICT = 25µA, TJ = 25°C 1.20 1.25 1.30 V ITOFF = 50µA, ICT = 25µA, Over Temperature ITOFF = 50µA 1.15 0.3 1.25 0.4 1.35 0.5 V V ITOFF = 50µA (Note 2) 2.0 4.0 7.7 mA/V Gain Input Offset Voltage VCS = 90 – 110mV VCS = 90 – 110mV 11.8 –5 12.5 0 13.0 5 V/V mV Input Voltage for CS Amplifier Enabled Input Voltage for CS Amplifier Disabled ITON = 3mA, Referred to VDD ITON = 3mA, Referred to VDD –1.5 –0.8 –0.8 –0.3 V V Voltage at TOFF Regulation gm Current Sense Amplifier Note 1: VDD forced to 100mV below VDD Zener Voltage ∆ICT for the values of VFB where the error amp is in regulation. The two points used to calculate gm ∆VFB are for ICT at 65% amd 35% of its maximum value. Note 2: gm is defined as 2 UCC1890 UCC2890 UCC3890 PIN DESCRIPTIONS CS: The high side of the current sense shunt is connected to this pin. Short CS to VDD for voltage feedback operation. TOFF: Resistor ROFF connects from voltage output to this pin to provide a maximum capacitor discharge current proportional to output voltage. CT: Oscillator timing capacitor is connected to this pin. TON: Resistor RON connects from line input to this pin to provide capacitor charge current proportional to line voltage. The current in RON also provides power for the 9V shunt regulator at VDD. DRIVE: Gate drive to external power switch. FB: Output of current sense amplifier. This pin can be used for direct output voltage feedback if the current sense amp input pin CS is shorted to the VDD pin. VDD: Output of 9V shunt regulator. GND: Ground pin. APPLICATION INFORMATION UDG-96053 Figure 1. Typical Voltage Mode Application OPERATION (VOLTAGE OUTPUT) Figure 1 shows a typical voltage mode application. When input voltage is first applied, all of the current through RDD and 80% of the current through RON, charge the external capacitor C3 connected to VDD. As the voltage builds on VDD, undervoltage lockout holds the circuit off and the output DRIVE low until VDD reaches 8.4V. At this time, DRIVE goes high, turning on the external power switch Q1, and 15% of the current into TON is directed to the timing capacitor CT. The voltage at TON is fixed at approximately 11V, so CT charges to a fixed threshold with current I = 0.2 • the power switch on time is inversely proportional to line voltage. This provides a constant line voltage-switch on time product. At the end of the switch on time, Q1 is turned off, and the 15% of the RON current which was charging CT is diverted to ground. The power switch off time is controlled by discharge of CT, which is determined by the outut voltage as described here: VIN – 11V RON Since the input line is much greater than 11V, the charge current is approximately proportional to the input line voltage. DRIVE is only high while CT is charging, so UDG-96054 3 UCC1890 UCC2890 UCC3890 APPLICATION INFORMATION (cont.) 1. When VOUT = 0, the off time is infinite. This feature provides inherent short circuit protection. However, to ensure output voltage startup when the output is not a short, a high value resistor, RS, is placed in parallel with CT to establish a minimum switching frequency. Frequency = TON = TOFF = VOUT – 0.4V ROFF CT • 3.4V • ROFF (region 2) VOUT − 0.4V The above equations assume VDD = 9, the voltage at TON = 11V, the voltage at TOFF = 0.4V. As VOUT increases, IDCHG increases resulting in the reduction of off time. The frequency of operation increases and VOUT rises quickly to its regulated value. OPERATION (CURRENT OUTPUT) Figure 2 shows a typical current mode application. In current mode, operation is the same as in voltage mode, except that in region 3 the transconductance amplifier is controlled by the current sense amplifier which senses the voltage across a shunt resistor RSH. The circuit then regulates the current in the shunt to the nominal value 3. In this region, a transconductance amplifier reduces IDCHG in order to maintain VOUT in regulation. The input to the transconductance amplifier is the pin FB. (In this mode the pin CS should be shorted to VDD.) FB can either be connected directly to VOUT to regulate at nominal VOUT = 1.25V or to be connected to VOUT through a resistor divider RVS1/RVS2 to regulate at nominal VOUT = CT • 3.4V • 0.15 • RON VIN – 11V TOFF(MAX) = 1.5 • RS • CT (regions1 and 4) 2. As VOUT rises above approximately 0.4V, IDCHG is set by ROFF, and is defined by IDCHG = 1 TON + TOFF ISH = 100mV RSH The circuit shown in this schematic would be suitable for an application which trickle charges a battery at a low current, (e.g. C/10), and has a battery load which draws a high current, (e.g. C), when turned on. In that case, RSH1 value is chosen so that 1.25V • (RVS1 + RVS2) RVS2 4. If VOUT should rise above its regulation range, IDCHG falls to zero and the circuit returns to the minimum frequency established by RS and CT. 100mV C = RSH1 10 The range of switching frequencies is established by RON, ROFF, RS, and CT as follows: UDG-96055 Figure 2. Typical Current Mode Application 4 UCC1890 UCC2890 UCC3890 APPLICATION INFORMATION (cont.) maintain a constant output voltage. For a single flyback stage at continuous conduction boundary If RSH2 is chosen so that 100mV =C RSH2 d= then the regulator output will assist the battery, minimizing or eliminating battery output current. For the cascaded flyback stages of the UCC3890 topology, the corresponding equation is DESIGN EXAMPLE A typical design has the following requirements: VIN VOUT VOUT′ = = = ILOAD = FSWITCHING = η (eff.) = 1 VIN 1+ VOUT 1 d(max) = 80 to 132 VAC or 100 to 180 VDC 1.25V 2.0V (assumes 1.25 VOUT with 750mV forward drop in D3) 500mADC max 100kHz 50% (excluding efficiency losses in D3 which will be very large due to the low output voltage. Losses in D3 are accounted for by using VOUT′ in the calculations). 1+ V √ V ′ IN OUT in this case 1 d(max) = 1+ √ = 0.125 100V 2V Next using the operating frequency and the maximum duty cycle to calculate the maximum on time TON(max) = Component values are indicated in Figure 3. The explanation for the choices in component values follows. d(max) FSWITCHING in this case First calculate the maximum duty cycle, d(max). To calculate this assume that at maximum load/minimum line conditions, the converter will be at the continuous conduction boundary and there will be no idle time after the inductors are discharged. For all other load/line conditions, the UCC3890 will stretch the off time, to create an idle time after the inductors are discharged, in order to TON(max) = 0.125 = 1.25µs 100kHz correspondingly TOFF(min) = 1 − 0.125 = 8.75µs 100kHz UDG-96056 Figure 3. Example Application 5 UCC1890 UCC2890 UCC3890 APPLICATION INFORMATION (cont.) The average input current at minimum line and maximum load will be IIN = entire range of operation must be considered to choose values for the rest of the components. IOUT VOUT′ • VIN η Under all normal operating conditions the current ITON, (which is the current in RON), should be greater than 2mA and less than 7.5mA. In this case set RON to give ITON = 2.8mA at low line. The voltage at TON will be about 11V so in this case IIN = 500mA 2V = 20mA • 100V 0.5 With RON = 33k, ITON at high line will be TON + TOFF IL1(pk) = 2 • IIN • TON ITON = in this case P(RON) = (180V − 11V) • 5.1mA = 860mW RON will need to be at least a 1W resistor. Alternately it could be four 1/4W 8.2kΩ resistors in series. Now calculate the value for L1 TON IL1(pk) Once RON is set, CT can be chosen. The charge current for CT is nominally 15% of ITON, and the nominal oscillator amplitude is 3.4V, so in this case L1 = 100V • 1.25µs = 390µH 320mA TON = TON TOFF CT = 1.25µs = 14.3V 8.75µs CT = Knowing that output current is provided to the load only during TOFF, calculate the peak current in L2 to be IL2(pk) = 2 • IOUT • TON + TOFF TOFF 1.25µs + 8.75µs = 1.14A 8.75µs TOFF = ITOFF = TOFF IL2(pk) VOUT − 0.4V ROFF substituting and solving for ROFF in this case L2 = 2V • CT • 3.4V ITOFF since the voltage at the TOFF pin = 0.4V Now calculate the value of L2 L2 = VOUT′ • 1.25µs • 0.15 • 2.8mA = 150pF 3.4V The final component to be chosen is ROFF, which determines the minimum value of TOFF. When the output voltage is below the regulation point, the discharge current for CT is equal to ITOFF (the current in ROFF). Under that condition in this case IL2(pk) = 2 • 0.5A • TON • 0.15 • ITON 3.4V ITON at low line is 2.8mA, and the target TON at low line is 1.25µs, so in this case in this case VC1 = 100V • CT • 3.4V 0.15 • ITON solving for CT The output voltage of the first flyback stage is VC1 = VIN • 180V − 11V = 5.1mA 33k At high line, the power dissipation in RON will be 1.25µs + 8.75µs = 320mA IL1(pk) = 2 • 20mA • 1.25µs L1 = VIN • 100V − 11V = 33kΩ 2.8mA RON = Knowing that input current is drawn from the line only during TON, calculate the peak current in L1 to be ROFF = 8.75µs = 15µH 1.14A TOFF • (VOUT − 0.4V) CT • 3.4V The largest discharge current, and hence the minimum off time, will occur when the output is about 10mV be- For all of the calculations so far only the maximum load/minimum line condition have been considered. The 6 UCC1890 UCC2890 UCC3890 APPLICATION INFORMATION (cont.) ple clamp on the output may not be adequate. In current sense mode it is recommended that a second zener be connected from the output to the FB pin, the breakdown voltage of this clamp chosen to be high enough so that it will not conduct during normal operation, but will conduct at least 2V lower than the breakdown voltage of the other clamp. low the regulation point of 1.25V. The minimum value for TOFF is 8.75µs. So in this case ROFF = 8.75µs • (1.24V − 0.4V) = 15k 150pF • 3.4V OTHER APPLICATION CONSIDERATIONS Output Capacitor: For best regulation of the output voltage or current, the output capacitor should be a low ESR type. This is especially true when operating in current sense mode with a non-linear load such as a battery. If a low ESR capacitor cannot be used, excellent regulation can also be achieved by placing a low pass R/C filter between the current shunt and the CS input. Gate Drive for the External FET: The UCC3890 is guaranteed to be able to deliver at least 1mA of steady state current to the gate of the external FET at ITON = 2mA. If ITON is higher than 2mA, 80% of the additional current is available to drive the FET gate. If, as in the design example above, a moderate sized FET such as the IRF820 is used, the operating frequency is 100kHz, and the minimum ITON at low line is 2.8mA, then the available gate drive current may be adequate. The IRF820 needs about 13nC to charge the gate on each cycle. At 100kHz, this is equivalent to 1.3mA steady state; below the minimum 1.64mA available. In some combinations of a larger FET, and/or higher frequency operation, the current available for driving the gate may not be adequate. In that case extra current may be provided by connecting a resistor RDD from the line input to the VDD pin. This resistor should be sized so that under all conditions the current input to VDD is below the 7.5mA absolute maximum limit. RDD will likely need to be a power resistor. No Load Operation: The UCC3890 is inherently protected for short circuits, but not for open circuits. If the load is removed, the output voltage will quickly rise up to the regulation point. Once the output is above the regulation voltage, the oscillator will drop to the minimum frequency set by RS/CT. With no load on the output, even at this low frequency the output voltage can quickly rise to a dangerous level. To protect against this, it is recommended that a zener or other voltage clamp always be connected across the output. The clamp should be chosen to be above the normal range of output voltage, but low enough to protect the output capacitor. In current sense operation, removal of the load will also break the regulation loop, in which case a sim- UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. 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