AD AD1984AJCPZ

High Definition Audio
SoundMAX Codec
AD1984A
FEATURES
STEREO DIGITAL MICROPHONE INTERFACE
Microsoft Vista Premium Logo for desktop
96+ dB audio outputs, 90 dB audio inputs
WLP 3.0 and 4.0
Security feature prevents unauthorized recording
2 stereo headphone amplifiers
Internal 32-bit arithmetic for greater accuracy
Impedance and presence detection on all jacks
Full analog mixer with DAC inputs
3 independent microphone bias pins
Digital and analog PCBeep
3 general-purpose digital I/O (GPIO) pins
3.3 V analog supply voltage
1.7 V to 1.9 V or 3.3 V digital supply voltages
1.5 V or 3.3 V HD Audio link signaling voltage
Advanced power management modes
48-lead, RoHS compliant LFCSP_VQ package
Two 192 kHz digital microphone channels
Supports 1 or 2 microphones per pin
Selectable bit clock rates of 1.5 MHz, 2.0 MHz, and 3.0 MHz
Mono and stereo array support
8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz, 44.1 kHz,
48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz
sample rates
16-, 20-, and 24-bit resolution
S/PDIF OUTPUT
Supports 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and
192 kHz sample rates
16-, 20-, and 24-bit data; PCM and AC3 formats
Digital PCM gain control
AUXILIARY PINS
Stereo CD/auxiliary I/O port with ground sense
Stereo auxiliary/dock I/O port
Mono out pin for internal speakers or telephony
192 kHz DACs/ADCs
2 independent stereo DAC/ADC pairs
Simultaneous record of 2 stereo channels
Simultaneous playback of 2 stereo channels
Independent 8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz,
44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz
sample rates
16-, 20-, and 24-bit resolution
Selectable stereo mixer on outputs
H
D
A
U
D
I
O
I
N
T
E
R
F
A
C
E
DAC1
⌺
HP
PORT A
DAC0
⌺
HP
PORT D
⌺
MONO OUT
⌺
PORT E
⌺
PORT F
S/PDIF
DIGITAL
PCBEEP
PCBEEP
⌺
PORT B
ADC0
PORT C
ADC1
DM_1/2
DIGITAL
MICROPHONE
AD1984A
DM_2
DM_CLK
Figure 1. Functional Block Diagram
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD1984A
TABLE OF CONTENTS
Features ................................................................. 1
Revision History ...................................................... 2
General Description ................................................. 3
Additional Information .......................................... 3
Jack Configuration ................................................ 3
AD1984A Specifications ............................................ 4
Test Conditions .................................................... 4
Performance ........................................................ 4
General Specifications ............................................ 4
HD Audio Link Specification ................................... 7
Power-Down States ............................................... 7
Absolute Maximum Ratings .................................... 8
ESD Caution ........................................................ 8
Environmental Conditions ...................................... 8
Pin Configuration and Function Descriptions ................. 9
Digital Microphone Interface Timing Specifications ....... 12
HD Audio Widgets ................................................ 14
HD Audio Parameters ............................................. 15
Widget Parameters ................................................. 16
Connection List ..................................................... 17
Default Configuration Bytes ..................................... 18
Outline Dimensions ............................................... 19
Ordering Guide ..................................................... 19
REVISION HISTORY
4/08—Rev 0. Initial version
Rev. 0 |
Page 2 of 20 |
April 2008
AD1984A
GENERAL DESCRIPTION
The AD1984A audio codec and SoundMAX® software provide
superior high definition audio quality that exceeds Vista Premium performance. The AD1984A has two 192 kHz DAC pairs,
two 192 kHz ADC pairs, an S/PDIF output, a 2-channel digital
microphone interface, and digital and analog PCBeep. These
features make the AD1984A the right choice for desktop and
notebook PCs where performance is key.
The AD1984A is available in a 48-lead, RoHS compliant lead
frame chip scale package in both reels and trays. See Ordering
Guide on Page 19.
Table 3. Typical Notebook Configuration with Dock
Interface
Port
Port A
Port B
Port C
Port D
Port E
Port F
S/PDIF
ADDITIONAL INFORMATION
This data sheet provides a general overview of the AD1984A
SoundMAX codec’s architecture and functionality. Detailed
widget information is available in the AD1984A Programmers
Reference Manual. Please contact your local Analog Devices,
Inc., sales representative for more information.
JACK CONFIGURATION
The guidelines shown in Table 1 through Table 3 should be
used when selecting ports for particular functions.
Table 1. Typical Desktop Configuration
Port
Port A
Port B
Port C
Port D
S/PDIF
Function
Front Panel Headphone
Front Panel Microphone
Rear Panel Line-In/Microphone
Rear Panel Line-Out/Headphone
Optical/RCA S/PDIF Output
Table 2. Typical Notebook Configuration
Port
Port A
Port B
Port C
Port F
S/PDIF
Function
Headphone
Microphone
Internal Microphone
Internal Stereo Speakers
Optical/RCA S/PDIF Output
Rev. 0 |
Page 3 of 20 |
April 2008
Function
Headphone
Microphone
Internal Microphone
Dock Line-Out/Headphone
Dock Line-In/Microphone
Internal Stereo Speakers
Optical/RCA S/PDIF Output
AD1984A
AD1984A SPECIFICATIONS
TEST CONDITIONS
Parameter
Temperature
Digital Supply
Analog Supply
MIC_BIAS_IN (via Low-Pass Filter)
Sample Rate FS
Input Signal (Frequency Sine Wave)
Amplitude for THD + N
Analog Output Pass Band
DAC1
Test Condition
25°C
3.3 V
3.3 V
5.0 V
48 kHz
1008 Hz
–3.0 dB Full Scale
20 Hz to 20 kHz
10 kΩ Output Load: Line-Out Tests
32 Ω Output Load: Headphone Tests
0 dB Gain
ADC
1
DAC/ADC tests are performed with AES-17 filter enabled.
PERFORMANCE
Parameter
Line-Out Drive (10 kΩ loads—DAC to Pin)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in ref to fS A-Weighted)
Signal-to-Noise Ratio
Headphone Drive (32 Ω loads—DAC to Pin)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in ref to fS A-Weighted)
Signal-to-Noise Ratio
Microphone/Line-In (Pin to ADC, Mic Boost = 0 dB)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in ref to fS A-Weighted)
Signal-to-Noise Ratio
Min
Typ
Max
Unit
–86
96
96
dB
dB
dB
–80
96
96
dB
dB
dB
–81
90
90
dB
dB
dB
GENERAL SPECIFICATIONS
Parameter
DIGITAL DECIMATION AND INTERPOLATION FILTERS—fS = 8 kHz to 192 kHz1
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Rejection
Group Delay
Group Delay Variation over Pass Band
ANALOG-TO-DIGITAL CONVERTERS
Resolution
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error1
ADC Crosstalk1
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
Line Inputs to Other
Rev. 0 |
Page 4 of 20 |
Min
Typ
0
Max
Unit
0.4 fS
±0.005
Hz
dB
Hz
dB
1/fS
μs
0.6 fS
–100
20
0
24
±0.2
–85
–100
April 2008
±10
±0.5
±5
Bits
%
dB
mV
–80
dB
dB
AD1984A
Parameter
DIGITAL-TO-ANALOG CONVERTERS
Resolution
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)1
Interchannel Gain Mismatch (Difference of Gain Errors)
Total Audible Out-of-Band Energy (Measured from 0.6 × fS to 20 kHz)1
DAC Crosstalk (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT)1
DAC VOLUMES
Step Size
Output Gain/Attenuation Range
Mute Attenuation of 0 dB Fundamental1
ADC VOLUMES
Step Size
PGA Gain/Attenuation Range
ANALOG MIXER
Signal-to-Noise Ratio Input to Output—Ports B, C, E, or F to Port D Output
Step Size: All Mixer Inputs
Input Gain/Attenuation Range: All Mixer Inputs
ANALOG LINE LEVEL OUTPUTS
Full-Scale Output Voltage
Min
Typ
Max
24
±10
±0.5
–85
–95
1.5
–58.5
0
–80
1.5
–58.5
Bits
%
dB
dB
dB
dB
dB
dB
+22.5
dB
dB
+12.0
dB
dB
dB
95
–1.5
–34.5
Unit
1.0
2.83
V rms
V p-p
Ports A, D, E, F, and Mono Out
Output Impedance1
External Load Impedance1
Output Capacitance1
External Load Capacitance
190
10
15
1000
ANALOG HP DRIVE OUTPUTS
Full-Scale Output Voltage
1.0
2.83
Ω
kΩ
pF
pF
V rms
V p-p
Ports A and D
Output Impedance1
External Load Impedance1
Output Capacitance1
External Load Capacitance1
0.5
32
15
1000
Ω
Ω
pF
pF
ANALOG INPUTS
Input Voltages—Ports B, C, E, or F
Mic Boost = 0 dB
Input Voltages—Microphone Boost
Amplifier, Ports B, C, or E
Mic Boost = 10 dB
Mic Boost = 20 dB
Mic Boost = 30 dB
Input Impedance
PCBeep
Ports B, C, E (Mic Boost = 0 dB)
Port F
Input Capacitance1
Rev. 0 |
Page 5 of 20 |
April 2008
1
2.83
0.316
0.894
0.1
0.283
0.032
0.089
V rms
V p-p
V rms
V p-p
V rms
V p-p
V rms
V p-p
23
150
45
5
kΩ
kΩ
kΩ
pF
7.5
AD1984A
Parameter
MICROPHONE BIAS
MIC_BIAS-B, MIC_BIAS-C
MIC_BIAS_IN (Pin 33) = 5 V or 3.3 V
MIC_BIAS_IN (Pin 33) = 5 V
MIC_BIAS_IN (Pin 33) = 3.3 V
MIC_BIAS-E (When Enabled as BIAS)
Output Drive Current
GPIO 0
Input Signal High (VIH)
Input Signal Low (VIL)
Output Signal High (VOH)
Output Signal Low (VOL)
Input Leakage Current (Signal High) (IIH)
Input Leakage Current (Signal Low) (IIL)
GPIO 1 and GPIO 2
Input Signal High (VIH)
Input Signal Low (VIL)
Output Signal High (VOH)
Output Signal Low (VOL)
Input Leakage Current (Signal High) (IIH)
Input Leakage Current (Signal Low) (IIL)
DM Clock
Output Signal High (VOH)
Output Signal Low (VOL)
DM_1/2 and DM_2
Input Signal High (VIH)
Input Signal Low (VIL)
Input Leakage Current (Signal High) (IIH)
Input Leakage Current (Signal Low) (IIL)
S/PDIF
Input Signal High (VIH)
Input Signal Low (VIL)
Output Signal High (VOH)
Output Signal Low (VOL)
Input Leakage Current (Signal High) (IIH)
Input Leakage Current (Signal Low) (IIL)
Min
Typ
Max
Unit
VREF Setting = High-Z
VREF Setting = 0 V
VREF Setting = 50%
VREF Setting = 80%
VREF Setting = 100%
VREF Setting = 80%
VREF Setting = 100%
High-Z
0
1.65
3.7
3.9
2.86
3.0
V dc
V dc
V dc
V dc
V dc
V dc
VREF Setting = High-Z
VREF Setting = 0 V
VREF Setting = 50%
VREF Setting = 80%
VREF Setting = 100%
High-Z
0
1.65
2.86
3.0
V dc
V dc
V dc
V dc
VREF Setting = 50%, 80%, or 100%
1.6
mA
DVIO × 0.60
0
DVIO × 0.72
0
IOUT = –500 μA
IOUT = +1500 μA
DVIO
DVIO × 0.24
DVIO
DVIO × 0.10
V
V
V
V
nA
μA
AVDD
AVDD × 0.24
AVDD
AVDD × 0.10
V
V
V
V
nA
μA
AVDD × 0.72
0
AVDD
AVDD × 0.10
V
V
AVDD × 0.60
0
AVDD
AVDD × 0.24
V
V
nA
nA
DVIO
DVIO × 0.24
DVIO
DVIO × 0.10
V
V
V
V
nA
μA
150
–50
AVDD × 0.60
0
AVDD × 0.72
0
IOUT = –500 μA
IOUT = +1500 μA
150
–50
IOUT = –500 μA
IOUT = +1500 μA
–150
–50
DVIO × 0.60
0
DVIO × 0.72
0
IOUT = –500 μA
IOUT = +1500 μA
150
–50
Rev. 0 |
Page 6 of 20 |
April 2008
AD1984A
Parameter
POWER SUPPLY
Analog (AVDD) 3.3 V ± 5%
Power Supply Range
Power Dissipation
Supply Current
Digital (DVDD) 3.3 V ± 10%
Power Supply Range
Power Dissipation
Supply Current
Digital (DVCORE) 1.7 through 1.9 V ± 10%
Power Supply Range
Power Dissipation
Supply Current
Digital I/O (DVIO) 3.3 V ± 10%
Power Supply Range
Power Dissipation
Supply Current
Digital I/O (DVIO) 1.5 V ± 5.5%
Power Supply Range
Power Dissipation
Supply Current
Power Supply Rejection (Reference to fS 100 mV p-p Signal @ 1 kHz)1
1
Min
Typ
Max
Unit
3.13
3.30
75.9
23
3.46
V
mW
mA
2.97
3.30
141.9
43
3.63
V
mW
mA
1.615
1.70
61
36
1.995
V
mW
mA
2.97
3.30
3.3
1
3.63
V
mW
mA
1.418
1.50
0.08
0.05
80
1.583
V
mW
mA
dB
IDVDD Typ (1.7 V)
36
15.75
7.5
3
IDVDD Typ (3.3 V)
43
17
7.5
3
IAVDD Typ
23
1
1
3
Unit
mA
mA
mA
mA
4.5
4.5
0
0
0
6
6
0
0
0
5
3
2
1
0.1
mA
mA
mA
mA
mA
Guaranteed but not tested.
HD AUDIO LINK SPECIFICATION
High definition audio signals comply with the High Definition
Audio Specification. Please refer to these specifications at
www.intel.com/standards/hdaudio.
POWER-DOWN STATES
Parameter
Function Node in D0, All Nodes Active
Function Node in D3
Function Node in D31
Codec in RESET
Individual Block Power Savings
DAC Pair Powered Down Saves (Each)
ADC Pair Powered Down Saves (Each)
Mixer Power Control (and Associated Amps) Saves
DM_CLK Powered Down Saves2
MIC_BIAS Powered Down Saves3
1
Maximum power saving mode; Register 0x31FD, Bit 4.
Test conditions: 30 pF load, 2.0 MHz frequency, 3.3 V AVDD.
3
Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits set to 100% or 50%, setting them to the high-Z state. The
0 V and high-Z states remain unaffected by the MIC_BIAS power state.
2
Rev. 0 |
Page 7 of 20 |
April 2008
AD1984A
ABSOLUTE MAXIMUM RATINGS
ENVIRONMENTAL CONDITIONS
Stresses greater than those listed below may cause permanent
damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above
those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Ambient Temperature Rating:
Parameter
Digital (DVDD)
Digital (DVCORE)
Digital I/O (DVIO)
Analog (AVDD)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
Storage Temperature
Rating
–0.30 V to +3.65 V
–0.30 V to +2.10 V
–0.30 V to +3.65 V
–0.30 V to +3.65 V
±10.0 mA
–0.30 V to AVDD +0.3 V
–0.30 V to DVIO +0.3 V
0°C to +70°C
–65°C to +150°C
TAMB = TCASE – (PD × θCA)
TCASE = case temperature in °C
PD = power dissipation in W
θCA = thermal resistance (case-to-ambient)
θJA = thermal resistance (junction-to-ambient)
θJC = thermal resistance (junction-to-case)
All measurements per EIA-JESD51 with 2S2P test board per
EIA-JESD51-7.
Package
LFCSP_VQ
ESD CAUTION
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Rev. 0 |
Page 8 of 20 |
April 2008
θJA
47
θJC
15
θCA
32
Unit
°C/W
AD1984A
SPDIF_OUT
EAPD/GPIO_0
DM_CLK
RESERVED (NC)
RESERVED (NC)
RESERVED (NC)
AVSS
PORT-A_R
RESERVED (NC)
PORT-A_L
AVDD
RESERVED (NC)
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48
47
46
45
44
43
42
41
40
39
38
37
DVCORE
1
36
PORT-D_R
DM_1/2
2
35
PORT-D_L
DVIO
3
34
SENSE_B/SRC_A
DM_2
4
33
MIC_BIAS_IN
32
MONO_OUT
31
MIC_BIAS-E/GPIO_1
30
GPIO_2
29
MIC_BIAS-C
28
MIC_BIAS-B
27
VREF_FLT
SDATA_OUT
5
BIT_CLK
6
AD1984AJCP
TOP VIEW
DVSS
7
(Not To Scale)
12
25
AVDD
14
15
16
17
18
19
20
21
22
23
24
PORT-C_R
13
PORT-C_L
PCBEEP
PORT-B_R
AVSS
PORT-B_L
26
RESERVED (NC)
11
CD_GND (PORT F)
RESET
RESERVED (NC)
10
PORT-F_R
SYNC
PORT-F_L
9
PORT-E_R
DVDD
PORT-E_L
8
SENSE_A/SRC_B
SDATA_IN
Figure 2. AD1984A 48-Lead Package and Pinout
Rev. 0 |
Page 9 of 20 |
April 2008
AD1984A
Table 4. Pin Function Descriptions
Mnemonic
DIGITAL INTERFACE
SDATA_OUT
Pin No.
I/O
Description
5
I
6
8
I
I/O
10
11
I
I
Link Serial Data Output. AD1984A input stream. Clocked on both edges of the
BIT_CLK.
Link Bit Clock. 24.000 MHz serial data clock.
Link Serial Data Input. AD1984A output stream clocked only on one edge of BIT_CLK.
Link Frame Sync.
Link Reset. AD1984A master hardware reset.
2
I
DM_2
DM_CLK
GPIO_2
4
46
30
I
O
I/O
MIC_BIAS-E/GPIO_1
31
I/O
EAPD/GPIO_0
47
I/O
48
O
Digital Microphone 1 and 2 Inputs (for Biphase Microphones), or Digital Microphone
1 Input (for Single-phase Microphones).
Digital Microphone 2 Input (for Single-phase Microphones).
Clock to Drive External Digital Microphones.
General-Purpose Input/Output Pins. Digital signals used to control or sense external
circuitry.
Microphone Bias for Port E/General-Purpose Input/Output. Capable of high-Z, 1.65 V,
and 2.86 V. Pin 31 shares functionality between MIC_BIAS_E (default) and GPIO_1.
These functions are mutually exclusive and the MIC_BIAS function takes priority over
the GPIO function.
EAPD/General-Purpose Input/Output pin. Pin 47 shares functionality between
GPIO_0 and EAPD. These functions are mutually exclusive and the EAPD function
takes priority over the GPIO function. By default, the pin is in a high-Z state. External
resistors should be used to ensure the proper circuit state when this pin is in high-Z.
Supports S/PDIF Output.
13
34
I/O
I/O
Jack Sense A-D Input/Sense B drive.
Jack Sense E-F Input/Sense A drive.
BIT_CLK
SDATA_IN
SYNC
RESET
DIGITAL I/O and EAPD
DM_1/2
SPDIF_OUT
JACK SENSE
SENSE_A/SRC_B
SENSE_B/SRC_A
ANALOG I/O
PCBEEP
PORT-E_L
PORT-E_R
PORT-F_L
PORT-F_R
CD_GND (PORT F)
Monaural Input from System for Analog PCBeep.
Auxiliary Input/Output Left Channel.
Auxiliary Input/Output Right Channel.
Auxiliary Input/Output Left Channel.
Auxiliary Input/Output Right Channel.
CD Audio Analog Ground Reference. Must be connected to AGND via a 0.1 μF
capacitor if not in use as CD_GND. MUST always be ac-coupled.
Front Panel Stereo MIC/Line-In.
LI, MIC
PORT-B_L
21
Front Panel Stereo MIC/Line-In.
LI,
MIC
PORT-B_R
22
Rear Panel Stereo MIC/Line-In.
LI,
MIC
PORT-C_L
23
Rear Panel Stereo MIC/Line-In.
LI,
MIC
PORT-C_R
24
Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone.
LO
MONO_OUT
32
PORT-D_L
Rear Panel Headphone/Line-Out.
HP, LO
35
PORT-D_R
Rear Panel Headphone/Line-Out.
HP, LO
36
PORT-A_L
Front Panel Headphone/Line-Out.
HP, LO
39
PORT-A_R
Front Panel Headphone/Line-Out.
HP, LO
41
The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving
headphone load, MIC = input supports microphones with MIC bias and boost amplifier.
12
14
15
16
17
19
LI
LI, MIC, LO
LI, MIC, LO
LI, LO
LI, LO
I
Rev. 0 | Page 10 of 20 |
April 2008
AD1984A
Table 4. Pin Function Descriptions (Continued)
Mnemonic
FILTER/MIC_BIAS
VREF _FILT
MIC_BIAS-B
MIC_BIAS-C
MIC_BIAS_IN
5.0 V or 3.3 V
POWER AND GROUND
DVCORE 1.7 V to 1.9 V or
FILTER
Pin No.
I/O
Description
27
28
29
O
O
O
33
I
Voltage Reference Filter.
Switchable Microphone Bias. For use with Port B (Pins 21, 22).
Switchable Microphone Bias. For use with Port C (Pins 23, 24).
Both MIC bias pins are capable of high-Z, 0 V, 1.65 V, 3.7 V, and 3.9 V (with 5.0 V on
Pin 33), high-Z, 0 V, 1.65 V, 2.86 V, and 3.0 V (with 3.3 V on Pin 33).
Source Power for Microphone Bias Boost Circuitry.
Connect this pin to 5.0 V via a low-pass filter. When connected this way the AD1984A
is capable of providing 3.9 V as a mic bias to all of the mic bias pins (except on Pin 31).
If 5 V is not available, connect this pin to 3.3 V (AVDD) via a low-pass filter.
1
I/O
CAUTION: DO NOT APPLY 3.3 V TO THIS PIN! Filter connection for internal core
voltage regulator.
If Pin 9 is connected to 3.3V DVDD, this pin must be connected to filter caps: 10μF,
1.0 μF, and 0.1 μF connected in parallel between Pin 1 and DVSS (pin 7). Direct, filtered
1.7 V to 1.9 V DVDD may be applied to Pin 1 to lower the digital power requirements.
Pin 9 MUST be connected to Pin 1 in this case.
DVIO 1.5 V or 3.3 V
3
I
Link Digital I/O Voltage Reference. 3.3 V ± 10% or 1.5 V ± 5.5%
7
I
Digital Supply Return (Ground).
DVSS
DVDD 1.7 V to 1.9 V or 3.3 V 9
I
Digital Supply Voltage 3.3 V ± 10%. This is regulated down to DVCORE on Pin 1 to
supply the internal digital core internal to the AD1984A. Direct, filtered 1.7 V to 1.9 V
DVDD may be applied to Pin 1 to lower the digital power requirements. Pin 9 MUST be
connected to Pin 1 in this case.
25, 38
I
CAUTION: DO NOT APPLY 5 V TO THESE PINS! Analog Supply Voltage 3.3 V ONLY.
AVDD 3.3 V
Note: AVDD supplies should be well regulated and filtered as supply noise degrades
audio performance.
26, 42
I
Analog Supply Return (Ground). AVSS should be connected to DVSS using a
AVSS
conductive trace under, or close to, the AD1984A.
The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving
headphone load, MIC = input supports microphones with MIC bias and boost amplifier.
Rev. 0 |
Page 11 of 20 |
April 2008
AD1984A
DIGITAL MICROPHONE INTERFACE TIMING SPECIFICATIONS
The digital microphone interface can support one or two digital
microphones using two or three codec pins. Both uniplex (one
microphone per data pin) and multiplex (two microphones
sharing the same data pin) are supported. The timing for these
configurations is shown in Table 5 and Figure 3, Figure 4 and
Figure 5. The interface can generate a microphone clock at
1.5 MHz, 2.0 MHz, or 3.0 MHz to suit quality and power
requirements.
Table 5. Microphone Timing Parameters
Parameter Description
Timing Requirements
t0
DM_CLK (1.5 MHz) Period
Duty Cycle
t0
DM_CLK (2.0 MHz) Period
Duty Cycle
DM_CLK (3.0 MHz) Period
t0
Duty Cycle
DM_CLK Rise Time
t1
t2
DM_CLK Fall Time
Data Setup to DM_CLK Edge
t3
t4
Data Hold from DM_CLK Edge
Min
Typ
Max
667
50/50
500
50/50
333
50/50
ns
%
ns
%
ns
%
ns
ns
ns
ns
5
5
10
5
t0
t1
t2
t1
t2
DM_CLK
t3
t4
DM_1/2
DATA VALID
Figure 3. Uniplex Microphone Timing
t0
DM_CLK
t3
DM_2
t4
DATA VALID
Figure 4. DM_2 Uniplex Microphone Timing
Rev. 0 | Page 12 of 20 |
April 2008
Unit
AD1984A
t0
t1
t2
DM_CLK
t3
t4
DM_1/2
LEFT DATA VALID
t3
t4
RIGHT DATA VALID
Figure 5. Multiplex Microphone Timing
Rev. 0 |
Page 13 of 20 |
April 2008
LEFT DATA VALID
AD1984A
HD AUDIO WIDGETS
Table 6. HD Audio Widgets1
Node ID
0x00
0x01
0x02
0x03
0x04
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
1
Name
ROOT
FUNCTION
S/PDIF DAC
DAC_0
DAC_1
Port A Mixer
ADC_0
ADC_1
Port D Mixer
Port F Mixer
ADC Selector 0
ADC Selector 1
Mono Out Selector
Port F Out Selector
Digital Beep
Port A (Headphone)
Port D (Line Out)
Mono Out
Port B (Mic In)
Port C (Line In)
Port F (Aux In/Out)
Dig Microphone
Mixer Power Down
Analog PCBeep
S/PDIF-Out
Port E (Dock I/O)
VREF Power Down
Mono Out Mixer
Stereo Mix-Down
Analog Mixer
Mixer Output Atten
Port A Out Selector
Port E Out Selector
Port E Mixer
Port E Mic Boost
BIAS Power Down
Type ID
x
x
0
0
0
2
1
1
2
2
3
3
3
3
7
4
4
4
4
4
4
4
5
4
4
4
F
2
2
2
3
3
3
2
3
F
Type
Root
Function
Audio Output
Audio Output
Audio Output
Audio Mixer
Audio Input
Audio Input
Audio Mixer
Audio Mixer
Audio Selector
Audio Selector
Audio Selector
Audio Selector
Beep Generator
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Power Widget
Pin Complex
Pin Complex
Pin Complex
Vendor Defined
Audio Mixer
Audio Mixer
Audio Mixer
Audio Selector
Audio Selector
Audio Selector
Audio Mixer
Audio Selector
Vendor Defined
Description
Device identification
Designates this device as an audio codec
S/PDIF digital stream output interface
Stereo headphone channel digital/audio converter
Stereo front channel digital/audio converter
Mixes the DAC_(0, 1) and analog mixer output to drive Port A
Stereo record Channel 0 audio/digital converters
Stereo record Channel 1 audio/digital converters
Mixes the DAC_1 and analog mixer output to drive Port D
Mixes the DAC_(0, 1) and analog mixer output to drive Port F
Selects and amplifies/attenuates the input to ADC_0
Selects and amplifies/attenuates the input to ADC_1
Selects the mono out DAC_(0, 1)
Selects the Port F DAC_(0, 1)
Internal digital PCBeep signal
Headphone jack pins
Line out jack pins
Monaural output pin (internal speakers or telephony system)
Microphone in jack pins
Line in jack pins
Auxiliary I/O pins
Digital microphone input pin
Powers down the analog mixer and associated amps
External analog PCBeep signal input
S/PDIF output pin
Analog dock I/O pins
Powers down the VREF circuitry
Mixes the DAC_(0, 1) and analog mixer output to drive mono out
Mixes the stereo L/R channels to drive mono output
Mixes individually gainable analog inputs
Attenuates the analog mixer output to drive the port mixers
Selects the Port A DAC_(0, 1)
Selects the Port E DAC_(0, 1)
Mixes the DAC_(0, 1) and analog mixer output to drive Port E
0 dB, 10 dB, 20 dB, or 30 dB gain boost for Port E
Powers down the internal MIC_BIAS_FILT and all MIC_BIAS pins
All node IDs (NIDs) are sequential in the codec. Any NIDs missing for this table are vendor defined.
Rev. 0 | Page 14 of 20 |
April 2008
AD1984A
HD AUDIO PARAMETERS
Table 7. Root and Function Node Parameters
Node ID
0x00
0x01
1
Name
ROOT
FUNCTION
Vendor ID
00
0x11D4 194A
Revision ID
021
0x0010 0400
Sub Node Count Func. Group Type
04
05
0x0001 0001
0x0002 0029
0x0000 0001
Audio F.G. Caps
08
GPIO Caps
11
0x0001 0C0C
0x4000 0003
Subject to change with silicon stepping.
Table 8. Subsystem ID
Node ID
0x01
Name
FUNCTION
Type
Function
Value
0xBFD4 0000
Rev. 0 |
Page 15 of 20 |
31:16
SSID
0xBFD4
April 2008
15:8
SKU
0x00
7:0
ASM ID
0x00
AD1984A
WIDGET PARAMETERS
Table 9. Widget Parameters
Node
ID
0x01
0x02
0x03
0x04
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
Widget
Capabilities
0x09
0x0000 04C0
0x0003 0211
0x0000 0405
0x0000 0405
0x0020 0103
0x0010 0501
0x0010 0501
0x0020 0103
0x0020 0103
0x0030 010D
0x0030 010D
0x0030 0101
0x0030 0101
0x0070 000C
0x0040 018D
0x0040 058D
0x0040 050C
0x0040 008B
0x0040 008B
0x0040 058D
0x0040 020B
0x0050 0500
0x0040 0000
0x0040 038D
0x0040 018D
0x00F0 0100
0x0020 0103
0x0020 0100
0x0020 010B
0x0030 010D
0x0030 0101
0x0030 0101
0x0020 0103
0x0030 010D
0x00F0 0100
PCM Size,
Rate
0x0A
0x000E 07FF
0x000E 07E0
0x000E 07FF
0x000E 07FF
Stream
Formats
0x0B
0x0000 0001
0x0000 0005
0x0000 0001
0x0000 0001
0x000E 07FF
0x000E 07FF
0x0000 0001
0x0000 0001
Pin
Capabilities
0x0C
Input Amp
Capabilities
0x0D
0x8000 0000
0x8000 0000
0x8000 0000
0x8000 0000
0x0000 001F
0x0001 001F
0x0001 0010
0x0000 3727
0x0000 3727
0x0001 0037
0x0000 0020
0x0027 0300
0x0027 0300
0x0017 0300
0x0000 0020
0x0000 0014
0x0000 3737
0x8000 0000
0x8005 1F17
0x8000 0000
Rev. 0 | Page 16 of 20 |
April 2008
Con. List
Length
0x0E
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0002
0x0000 0001
0x0000 0001
0x0000 0002
0x0000 0002
0x0000 0006
0x0000 0006
0x0000 0002
0x0000 0002
0x0000 0000
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0000
0x0000 0000
0x0000 0001
0x0000 0000
0x0000 0002
0x0000 0000
0x0000 0001
0x0000 0001
0x0000 000A
0x0000 0002
0x0000 0001
0x0000 0007
0x0000 0001
0x0000 0002
0x0000 0002
0x0000 0002
0x0000 0001
0x0000 0003
Output Amp
Power States Capabilities
0x0F
0x12
0x0000 0009 0x0005 2727
0x0000 0009 0x0005 2727
0x0000 0009 0x0005 2727
0x0000 0009
0x0000 0009
0x8005 3627
0x8005 3627
0x800B 0F0F
0x8000 0000
0x0000 0009 0x8000 0000
0x0000 0009 0x8005 1F1F
0x0000 0009 0x8000 0000
0x0000 0009
0x8005 2727
0x8000 0000
0x8005 1F1F
0x0027 0300
AD1984A
CONNECTION LIST
Table 10. Connection List
Node
ID
0x02
0x03
0x04
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
1
Connections
[0–3]
[4–7]
[8–11]
0
1
2
3
4
5
6
7
NID
R1 NID
R NID
R NID
R NID
R NID
R NID
R NID R NID
0x0000 2122
0x0000 000C
0x0000 000D
0x0000 2104
0x0000 210F
0x2016 1514 0x0000 1725
0x2016 1514 0x0000 1725
0x0000 0403
0x0000 0403
0x22
0x0C
0x0D
0x04
0x0F
0x14
0x14
0x03
0x03
0x0000 0007
0x0000 000A
0x0000 001F
0x07
0x0A
0x1F
0x0000 000B
0x0B
0x0000 2120
0x20
0x0000 0002
0x0000 0024
0x118F 0A07 0x1C1A 1996 0x0000 A61E
0x0000 210E
0x0000 001E
0x1A16 1514 0x004 0325
0x0000 0020
0x0000 0403
0x0000 0403
0x0000 2123
0x0000 001C
0x001C 1514
0x02
0x24
0x07
0x0E
0x1E
0x14
0x20
0x03
0x03
0x23
0x1C
0x14
8
9
R NID
0x21
0x21
0x21
0x15
0x15
0x04
0x04
0x16
0x16
0x20
0x20
0x25
0x25
0x17
0x17
0x0A 1 0x0F
0x21
0x11 1 0x16
0x19
0x1A
0x15
0x1A
0x03
0x04
0x21
0x16
0x25
0x1C
0x1E 1 0x26
0x04
0x04
0x21
0x15
0x1C
R = the MS bit of any node ID indicates a 2-tuple NID pair delineating a continuous range of nodes. If the MS bit is set (=1), that list entry forms a range of entries from the
previous NID to the current NID. For additional information, see chapter 7.1.2, “Node Addressing” in the High Definition Audio Specification.
Rev. 0 |
Page 17 of 20 |
April 2008
AD1984A
DEFAULT CONFIGURATION BYTES
Table 11. Default Configuration Bytes
31:30
29:28
27:24
23:20
Location
Node ID
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x1A
0x1B
0x1C
Name
Port A (Headphone)
Port D (Line Out)
Mono Out
Port B (Mic In)
Port C (Line In)
Port F (Aux In/Out)
Dig Mic Pin
Analog PCBeep
S/PDIF Out-1
Port E (Dock I/O)
Value
0x0321 40F0
0x2121 4010
0x9017 01F0
0x03A1 90F0
0xB7A7 0121
0x9933 012E
0x97A6 01F0
0x90F3 01F0
0x0145 10F0
0x21A1 9020
Connectivity
Jack
Jack
Fixed
Jack
Fixed
Fixed
None
Fixed
Jack
Jack
Chassis
External
Separate
Internal
External
Other
Internal
Internal
Internal
External
Separate
Position
Left
Rear
N/A
Left
Special 1
Special 3
Special 1
N/A
Rear
Rear
Def. Device
HP Out
HP Out
Speaker
Mic In
Mic In
CD
Mic In
other
SPDIF Out
Mic In
Table 11. Default Configuration Bytes (Continued)
Node ID
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x1A
0x1B
0x1C
Name
Port A (Headphone)
Port D (Line Out)
Mono Out
Port B (Mic In)
Port C (Line In)
Port F (Aux In/Out)
Dig Mic Pin
Analog PCBeep
S/PDIF Out-1
Port E (Dock I/O)
Value
0x0321 40F0
0x2121 4010
0x9017 01F0
0x03A1 90F0
0xB7A7 0121
0x9933 012E
0x97A6 01F0
0x90F3 01F0
0x0145 10F0
0x21A1 9020
19:16
15:12
8
7:4
3:0
Conn Type
1/8” Jack
1/8” Jack
Other Analog
1/8” Jack
Other Analog
ATAPI
Other Digital
ATAPI
Optical
1/8” Jack
Color
Green
Green
Unknown
Pink
Unknown
Unknown
Unknown
Unknown
Black
Pink
JD OVRD
0
0
1
0
1
1
1
1
0
0
Def Assn.
0xF
0x1
0xF
0xF
0x2
0x2
0xF
0xF
0xF
0x2
Seq.
0x0
0x0
0x0
0x0
0x1
0xE
0x0
0x0
0x0
0x0
Rev. 0 | Page 18 of 20 |
April 2008
AD1984A
OUTLINE DIMENSIONS
7.00
BSC SQ
0.60 MAX
0.60 MAX
37
36
PIN 1
INDICATOR
TOP
VIEW
1
5.25
5.10 SQ
4.95
(BOTTOM VIEW)
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
12° MAX
PIN 1
INDICATOR
48
EXPOSED
PAD
6.75
BSC SQ
0.50
0.40
0.30
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.50 BSC
SEATING
PLANE
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 6. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm x 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD1984AJCPZ1
AD1984AJCPZ-RL1
1
Temperature Range
0°C to 70°C
0°C to 70°C
Package Description
48-Lead LFCSP_VQ
48-Lead LFCSP_VQ, 13” Tape and Reel
Z = RoHS Compliant Part.
Rev. 0 |
Page 19 of 20 |
April 2008
Package Option
CP-48-1
CP-48-1
AD1984A
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07399-0-4/08(0)
Rev. 0 | Page 20 of 20 |
April 2008