Revised September 2000 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse. Asynchronous input: LOW input to SD sets Q to HIGH level Set is independent of clock Ordering Code: Order Number Package Number Package Description 74F113SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F113SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F113PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009473 www.fairchildsemi.com 74F113 Dual JK Negative Edge-Triggered Flip-Flop April 1988 74F113 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL Description HIGH/LOW Output IOH/IOL J1, J2, K1, K2 Data Inputs 1.0/1.0 20 µA/−0.6 mA CP1, CP2 Clock Pulse Inputs (Active Falling Edge) 1.0/4.0 20 µA/−2.4 mA SD1, SD2 Direct Set Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA Q1, Q2, Q1, Q2 Outputs 50/33.3 −1 mA/20 mA Truth Table Inputs Outputs SD CP J K Q Q L X X X H L h h Q0 Q0 l h L H h l H L l l Q0 Q0 H H H H H (h) = HIGH Voltage Level L (l) = LOW Voltage level ] = HIGH-to-LOW Clock Transition X = Immaterial Q0 (Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output prior to the HIGH-to-LOW clock transition. Logic Diagram (One Half Shown) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min V Min 0.5 V Min IOL = 20 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 µA 0.0 mA Max VIN = 0.5V (CPn) µA Max VOUT = 2.7V Output HIGH Voltage VOL Output LOW 10% VCC 2.5 5% VCC 2.7 V Conditions Input HIGH Voltage VOH 2.0 Units VIH 10% VCC Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA Voltage IIH Input HIGH Current IBVI Input HIGH Current Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage Test IOD 4.75 Output Leakage 3.75 Circuit Current IIL −0.6 Input LOW Current −2.4 Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current ICC Power Supply Current 50 −60 12 3 VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (Jn, Kn) −3.0 IOZH IID = 1.9 µA All Other Pins Grounded VIN = 0.5V (SDn) −50 µA Max VOUT = 0.5V −150 mA Max VOUT = 0V 19 mA Max www.fairchildsemi.com 74F113 Absolute Maximum Ratings(Note 1) 74F113 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 85 105 Max Min tPLH Propagation Delay 2.0 4.0 Max tPHL CPn to Qn or Qn 2.0 4.0 6.0 2.0 7.0 tPLH Propagation Delay 2.0 4.5 6.5 2.0 7.5 tPHL SDn to Qn or Qn 2.0 4.5 6.5 2.0 7.5 80 6.0 2.0 Units MHz 7.0 ns ns AC Operating Requirements TA = +25°C Symbol VCC = +5.0V Parameter Min Max TA = 0°C to +70°C VCC = +5.0V Min Units Max tS(H) Setup Time, HIGH or LOW 4.0 5.0 tS(L) Jn or Kn to CPn 3.0 3.5 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) Jn or Kn to CPn 0 0 tW(H) CPn Pulse Width 4.5 5.0 tW(L) HIGH or LOW 4.5 5.0 tW(L) SDn Pulse Width, LOW 4.5 5.0 ns tREC SDn to CPn 4.0 5.0 ns Recovery Time www.fairchildsemi.com 4 ns ns 74F113 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 5 www.fairchildsemi.com 74F113 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 74F113 Dual JK Negative Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com