Revised September 2000 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs. LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Order Number Package Number Package Description 74F109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009471 www.fairchildsemi.com 74F109 Dual JK Positive Edge-Triggered Flip-Flop April 1988 74F109 Truth Table Inputs Outputs SD CD CP J K Q L H X X X H L H L X X X L H X X H H I I L h I L L H H H H H H H H H H X L Q H Toggle I h Q h h H Q L X X Q Q H (h) = HIGH Voltage Level L (l) = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial Q0 (Q0) = Before LOW-to-HIGH Transition of Clock Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition. Unit Loading/Fan Out U.L. Pin Names Description Input IIH/IIL HIGH/LOW Output IOH/IOL 20 µA/−0.6 mA J1, J2, K1, K2 Data Inputs 1.0/1.0 CP1, CP2 Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA CD1, CD2 Direct Clear Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA SD1, SD2 Direct Set Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA 50/33.3 −1 mA/20 mA Q1, Q2, Q1, Q2 Outputs Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150 °C Ambient Temperature under Bias −55°C to +125 °C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +175 °C Supply Voltage 0°C to +70°C +4.5V to +5.5V VCC Pin Potential to −0.5V to +7.0V Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with Vcc = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VCC Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH Voltage V Min 0.5 V Min IOL = 20 mA 10% VCC 2.5 5% VCC 2.7 V Conditions VIH 10% VCC Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA VOL Output LOW Voltage IIH Input HIGH Current 5.0 µA Max VIN = 2.7V IBVI Input HIGH Current Breakdown Test 7.0 µA Max VIN = 7.0V ICEX Output HIGH Leakage Current 50 µA Max VOUT = VCC VID Input Leakage Test V 0.0 4.75 IID = 1.9 µA All Other Pins Grounded IOD Output Leakage IIL Input LOW Current IOS Output Short-Circuit Current ICC Power Supply Current −60 11.7 3 VIOD = 150 mV µA 0.0 −0.6 mA Max VIN = 0.5V (Jn, Kn) −1.8 mA Max VIN = 0.5V (CDn, SDn) −150 mA Max VOUT = 0V 17.0 mA Max CP = 0V 3.75 Circuit Current All Other Pins Grounded www.fairchildsemi.com 74F109 Absolute Maximum Ratings(Note 1) 74F109 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Max Min Units Min Typ fMAX Maximum Clock Frequency 100 125 Max tPLH Propagation Delay 3.8 5.3 7.0 3.8 8.0 tPHL CPn to Qn or Qn 4.4 6.2 8.0 4.4 9.2 tPLH Propagation Delay 3.2 5.2 7.0 3.2 8.0 ns tPHL CDn or SDn to 3.5 7.0 9.0 3.5 10.5 ns 90 MHz ns Qn or Qn AC Operating Requirements Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V Min tS(H) Max Min Setup Time, HIGH or LOW 3.0 3.0 tS(L) Jn or Kn to CPn 3.0 3.0 tH(H) Hold Time, HIGH or LOW 1.0 1.0 Units Max ns tH(L) Jn or Kn to CPn 1.0 1.0 tW(H) CPn Pulse Width 4.0 4.0 tW(L) HIGH or LOW 5.0 5.0 tW(L) CDn or SDn Pulse Width LOW 4.0 4.0 ns tREC Recovery Time 2.0 2.0 ns ns CDn or SDn to CP www.fairchildsemi.com 4 74F109 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com 74F109 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 6 74F109 Dual JK Positive Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com