Revised August 1999 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of Clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Order Number Package Number Package Description 74F114SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F114PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009474 www.fairchildsemi.com 74F114 Dual JK Negative Edge-Triggered Flip-Flop April 1988 74F114 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Description J1, J2, K1, K2 Data Inputs 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Falling Edge) 1.0/8.0 20 µA/−4.8 mA CD Direct Clear Input (Active LOW) 1.0/10.0 20 µA/−6.0 mA SD1, SD2 Direct Set Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA Q1, Q2, Q1, Q2 Outputs 50/33.3 −1 mA/20 mA Truth Table Inputs Outputs SD CD CP J K Q Q L H X X X H L H L X X X L H L L X X X H H h h Q0 Q0 l h L H h l H L l l Q0 Q0 H H H H H H H H H (h) = HIGH Voltage Level L (h) = LOW Voltage Level X = Immaterial = HIGH-to-LOW Clock Transition Q0 (Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram (one half shown) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA VOH Output HIGH V Min IOH = −1 mA 0.5 V Min IOL = 20 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 µA 0.0 Voltage Output LOW 10% VCC 2.5 5% VCC 2.7 V Conditions Input HIGH Voltage VOL 2.0 Units VIH Recognized as a HIGH Signal Recognized as a LOW Signal IOH = −1 mA 10% VCC Voltage IIH Input HIGH Current IBVI Input HIGH Current Breakdown Test ICEX Output High Leakage Current VID Input Leakage Test IOD 4.75 Output Leakage 3.75 Circuit Current IIL −0.6 Input LOW Current VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (Jn, Kn) −3.0 VIN = 0.5V (SDn) mA Max −150 mA Max VOUT = 0V −4.8 −6.0 −60 IID = 1.9 µA All Other Pins Grounded VIN = 0.5V (CP) VIN = 0.5V (CDn) IOS Output Short-Circuit Current ICCH Power Supply Current 12.0 19.0 mA Max VO = HIGH ICCL Power Supply Current 12.0 19.0 mA Max VO = LOW 3 www.fairchildsemi.com 74F114 Absolute Maximum Ratings(Note 1) 74F114 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 75 95 Max Min tPLH Propagation Delay 3.0 5.0 6.5 3.0 7.5 tPHL CP to Qn or Qn 3.0 5.5 7.5 3.0 8.5 tPLH Propagation Delay 3.0 4.5 6.5 3.0 7.5 tPHL CDn or SDn to Qn or Qn 3.0 4.5 6.5 3.0 7.5 Units Max 70 MHz ns ns AC Operating Requirements TA = +25°C Symbol VCC = +5.0V Parameter Min Max TA = 0°C to +70°C VCC = +5.0V Min Units Max tS(H) Setup Time, HIGH or LOW 4.0 5.0 tS(L) Jn or Kn to CP 3.0 3.5 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) Jn or Kn to CP 0 0 tW(H) CP Pulse Width 4.5 5.0 tW(L) HIGH or LOW 4.5 5.0 CDn or SDn Pulse Width, 4.5 5.0 ns 4.0 5.0 ns tW(L) ns ns LOW tREC Recovery Time SDn, CDn, to CP www.fairchildsemi.com 4 74F114 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 5 www.fairchildsemi.com 74F114 Dual JK Negative Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6