78P2252 STM-1/OC-3 Transceiver JUNE 2002 DESCRIPTION FEATURES The 78P2252 is a transceiver IC designed for 155.52Mbit/s (OC-3 or STM-1) transmission. It is used at the interface to a fiber optic module. Interface to digital framer circuits is accomplished via a serial PECL or parallel CMOS interface. • Compliant with ITU-T G.958 jitter tolerance, Telcordia TR-NWT-00253, ANSI T1.105.031994, and ANSI T1.105.05-1994 • Integrated Clock Recovery Unit (CRU) • Serial PECL Interface • Four and Eight bit Parallel CMOS Interfaces • PECL Interfaces for connection to Fiber Optic Modules for SONET OC3 applications • Integrated Clock Multiplier PLL • Advanced BiCMOS Process • Available in 64TQFP Package The 78P2252 is built in a BiCMOS technology allowing for high performance with low power operation. The device automatically adjusts for operations with either a 3.3V or 5V power supply and is packaged in a 64-pin TQFP. CKIN Crystal Oscillator 8BIT/$BIT PAR/SER HUB/HOST XTAL2 XTAL1 BLOCK DIAGRAM Clock Generator TXCK TXCKP,N RLBACK TXDTP,N TXDT[7:0] ECLOUTP ECLOUTN RXDTP,N RXDT[7:0] Clock Recovery ECLINP ECLINN RXCKP,N RXCK LLBACK LF RFO Bias 78P2252 STM-1/OC-3 Transceiver FUNCTIONAL DESCRIPTION RECEIVER OPERATION The 78P2252 contains all the necessary transmit and receive circuitry for connection between 155.52Mbit/s signals and digital Framer/Deframer ICs. The receiver accepts NRZ coded, serial data at 155.52Mbit/ from the fiber optic module via the ECL inputs, ECLINP and ECLINN. A clock signal is recovered using a low jitter PLL circuit. DIGITAL INTERFACE In serial mode, the received data is output on the RXDTP and RXDTN pins and the recovered clock is output on the RXCKP and RXCKN pins at the line rate frequency. The digital interface of the 78P2252 can operate as a Serial PECL, 4-bit Parallel CMOS, or 8-bit Parallel CMOS interface. These modes are controlled by the PAR/SER and 8BIT/$BIT pins as shown in the following table. Mode PAR/ SER 8BIT/ $BIT Data pins Clock pins Clock Frequency (MHz) Serial 0 X TXDTP,N RXDTP,N TXCKP,N RXCKP,N 155.52 4-bit Parallel 1 0 TXDT[3:0] RXDT[3:0] TXCK RXCK 38.88 8-bit Parallel 1 1 TXDT[7:0] RXDT[7:0] TXCK RXCK 19.44 In parallel mode, the received data is converted to either eight bit or four bit parallel formats, determined by the state of the 8BIT/$BIT pin. The first bit received will arrive on the most significant output pin, RXDT[7] in eight bit mode and RXDT[3] in four bit mode. In parallel mode, the recovered clock in output on the RXCK pin at either one-eighth or one-fourth the line rate frequency, depending on the state of the 8BIT/$BIT pin. TRANSMITTER OPERATION The transmitter accepts serial or parallel data and generates an NRZ coded PECL signal for transmission to a fiber optic module. When set to serial mode via PAR/SER pin, serial data is input from the digital Framer/Deframer IC to the 78P2252 on the TXDTP and TXDTN pins at PECL levels. The data is clocked in with a line rate frequency clock generated by the 78P2252 on the TXCKP and TXCKN pins. When set to parallel mode, parallel data is input from the digital Framer/Deframer IC to the 78P2252 on the TXDT[7:0] pins. Eight bits or four bits of data are used depending the setting of the 8BIT/$BIT pin. o In eight bit parallel mode, data is read on pins TXDT[7:0]. o In four bit parallel mode, data is read on pins TXDT[3:0]. The parallel input data is clocked in with the generated clock output TXCK. The TXCK automatically adjusts to either one-eighth or onefourth the standard line rate frequency, depending on the state of the 8BIT/$BIT pin. 2 78P2252 STM-1/OC-3 Transceiver The HUB/HOST pin selects the source of the reference signal used for the internal transmit clock generator. When in Remote (Digital) Loopback mode (RLBACK logic high), the received data is internally routed onto the transmitter inputs. Note that any input data on the TXDTP,N pins or TXDT[7:0] pins is ignored in remote loopback mode. In Hub mode (HUB/HOST logic high), the transmit clock reference is derived from either a crystal oscillator applied to the XTAL1 and XTAL2 pins or a reference clock input applied at the CKIN pin. The reference frequency should be one-eighth the line rate frequency at 19.44MHz and should be applied in one of the following configurations. XTAL2 XTAL1 Crystal Oscillator CKIN 8BIT/$BIT Remote and Local Loopback modes in the 78P2252 are controlled by the RLBACK and LLBACK pins respectively. PAR/SER REFERENCE CLOCK HUB/HOST LOOPBACK OPERATION Hub Mode Configurations Remote (Digital) Loopback Clock Generator TXCK TXCKP,N RLBACK TXDTP,N TXDT[7:0] XTAL1 XTAL1 XTAL2 XTAL2 CKIN CKIN ECLOUTP ECLOUTN Clock Recovery RXDTP,N RXDT[7:0] ECLINP ECLINN RXCKP,N RXCK LLBACK LF RFO Bias Using crystal CKIN Crystal Oscillator LLBACK RLBACK Local (Analog) Loopback Clock Generator -- or -- TXCK TXCKP,N HUB/HOST HOST Reference Clock 0 0 1 CKIN or XTAL1,2 1 0 1 CKIN or XTAL1,2 X 1 1 Recovered Rx Clock X X 0 Recovered Rx Clock RLBACK TXDTP,N TXDT[7:0] ECLOUTP ECLOUTN Clock Recovery RXDTP,N RXDT[7:0] ECLINP ECLINN RXCKP,N RXCK LLBACK LF Bias RFO Using external clock In Host mode (HUB/HOST logic low), the transmit clock reference is derived from the recovered receive clock. Note that the recovered receive clock is also used as the reference clock when Remote Loopback is enabled. 8BIT/$BIT PAR/SER HUB/HOST XTAL1 XTAL2 When in Local (Analog) Loopback mode (LLBACK logic high), the transmit output signals are internally routed to the receiver inputs. Note that Local Loopback mode is disabled when HUB/HOST is low or RLBACK is high. 3 78P2252 STM-1/OC-3 Transceiver PIN DESCRIPTION LEGEND TYPE DESCRIPTION TYPE A Analog Pin PI PECL Digital Input CI CMOS Digital Input PO PECL Digital Output CO CMOS Digital Output S DESCRIPTION Supply Pin TRANSMIT PINS NAME PIN TXDTP 19 TXDTN 20 TXCKP 22 TXCKN 23 TXDT[7:0] TYPE DESCRIPTION PI Transmit Data Inputs - Serial Mode. PO Transmit Clock Output - Serial Mode. 11-18 CI TXCK 10 CO ECLOUTP 56 ECLOUTN 55 PO Transmit Data Inputs – Parallel Mode. TXDT[7:4] are ignored in 4 bit mode. Reference Clock Output – Serial mode. Transmit Clock Output – Parallel Mode. Transmit Outputs. RECEIVE PINS NAME PIN TYPE ECLINP ECLINN 52 51 PI RXCKP 25 RXCKN 26 RXCK 38 RXDTP 27 RXDTN 28 RXDT[7:0] 30-37 DESCRIPTION Receiver inputs. PO Recovered Receive Clock – Serial Mode. CO Recovered Receive Clock – Parallel Mode. PO Receive data – Serial Mode. CO Receive data – Parallel Mode. In 4 bit mode RXDT[3:0] are used and RXDT[7:4] are pulled low. REFERENCE CLOCK PINS NAME PIN XTAL1 5 XTAL2 6 CKIN 9 TYPE A CI DESCRIPTION Crystal Pins. These pins should be left floating if using reference clock input CKIN. Reference clock input. This pin should be grounded if using the crystal oscillator inputs. 4 78P2252 STM-1/OC-3 Transceiver PIN DESCRIPTION (continued) CONTROL AND STATUS PINS NAME PIN TYPE RLBACK 41 CI DESCRIPTION Remote (Digital) Loopback Enable. When logic high, loops receiver output data to transmitter inputs. Local (Analog) Loopback Enable. LLBACK 42 CI When logic high, loops transmitter output to receiver input. Note: Disabled when HUB/HOST is low or RLBACK is high. HUB/HOST 2 CI 8BIT/$BIT 63 CI In HUB mode (input high) the transmit reference clock is derived from the CKIN pin or the crystal oscillator. In HOST mode (input low) the transmit reference clock is derived from the recovered receive clock. When in parallel mode, logic high selects 8-bit mode and logic low selects 4-bit mode. Ignored in serial mode. PAR/SER 62 CI Selects parallel mode when high, serial mode when low. NAME PIN TYPE RFO 46 A External reference resistor. section for more info. LF 44 A PLL loop filter capacitor. See APPLICATION INFORMATION section for more info. ANALOG PINS DESCRIPTION See APPLICATION INFORMATION POWER SUPPLY PINS It is recommended that all VCC pins be connected to a single power supply plane and all GND pins be connected to a single ground plane. NAME PIN TYPE DESCRIPTION VCC 3, 8, 24, 40, 43, 53, 54, 57 S Power Supply. GND 1, 4, 7, 21, 29, 39, 45, 47, 48, 50, 58, 59, 60, 61, 64 S Ground. 5 78P2252 STM-1/OC-3 Transceiver ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation beyond these limits may permanently damage the device. PARAMETER Supply Voltage Storage Temperature Pin Voltage Pin Current RATING 7 VDC -65 to 150° C -0.3 to (VCC+0.3) VDC ±100 mA RECOMMENDED OPERATING CONDITIONS Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges. PARAMETER RATING DC Voltage Supply, VCC 3.3 ± 0.3 VDC; 5 ± 0.5 VDC Ambient Operating Temperature -40 to 85°C DC CHARACTERISTICS: PARAMETER SYMBOL Supply Current (Parallel Mode) Icc Supply Current (Serial Mode) Icc CONDITIONS NOM MAX Vcc = 3.3V 140 165 Vcc = 5.0V 150 175 Vcc = 3.3V 210 245 Vcc = 5.0V 280 330 6 MIN UNIT mA mA 78P2252 STM-1/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) DIGITAL INPUT CHARACTERISTICS Pins of type CI PARAMETER SYMBOL CONDITIONS MIN NOM Input Voltage Low Vil Input Voltage High Vih Vcc/2 + 0.9 Iil, Iih -10 Input Current Input Capacitance MAX UNIT Vcc/2 - 0.9 V V 10 Cin µA 10 pF Pins of type PI PARAMETER SYMBOL CONDITIONS MIN Input Voltage Low Vil Relative to Vcc Input Voltage High Vih Relative to Vcc -1.1 CONDITIONS MIN NOM MAX UNIT -1.5 V V DIGITAL OUTPUT CHARACTERISTICS Pins of type CO PARAMETER SYMBOL Output Voltage Low Vol Output Voltage High Voh Transition Time Below Vcc Tt NOM MAX UNIT 0.6 0.7 V 0.6 0.7 V 3.5 ns Pins of type PO PARAMETER Output Voltage Low SYMBOL Vol CONDITIONS Vcc Reference biased at Vcc -1.5V with 50 ohm MIN -1.7 NOM -1.4 MAX -1.3 UNIT V Output Voltage High Voh Vcc Reference biased at Vcc -1.5V with 50 ohm -1.1 -0.9 -0.7 V Rise Time Tr 1 3 ns Fall Time Tf 1 3 ns 7 78P2252 STM-1/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) DIGITAL TIMING CHARACTERISTICS Transmit Interface – Serial Mode TXCKP TXCKN TXDTP TXDTN TSUs PARAMETER SYMBOL THs CONDITIONS MIN NOM MAX UNIT Transmit Setup Time TSUs Serial Mode 1.5 ns Transmit Hold Time THs Serial Mode 1.5 ns TXCKP,N Duty Cycle 40 60 % MAX UNIT Transmit Interface – 8-bit Parallel Mode TXCK TXDT[7:0] TSUp PARAMETER THp SYMBOL CONDITIONS MIN Transmit Setup Time TSUp Parallel Mode 3.5 ns Transmit Hold Time THp Parallel Mode 2.5 ns TXCK Duty Cycle 40 8 NOM 60 % 78P2252 STM-1/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) DIGITAL TIMING CHARACTERISTICS Receive Interface – Serial Mode RXCKP RXCKN RXDTP RXDTN PARAMETER Receive Propagation Delay SYMBOL TPROPs TPROPs CONDITIONS MIN Serial Mode RXCKP,N Duty Cycle NOM MAX UNIT 2.4 3.0 ns 60 % NOM MAX UNIT 4.0 6.0 ns 60 % 40 Receive Interface – 8-bit Parallel Mode RXCK RXDT[7:0] TPROPp PARAMETER Receive Propagation Delay SYMBOL CONDITIONS TPROPps Parallel Mode RXCKP,N Duty Cycle MIN 40 9 78P2252 STM-1/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) REFERENCE CLOCK INTERFACE CKIN TXCKP TXCKN PARAMETER CKIN to TXCKP/N Delay SYMBOL TPROPs TPROPs CONDITIONS MIN NOM MAX UNIT Serial Mode 3.1 4.6 5.6 ns CONDITIONS MIN NOM MAX UNIT Parallel 8 bit Mode 1.6 3.7 5.7 ns CKIN TXCK T PARAMETER CKIN to closes phase of TXCK Delay SYMBOL TPROPp PROPp 10 78P2252 STM-1/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER OUTPUT JITTER The transmit jitter specification ensures compliance with ITU-T G.958 and ANSI T1.105.03-1994 for STM-1 and OC-3 rates. The corner frequency of the transmit PLL is nominally 3.0 MHz. Jitter Detector Measured Jitter Amplitude 20dB/decade Transmitter Output 500 Hz PARAMETER CONDITION Transmitter Output Jitter 200 Hz to 3.5 MHz 1.3 MHz MIN 11 NOM MAX UNIT 0.075 UIpp 78P2252 STM-1/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) RECEIVER JITTER TOLERANCE OC-3 jitter tolerance specifications are in ANSI T1.105.05-1994 and Telcordia TR-NWT-000253, Issue 2, Dec. 1991. STM-1 specifications are in ITU-T G.825. They are identical except that STM-1 specifies both jitter and wander. The STM-1 specification is the tightest and covers the largest frequency range. 10000 1000 100 STM-1 E4 10 1 0.1 0.01 1.E-06 1.E-05 1.E-04 1.E-03 PARAMETER Receiver Jitter Tolerance Note 1: Not tested in production 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 CONDITION MIN 12µHz to 178µHz 2800 1.6mHz to 15.6mHz 311 125mHz to 19.3 Hz 39 500Hz to 6.5kHz 1.5 65kHz to 3.5MHz 0.15 12 1.E+06 1.E+07 NOM MAX UNIT UI 78P2252 STM-1/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) RECEIVER JITTER TRANSFER FUNCTION The receiver clock recovery loop filter characteristics such that the receiver has the following transfer function. The corner frequency of the PLL is approximately 100 kHz. These specifications are not tested in production. 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 1.00E+03 1.00E+04 1.00E+05 PARAMETER CONDITION Receiver Jitter transfer function below 100 kHz 1.00E+06 MIN Jitter transfer function roll-off NOM 20 Note 1: Not tested in production 13 1.00E+07 MAX UNIT 0.1 dB dB per decade 78P2252 STM-1/OC-3 Transceiver APPLICATION INFORMATION EXTERNAL COMPONENTS: COMPONENT PIN(S) VALUE UNITS TOLERANCE Reference Resistor RFO 31.6 kΩ 1% Filter Capacitor LF1 470 nF 5% VALUE UNITS TOLERANCE 19.44 MHz +/- 20ppm 27 pF CRYSTAL SPECIFICATIONS: COMPONENT Center Frequency Load Capacitor – XTAL1 to ground; XTAL2 to ground Please check datasheet of crystal manufacturer for optimal load capacitor values. SCHEMATICS The latest typical application schematics are available in the form of Application Notes and/or Demo Board Manuals. Please contact TDK Semiconductor for more information. PECL INTERFACE COMPONENTS: COMPONENT Output Bias Resistor, RBIAS VALUE UNITS TOLERANCE VCC = 5v 250 Ω 5% VCC = 3.3V 140 Ω 5% 100 Ω 5% Termination Resistor, RTERM When the PECL signals travel one inch or less, lower power operation can be achieved by increasing RBIAS and eliminating RTERM. RTERM RBIAS RBIAS FIGURE 1. PECL INTERFACE 14 78P2252 STM-1/OC-3 Transceiver MECHANICAL SPECIFICATIONS 64-TQFP (JEDEC LQFP) Mechanical Specification 15 78P2252 STM-1/OC-3 Transceiver PACKAGE PIN DESIGNATIONS GND ECLINN ECLINP VCC VCC ECLOUTN ECLOUTP VCC GND GND GND GND PAR/SER 8BIT/$BIT GND GND CAUTION: Use handling procedures necessary for a static sensitive component. (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GND 1 48 GND HUB/HOST 2 47 GND VCC 3 46 RFO GND 4 45 GND XTAL1 5 44 LF XTAL2 6 43 VCC GND 7 42 LLBACK VCC 8 41 RLBACK CKIN 9 40 VCC TXCK 10 39 GND TXDT7 11 38 RXCK TXDT6 12 37 RXDT0 TXDT5 13 36 RXDT1 TXDT4 14 35 RXDT2 TXDT3 15 34 RXDT3 TXDT2 16 33 RXDT4 RXDT5 RXTD6 RXDT7 GND RXTDN RXTDP RXCKN RXCKP VCC TXCKN TXCKP GND TXDTN TXDTP TXDT0 TXDT1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64-Pin TQFP (JEDEC LQFP) 78P2252-IGT ORDERING INFORMATION PART DESCRIPTION ORDER NUMBER PACKAGING MARK 78P2252 64- Pin Thin Quad Flatpack 78P2252-IGT 78P2252-IGT No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that you are referencing the most current data sheet before placing orders. To do so, see our web site at http://www.tsc.tdk.com or contact your local TDK Semiconductor representative. TDK Semiconductor Corporation, 2642 Michelle Drive, Tustin, CA 92780-7019, (714) 508-8800, FAX: (714) 508-8877 2002 TDK Semiconductor Corporation 6/13/02- Rev. H 16