78P2253 E4/STM-1/STS-3/OC-3 Transceiver Advanced Information November 2000 DESCRIPTION FEATURES The 78P2253 is a transceiver IC designed for 139.264Mbit/s (E4) or 155.52Mbit/s (OC-3, STS-3 or STM-1) transmission. It is used at the interface to a 75Ω coaxial cable using CMI coding or a fiber optic module. Interface to digital framer circuits is accomplished via a serial PECL or parallel CMOS interface. • 139.264Mbit/s or 155.52Mbit/s interface for CMI coded transmission using 75Ω coaxial cable • Compliant with ITU-T G.703, G.823 jitter tolerance, Telcordia TR-NWT-00253 • Integrated Clock Recovery Unit (CRU) • Serial PECL Interface • Four and Eight bit Parallel CMOS Interfaces • PECL Interfaces for connection to Fiber Optic Modules for SONET OC3 applications • Adaptive Equalization • Integrated Clock Multiplier PLL • Advanced BiCMOS Process The transmitter includes a PLL to multiply the reference clock to the transmission frequency. The receiver provides adaptive equalization for accurate clock and data recovery. The 78P2253 is built in a BiCMOS technology for high performance and low power operation. It operates with a 3.3V or 5V power supply and is packaged in a 64-pin TQFP. CKIN Crystal Oscillator CM I/ECL 8BIT/$BIT HUB/HOST PAR/SER E4/SONET XTAL2 XTAL1 BLOCK DIAGRAM Clock Generator CMIOUTP CMIOUTN Binary to CMI TXCK ECLOUTP ECLOUTN TXCKP,N RLBACK TXDTP,N TXDT[7:0] RXDTP,N RXDT[7:0] ECLINP ECLINN CMI to Binary Clock Recovery CMIINP CMIINN Adaptive Equalizer RXCKP,N RXCK LLBACK LF RFO LOS Signal Detector Bias 78P2253 E4/STM-1/STS-3/OC-3 Transceiver FUNCTIONAL DESCRIPTION matching resistors. In CMI mode the transmitter shapes the transmit pulses to meet the appropriate template and the adaptive equalizer corrects the received signal for dispersive attenuation. The ECLOUTP and ECLOUTN pins are inoperative and should be left open. The 78P2253 contains all the necessary transmit and receive circuitry for connection between 139.264Mbit/s or 155.52Mbit/s signals and digital Framer/Deframer ICs. Operating Rate When the CMI/ECL pin is low the chip is in ECL mode and a fiber optics transceiver is used. The output data signal from the pins ECLOUTP and ECLOUTN have PECL levels. In this mode, the CMI pins are inoperative and should be left open. The CMI encoder and decoder are disabled. The 78P2253 has a variety of operating modes and rates. They are summarized in the tables below. More detailed descriptions can be found in the sections that follow. Standard E4/SONET CMI/ECL Rate (Mbit/s) Reference Frequency Active I/O TRANSMITTER OPERATION (MHz) OC-3 0 0 155.52 19.44 ECL 0 1 155.52 19.44 CMI 1 0 139.264 17.408 ECL 1 1 139.264 17.408 CMI The transmitter section generates an analog signal for transmission through a transformer onto the coaxial cable or fiber optic module. STM1 optic STS-3 STM-1 Coax E4 When the PAR/SER pin is low the chip is in serial mode. Serial data is input to the 78P2253 on the TXDTP and TXDTN pins at PECL levels. The data is timed with the clock generated by the 78P2253 on the TXCKP and TXCKN pins. In this mode the 8BIT/$BIT pin is ignored. The digital interface of the 78P2253 can be either Serial PECL, 4-bit Parallel CMOS or 8-bit Parallel CMOS. Mode PAR/SER 8BIT/BIT Data pins Clock pins Clock Frequency (MHz) Serial 0 X TXDTP,N TXCKP,N 155.52(Sonet) RXDTP,N RXCKP,N 139.264 (E4) 4-bit Parallel 1 0 TXDT[3:0] TXCK 38.88(Sonet) RXDT[3:0] RXCK 34.816(E4) 8-bit Parallel 1 TXDT[7:0] TXCK 19.44(Sonet) RXDT[7:0] RXCK 17.408(E4) 1 When the PAR/SER pin is high the chip is in parallel mode. Parallel data is in put to the 78P2253 on the TXDT[7:0] pins. The input data is timed with the clock output from TXCK. When 8BIT/$BIT is high all eight bits of TXDT[7:0] are used and the clock frequency at TXCK is one-eighth the standard frequency. When 8BIT/$BIT is low the lower four bits, TXCK[3:0] are used and TXCK is one-fourth the standard frequency. Transmit timing is derived from either the reference clock (the crystal oscillator or CKIN), or the recovered receive clock. LLBACK and RLBACK control the local and remote loopback modes respectively. LLBACK RLBACK HUB/HOST Transmit Clock derived from 0 0 1 Reference 1 0 1 Reference X 1 1 Receiver X X 0 Receiver The first bit output from the ECL/CMI interface is the most significant bit on the parallel interface, TXDT7 in eight bit mode, TXDT3 in four bit mode. The clock is generated by a phase-locked oscillator (PLO). The PLO is locked to a crystal oscillator operating at one-eighth of the standard clock frequency, 19.44MHz for OC-3, STS-3 and STM-1 and 17.408MHz for E4. This is shown in Figure 1a. An external clock signal at CKIN may also be substituted for a crystal as the reference frequency for the chip. In this mode, XTL1 and XTL2 must be configured as shown in Figure 1b. Note that the chip can be in either ECL or CMI mode when using either an external clock or a crystal for the reference. In serial mode the reference clock is output from TXCK. In parallel mode, the parallel transmit clock is output from TXCK. Medium Choices The CMI/ECL pin selects one of two media for transmission. When the CMI/ECL pin is high, the chip is in CMI mode and a 75Ω coaxial cable is used as the transmission medium. In this mode, the CMIOUTP and CMIOUTN pins are active. They connect the chip to the coaxial cable through a transformer and 2 78P2253 E4/STM-1/STS-3/OC-3 Transceiver TRANSMITTER OPERATION (continued) RECEIVER OPERATION XTAL2 The receiver accepts serial, CMI coded data, at 155.52Mbit/s or 139.264Mbit/s from either the CMI or the ECL inputs. In CMI mode, the inputs CMIINP and CMIINN receive the input signal from a coaxial cable that is transformer-coupled to the chip. The ECL pins should be left open. In ECL mode, the pins ECLINP and ECLINN receive the input signal. CKIN In CMI mode, the received signal is equalized for dispersive cable attenuation and decoded in the CMI to binary decoder. XTAL1 A clock signal is recovered using a low jitter PLL circuit. FIGURE 1A: USING CRYSTAL The data is converted to binary by the CMI to Binary decoder. In serial mode, the received data is output on the RXDTP and RXDTN pins and the recovered clock is output on the RXCKP and RXCKN pins. XTAL1 In parallel mode, the received data is converted to parallel, eight bits if 8BIT/$BIT is high and four if it is low. The first bit received will arrive on the most significant output pin, RXDT[7] in eight bit mode and RXDT3 in four bit mode. XTAL2 17.283 MHz (E4) 19.440 MHz (Sonet) CKIN The LOS pin goes high when the signal detector detects a loss-of-signal condition. LOOPBACK OPERATION FIGURE 1B: USING EXTERNAL CLOCK The 78P2253 is capable of performing signal loopback in two ways The RLBACK pin selects the remote loopback mode. In this mode, the received signal is “looped back” and sent out of transmitter in place of the transmit input signal. In ECL mode the data signal is converted to CMI code by the Binary to CMI encoded. The HUB/HOST input changes the reference signal for the clock generator. In the hub mode (HUB/HOST high), the transmit clock reference is derived from either the crystal oscillator or CKIN. In host mode (HUB/HOST low), the transmit clock reference is derived from the recovered receive clock. The LLBACK pin selects the local loop-back mode, and causes the receiver to use the transmitter output signal as its input. Local loopback is disabled when HUB/HOST is low or RLBACK is high. 3 78P2253 E4/STM-1/STS-3/OC-3 Transceiver PIN DESCRIPTION LEGEND TYPE DESCRIPTION A Analog Pin CI CMOS Digital Input CO CMOS Digital Output TYPE PI PO S DESCRIPTION PECL Digital Input PECL Digital Output Supply Pin TRANSMIT PINS NAME PIN TYPE TXDTP 19 PI Transmit Data Inputs - Serial Mode. TXDTN 20 TXCKP 22 PO Transmit Clock Output - Serial Mode. TXCKN 23 11-18 CI Transmit Data Inputs – Parallel Mode. TXDT[7:4] are ignored in 4 bit mode. 10 CO Reference Clock Output – Serial mode. TXDT[7:0] TXCK DESCRIPTION Transmit Clock Output – Parallel Mode. CMIOUTP 60 CMIOUTN 59 ECLOUTP 56 ECLOUTN 55 A Transmit Output in CMI mode. No signal is output in ECL mode. PO Transmit Outputs for ECL mode. No signal is output in CMI mode. RECEIVE PINS NAME PIN TYPE CMIINP 50 A CMIINN 49 DESCRIPTION Receive inputs in CMI mode. Transformer coupled from the coaxial cable. Ignored in ECL mode. ECLINP ECLINN 52 51 PI Receiver inputs in ECL mode. Ignored in CMI mode. RXCKP 25 PO Recovered Receive Clock – Serial Mode. RXCKN 26 RXCK 38 CO Recovered Receive Clock – Parallel Mode. RXDTP 27 PO Receive data – Serial Mode. RXDTN 28 CO Receive data – Parallel Mode. In 4 bit mode RXDT[3:0] are used and RXDT[7:4] are pulled low. RXDT[7:0] 30-37 4 78P2253 E4/STM-1/STS-3/OC-3 Transceiver PIN DESCRIPTION (continued) REFERENCE CLOCK PINS NAME PIN TYPE DESCRIPTION XTAL1 5 A Crystal Pins. Connect as in Figure 1a. XTAL2 6 CKIN 9 CI Reference clock input. The crystal oscillator connections should be left open. CONTROL AND STATUS PINS NAME PIN TYPE RLBACK 41 CI Loopback receiver output to transmitter input. LLBACK 42 CI Loopback transmitter output to receiver input. Disabled when HUB/HOST is low or RLBACK is high. HUB/HOST 2 CI In HUB mode (input high) the transmit reference clock is derived from the CKIN pin or the crystal oscillator. In HOST mode (input low) the transmit reference clock is derived from the recovered receive clock. CMI/ECL 1 CI Selects CMI (input high) or ECL (input low) modes. E4/SONET 64 CI When high, E4 (139.264 Mbit/s) operation is selected. When low, STM-1/STS-3/OC-3 (155.52Mbit/s) operation is selected. CI Selects 8 bit parallel data when high and 4 bit parallel mode when low. In serial mode this pin is ignored. 39 CO High during a loss-of-signal condition. PIN TYPE RFO 46 A External reference resistor. LF 44 A PLL loop filter capacitor. 8BIT/$BIT LOS DESCRIPTION ANALOG PINS NAME DESCRIPTION POWER SUPPLY PINS It is recommended that all VCC pins be connected to a single power supply plane and all GND pins be connected to a single ground plane. NAME PIN TYPE DESCRIPTION VCC 43 S Power Supply. GND 4, 7, 21, 29, 45, 47, 48, 58, 61 S Ground. 5 78P2253 E4/STM-1/STS-3/OC-3 Transceiver ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation beyond these limits may permanently damage the device. PARAMETER Supply Voltage Storage Temperature Pin Voltage Pin Current RATING 7 VDC -65 to 150° C -0.3 to (V CC+0.3) VDC ±100 mA RECOMMENDED OPERATING CONDITIONS Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges. PARAMETER RATING DC Voltage Supply, VCC 3.3 ± 0.3 VDC; 5 ± 0.5 VDC Ambient Operating Temperature -40 to 85°C DC CHARACTERISTICS: PARAMETER SYMBOL Supply Current (Parallel Mode) Supply Current (Serial Mode) Icc Icc CONDITIONS MIN NOM MAX UNIT Vcc = 3.3V 140 165 mA Vcc = 5.0V 150 175 VCC = 3.3V 210 245 VCC = 5.0V 280 330 NOM MAX UNIT 0.8 V mA DIGITAL INPUT CHARACTERISTICS Pins of type CI PARAMETER SYMBOL CONDITIONS MIN Input Voltage Low Vil Input Voltage High Vih 2.0 Iil, Iih -10 Input Current Input Capacitance Cin V 10 10 µA pF Pins of type PI PARAMETER SYMBOL CONDITIONS Input Voltage Low Vil Relative to Vcc Input Voltage High Vih Relative to Vcc 6 MIN -1.1 NOM MAX UNIT -1.5 V V 78P2253 E4/STM-1/STS-3/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) DIGITAL OUTPUT CHARACTERISTICS Pins of type CO PARAMETER SYMBOL CONDITIONS Output Voltage Low Vol Iol = 2mA Output Voltage High Voh Ioh = -2mA Transition Time MIN Tt NOM MAX UNIT 0.6 V Vcc – 0.6 V 3.5 ns Pins of type PO PARAMETER Output Voltage Low SYMBOL Vol CONDITIONS Relative to Vcc MIN NOM -1.8 MAX -1.6 UNIT V Output Voltage High Voh Relative to Vcc -1.1 -0.8 V Rise Time Tr 1 ns Fall Time Tf 1 ns DIGITAL TIMING CHARACTERISTICS: Reference Clock Interface CKIN TXCK TCK PARAMETER CKIN to TXCK Propagation Delay SYMBOL CONDITIONS TCK MIN NOM 20 7 MAX UNIT ns 78P2253 E4/STM-1/STS-3/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) DIGITAL TIMING CHARACTERISTICS Transmit Interface TXCKP TXCKN TXDTP TXDTN TSUs PARAMETER SYMBOL THs CONDITIONS MIN NOM MAX UNIT Transmit Setup Time TSUs Serial Mode 1.0 ns Transmit Hold Time THs Serial Mode -0.5 ns TXCKP,N Duty Cycle 40 60 % MAX UNIT TXCK TXDT[7:0] TSUp PARAMETER THp SYMBOL CONDITIONS Transmit Setup Time TSUp Parallel Mode 2.5 ns Transmit Hold Time THp Parallel Mode 0.1 ns TXCK Duty Cycle MIN 40 8 NOM 60 % 78P2253 E4/STM-1/STS-3/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) DIGITAL TIMING CHARACTERISTICS Receive Interface RXCKP RXCKN RXDTP RXDTN PARAMETER Receive Propagation Delay SYMBOL TPROPs TPROPs CONDITIONS MIN Serial Mode RXCKP,N Duty Cycle NOM MAX 1.0 40 UNIT ns 60 % MAX UNIT RXCK RXDT[7:0] TPROPp PARAMETER Receive Propagation Delay SYMBOL TPROPs CONDITIONS MIN Serial Mode RXCKP,N Duty Cycle 4.0 40 9 NOM ns 60 % 78P2253 E4/STM-1/STS-3/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER OUTPUT JITTER The transmit jitter specification ensures compliance with ITU-T G.823 and G.825 and ANSI T1.105.03-1994 for all supported rates. The corner frequency of the transmit PLL is nominally 3.0 MHz. Jitter Detector Measured Jitter Amplitude 20dB/decade Transmitter Output 200 Hz PARAMETER CONDITION Transmitter Output Jitter 200 Hz to 3.5 MHz 3.5 MHz MIN NOM MAX UNIT 0.075 UI TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE IN E4 MODE Bit Rate: 139.264Mbit/s ± 15ppm Code: coded mark inversion (CMI) The following specifications are met with the external components for E4 operation, above, and configured with a recommended 1:1 transformer as in Figure 10. With the coaxial output port driving a 75Ω load, the output pulses conform to the templates in Figure 4 and Figure 5. PARAMETER CONDITION MIN Peak-to-peak Output Voltage Template 0.9 Rise/ Fall Time 10-90% Transition Timing Tolerance Negative Transitions NOM MAX UNIT 1.1 V 2 ns -0.1 0.1 ns Positive Transitions at Interval Boundaries -0.5 0.5 ns Positive Transitions at midinterval -0.35 0.35 ns PARAMETER CONDITION MIN MAX UNIT Return Loss 7MHz to 240MHz TRANSMISSION PERFORMANCE 10 15 NOM dB 78P2253 E4/STM-1/STS-3/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) V 0.60 T = 7.18ns (Note 1) (Note 1) Nominal Pulse 0.55 0.50 0.45 0.40 1.795 ns 1ns 0.1ns 1ns 0.1ns -0.05 -0.40 1ns 0.1ns 0.35ns 0.05 1.795 ns 0.1ns 0.35ns Nominal Zero Level (Note 2) 1ns 1ns 1ns -0.45 -0.50 -0.55 1.795 ns 1.795 ns (Note 1) (Note 1) -0.60 Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again and verifying that the trace lies with ±0.05V of the nominal zero level of the masks. Note 3 – Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed 2ns. FIGURE 4 – MASK OF A PULSE CORRESPONDING TO A BINARY ZERO IN E4 MODE 11 78P2253 E4/STM-1/STS-3/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) V T = 7.18ns 0.60 0.55 (Note 1) (Note 1) 0.50 0.45 1ns 0.40 0.1ns 1ns 0.5ns 0.1ns 0.5ns Nominal Pulse 0.05 Nominal Zero Level (Note 2) -0.05 3.59ns 3.59ns 1.35ns -0.40 -0.45 -0.50 1.35ns 1ns 1ns 1.795 ns 1.795 ns -0.55 (Note 1) -0.60 Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again and verifying that the trace lies with ±0.05V of the nominal zero level of the masks. Note 3 – Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed 2ns. Note 5 –The inverse pulse will have the same characteristics, noting that the timing tolerance at the level of the negative and positive transitions are ± 0.1ns and ±0.5ns respectively. Figure 5 – Mask of a Pulse corresponding to a binary One in E4 mode. 12 78P2253 E4/STM-1/STS-3/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE IN STS-3 (STM-1) MODE Bit Rate: 155.52Mbit/s ± 20ppm Code: coded mark inversion (CMI) The following specifications are met with the external components for STS-1 operation configured with a recpmmended 1:1 transformer as in Figure 10. With the coaxial output port driving a 75Ω load, the output pulses conform to the templates in Figure 6 and Figure 7. PARAMETER CONDITION MIN Peak-to-peak Output Voltage Template 0.9 Rise/ Fall Time 10-90% Transition Timing Tolerance Negative Transitions NOM MAX UNIT 1.1 V 2 ns -0.1 0.1 ns Positive Transitions at Interval Boundaries -0.5 0.5 ns Positive Transitions at midinterval -0.35 0.35 ns PARAMETER CONDITION MIN MAX UNIT Return Loss 7MHz to 240MHz TRANSMISSION PERFORMANCE 13 15 NOM dB 78P2253 E4/STM-1/STS-3/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) V 0.60 0.55 T = 6.43ns (Note 1) (Note 1) Nominal Pulse 0.50 0.45 1ns 0.40 0.1ns 1.608ns 1ns 0.1ns -0.05 -0.40 -0.45 -0.50 -0.55 -0.60 1ns 0.1ns 0.35ns 0.05 1.608ns 0.1ns 0.35ns Nominal Zero Level (Note 2) 1ns 1ns 1.608ns 1ns 1.608ns (Note 1) (Note 1) Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again and verifying that the trace lies with ±0.05V of the nominal zero level of the masks. Note 3 – Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed 2ns. Figure 6 – Mask of a Pulse corresponding to a binary Zero in STS-3 mode. 14 78P2253 E4/STM-1/STS-3/OC-3 Transceiver V 0.60 0.55 6.43ns (Note 1) (Note 1) 0.50 0.45 0.40 1ns 0.1ns 1ns 0.5ns 0.1ns 0.5ns Nominal Pulse 0.05 Nominal Zero Level (Note 2) -0.05 3.215ns 3.215ns 1.2ns -0.40 -0.45 -0.50 1.2ns 1ns 1ns 1.608ns 1.608ns -0.55 (Note 1) -0.60 Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again and verifying that the trace lies with ±0.05V of the nominal zero level of the masks. Note 3 – Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed 2ns. Note 5 –The inverse pulse will have the same characteristics, noting that the timing tolerance at the level of the negative and positive transitions are ± 0.1ns and ±0.5ns respectively. Figure 7 – Mask of a Pulse corresponding to a binary One in STS-3 mode 15 78P2253 E4/STM-1/STS-3/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) RECEIVER SPECIFICATIONS The following specifications are met with the external components. PARAMETER CONDITION MIN NOM LOS Threshold MAX 0.1 UNIT V RECEPTION PERFORMANCE Return Loss 7MHz to 240MHz 15 dB RECEIVER JITTER TOLERANCE STS-3 and OC-3 jitter tolerance specifications are in ANSI T1.105.05-1994 and Telcordia TR-NWT-000253, Issue 2, Dec. 1991. STM-1 specifications are in ITU-T G.825. They are identical except that STM-1 specifies both jitter and wander. The E4 specifications are found in ITU-T G.823. The STM-1 specification is the tightest and covers the largest frequency range. 10000 1000 100 STM-1 E4 10 1 0.1 0.01 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 PARAMETER CONDITION MIN Receiver Jitter Tolerance 12µHz to 178µHz 2800 1.6mHz to 15.6mHz Note 1: Not tested in production 311 125mHz to 19.3 Hz 39 500Hz to 6.5kHz 1.5 65kHz to 3.5MHz 0.15 16 NOM MAX UNIT UI 78P2253 E4/STM-1/STS-3/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) RECEIVER JITTER TRANSFER FUNCTION The receiver clock recovery loop filter characteristics such that the receiver has the following transfer function. 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 The corner frequency of the PLL is approximately 250 kHz. PARAMETER CONDITION Receiver Jitter transfer function below 250 kHz MIN Jitter transfer function roll-off NOM 20 Note 1: Not tested in production MAX UNIT 0.1 dB dB per decade 17 78P2253 E4/STM-1/STS-3/OC-3 Transceiver ELECTRICAL SPECIFICATIONS (continued) RECEIVER SPECIFICATIONS FOR CMI INTERFACE The following specifications are met with the external components for E4 operation, above, and configured with a 1:1 recommended. The input signal is assumed compliant with ITU-T G.703 and attenuated by the dispersive loss of a cable. The minimum cable loss is 0dB and the maximum is shown in Figure 8. The “Worst Case” line corresponds to the01 ITU-T G.703 recommendation. The “Typical” line corresponds to a typical installation referred to in ANSI T1.102-1993. The receiver is tested using the cable model on page n. It is a lumped element approximation of the “Worst Case” line. 30 Attenuation (dB) 25 20 15 10 5 0 1.00E+05 1.00E+06 1.00E+07 1.00E+08 Frequency (Hz) Worst Case Typical Figure 8: Typical and worst-case Cable attenuation 18 1.00E+09 78P2253 E4/STM-1/STS-3/OC-3 Transceiver APPLICATION INFORMATION EXTERNAL COMPONENTS: COMPONENT PIN(S) VALUE UNITS TOLERANCE Reference Resistor RFO 31.6 kΩ 1% Filter Capacitor LF1 150 nF 10% VALUE UNITS TOLERANCE 1:1 3% TOLERANCE TRANSFORMER SPECIFICATIONS: COMPONENT Turns Ratio Suggested Manufacturer: Pulse, MiniCircuits CRYSTAL SPECIFICATIONS: E4 Operation COMPONENT VALUE UNITS Center Frequency 17.408 MHz 27 pF VALUE UNITS 19.44 MHz 27 pF Load Capacitor – XTAL1 to ground; XTAL2 to ground CRYSTAL SPECIFICATIONS: OC-3, STM-1, STS-3 Operation COMPONENT Center Frequency Load Capacitor – XTAL1 to ground; XTAL2 to ground 19 TOLERANCE 78P2253 E4/STM-1/STS-3/OC-3 Transceiver APPLICATION INFORMATION (continued) RTERM RBIAS RBIAS FIGURE 9. PECL INTERFACE PECL INTERFACE COMPONENTS: COMPONENT Output Bias Resistor, RBIAS VALUE UNITS TOLERANCE VCC = 5v 250 Ω 5% VCC = 3.3V 140 Ω 5% 100 Ω 5% Termination Resistor, RTERM When the PECL signals travel one inch or less, lower power operation can be achieved by increasing RBIAS and eliminating RTERM. 20 78P2253 E4/STM-1/STS-3/OC-3 Transceiver VCC VCC C18 C19 C20 0.1uF 0.01uF C2 + 0.1uF GND U1 VCC VCC VCC VCC VCC VCC VCC VCC 3 8 24 40 43 53 54 57 4.7uF RX1 T1 1 5 1 50 R1 75 1% LOS CMIINP 2 2 49 R12 31.6K ADT1-1WT 46 C8 VCC 9 0.1uF C26 5 8 C1 0.1uF 27pF Vcc U2 1 ENA OUT 5 CKIN XTAL1 CRYSTAL Y1 GND Can oscillator or sigle crystal 4 Crystal Osc. VCC Isolated ground under Transformer output J2 TX1 C27 27pF 6 S1 1 2 3 4 5 6 7 8 1 2 62 63 64 42 41 T2 1 6 XTAL2 SW DIP-8 16 15 14 13 12 11 10 9 1 60 R2 301 1% 44 1uF CMINN RFO CMI/ECL HUB/HOST PAR/SER 8BIT/4BIT E4/SONET LLBACK RLBACK D2 LED 1 2 R12 510 C28 LF 6 39 RXCK RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0 TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDT0 TXCK 38 30 31 32 33 34 35 36 37 33 11 12 13 14 15 16 17 18 10 J1 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 CMIOUTP C9 4 3 C3 ADT1-1WT 0.1uF 59 CMIOUTN GND GND GND GND GND GND GND GND GND 2 2 4 7 21 29 45 47 48 58 61 0.1uF 78P2253 FIGURE 10: RECOMMENDED APPLICATION CIRCUIT, STM-1 COAX SERIAL INTERFACE 21 78P2253 E4/STM-1/STS-3/OC-3 Transceiver MECHANICAL SPECIFICATIONS 64-TQFP Mechanical Specification 22 78P2253 E4/STM-1/STS-3/OC-3 Transceiver PACKAGE PIN DESIGNATIONS CMIINN CMIINP ECLINP VCC VCC ECLOUTN ECLOUTP VCC GND CMIOUTN CMIOUTP GND PAR/ SER 8BIT/$BIT E4/SONET ECLINN CAUTION: Use handling procedures necessary for a static sensitive component. (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CMI/ECL 1 48 GND HUB/HOST 2 47 GND VCC 3 46 RFO GND 4 45 GND XTAL1 5 44 LF XTAL2 6 43 VCC GND 7 42 LLBA CK VCC 8 41 RLBACK CKIN 9 40 VCC TXCK 10 39 LOS TXDT7 11 38 RXCK TXDT6 12 37 RXDT0 TXDT5 13 36 RXDT1 TXDT4 14 35 RXDT2 TXDT3 15 34 RXDT3 TXDT2 16 33 RXDT4 RXDT5 RXTD6 RXDT7 GND RXDTN RXTDP RXCKN RXCKP VCC TXCKN TXCKP GND TXDTN TXDTP TXDT0 TXDT1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64-Pin TQFP (JEDEC LQFP) 78P2253-I64GT ORDERING INFORMATION PART DESCRIPTION ORDER NUMBER PACKAGING MARK 78P2253 64- Pin Thin Quad Flatpack 78P2253-IGT 78P2253-IGT Advanced Information: Indicates a product is either in prototype testing or undergoing design evaluation prior to full production release. Specifications are based on design goals or preliminary evaluation and are not guaranteed. Small quantities are usually available and TDK Semiconductor Corporation should be consulted for current information. No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that you are referencing the most current data sheet before placing orders. To do so, see our web site at http://www.tsc.tdk.com or contact your local TDK Semiconductor representative. TDK Semiconductor Corporation, 2642 Michelle Drive, Tustin, CA 92780-7019, (714) 508-8800, FAX: (714) 508-8877 2000 TDK Semiconductor Corporation 11/08/00- rev. D 23