OKI Semiconductor ML674001/Q4002/Q4003 FEDL674001-01 Issue Date: Dec. 15, 2003 32-bit ARM-Based General-Purpose Microcontroller GENERAL DESCRIPTION The ML674001, ML67Q4002, and ML67Q4003 microcontrollers (MCUs) are the members of an extensive and growing family of 32-bit ARM®-based standard products for general-purpose applications that require 32-bit CPU performance and low cost afforded by MCU integrated features. ML674001/67Q4002/67Q4003 provide built-in 32Kbyte SRAM, built-in 4Kbyte boot ROM, and a host of other useful peripherals such as auto-reload timers, watchdog timer (WDT), pulse-width modulators (PWM), A-to-D converter, expanded UARTs, synchronous serial port, I2C serial interface, GPIOs, DMA controller, external memory controller, and boundary scan capability. In addition, the ML67Q4002 and ML67Q4003 offer 256 Kbytes and 512 Kbytes of built-in Flash memory respectively. The ML674001, ML67Q4002 and ML67Q4003 are pin-to-pin compatible with each other for easy performance updates. Oki’s ML674K Family MCUs are capable of executing both the 32-bit ARM instruction set for high-performance applications as well as the 16-bit Thumb® instruction set for high code-density, power-efficient applications. With an ARM7TDMI® core operating at 33 MHz maximum frequency, ARM Thumb™ capabilities, and robust feature sets, the ML674001 Series MCUs are suitable for an array of applications including high performance industrial controllers and instrumentation, telecom, PC peripherals, security/surveillance, test equipment, and a variety of consumer electronics devices. The ARM7TDMI® Advantage Oki’s ML674K Family of low-cost ARM-based MCUs offers system designers a bridge from 8- and 16-bit proprietary MCU architectures to ARM’s higher-performance, affordable, widely-accepted industry standard architecture and its industry-wide support infrastructure. The ARM industry infrastructure offers the system developers many advantages including software compatibility, many ready-to-use software applications, large choices among hardware and software development tools. These ARM-based advantages allow Oki’s customers to better leverage engineering resources, lower development costs, minimize project risks, and reduce their product time to market. In addition, migration of a design with an Oki standard MCU to an Oki custom solution is easily facilitated with its award-winning uPLAT™ product development architecture. FEATURES • CPU 32-bit RISC CPU (ARM7TDMI) 32-bit instructions (ARM Instructions) and 16-bit instructions (Thumb Instructions) mixed General purpose registers : 31 x 32 bits Built-in Barrel shifter and multiplier (32 bit x 8 bit, Modified Booth’s Algorithm) Little endian Built-in debug function • Internal memory RAM 32KB (32-bit access) FLASH (16-bit access) ML674001 : ROM-less version ML67Q4002 : 256Kbytes ML67Q4003 : 512Kbytes ARM, ARM7TDMI, Multi-ICE and AMBA are registered trademarks of ARM Ltd., UK. µPLAT is Oki's trademark. The contents of this data sheet are subject to change for modification without notice. 1/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 • External memory controller ROM (FLASH): 16 Mbytes SRAM: 16 Mbytes DRAM: 64 Mbytes (SDRAM and EDO-DRAM support) External IO devices: 16 Mbytes x 2 banks, 4 Chip select pins Wait control input signal for each bank Independent programmable wait settings for each bank • Interrupt controller 28 sources: 23 internals and 5 externals (IRQ: 4, FIQ: 1) • DMA controller 2 channels: Dual address mode, cycle steal and burst tranfer mode • Timer 1 channel: 16-bit auto reload for operating system 6 channels: 16-bit auto reload for application 1 channel: 16 bit watchdog timer • Serial interface 1 channel: UART 1 channel: UART with 16-byte FIFO 1 channel: synchronous 1 channel: I2C (single master) • Parallel I/O Port 4 ports x 8 bits (bitwise input/output settings) 1 port x 10 bit (bitwise input/output settings) • PWM 2 channels x 16 bits • Analog-to-Digital Converter 4 channels x 10 bits • Power down mechanism Standby (all clock stop) and Halt (clock stop by each function block) Clock gear (selectable 1/1, 1/2, 1/4, 1/8, 1/16 input clock frequency) • JTAG interface Connectable to JTAG ICE • Power supply voltage Core section: 2.25 V to 2.75 V IO section: 3.0 V to 3.6 V Analog section: 3.0 V to 3.6 V • Operating frequency 1-33 MHz • Operating temperature (ambient temperature) –40°C to +85°C • Package 144-pin plastic LQFP (LQFP144-P-2020-0.50) 144-pin plastic LFBGA (P-LFBGA144-1111-0.80) 2/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 BLOCK DIAGRAM 5 TDI TDO nTRST TMS TCK Internal (MCP) FLASH ROM ML67Q4002 : 256KB ML67Q4003 : 512KB Internal RAM 32KB µPLAT-7B Internal & External Memory controller ARM7TDMI TIC DRAMC AHB Bridge Boot ROM 4KB AMBA AHB bus APB Bridge Exp. IRC IRC AMBA APB bus DMAC APB Bridge PIOC[6:2] / XA[23:19] XA[18:0] XD[15:0] PIOC[7] / XWR XOE_N XWE_N XBWE_N[1:0] XROMCS_N XRAMCS_N XIOCS_N[3:0] XBS_N[1:0] PIOD[0] / XWAIT PIOD[1] / XCAS_N PIOD[2] / XRAS_N PIOD[3] / XSDCLK PIOD[4] / XSDCS_N PIOD[5] / XSDCKE PIOD[6] / XDQM[1]/XCAS_N[1] PIOD[7] / XDQM[0]/XCAS_N[0] 2 PIOB[0] / DREQ[0] PIOB[2] / DREQ[1] 2 PIOB[1] / DREQCLR[0] PIOB[3] / DREQCLR[1] 2 PIOB[4] / TCOUT[0] PIOB[5] / TCOUT[1] APB bus System TMR UART System Control TMR 16 bit x 6ch PWM RESET_N PIOB[6] / STXD PIOB[7] / SRXD OSC0 OSC1_N WDT UART (16550) CGB CKOE_N CKO PIOE[8:5] / EXINT[3:0] PIOE[9] / EFIQ_N SSIO 8 A/D GPIO PIOC[1:0] / PWMOUT[1:0] PIOA[0] / SIN PIOA[1] / SOUT PIOA[2] / CTS PIOA[3] / DSR PIOA[4] / DCD PIOA[5] / DTR PIOA[6] / RTS PIOA[7] / RI 3 PIOE[0] / SCLK PIOE[1] / SDI PIOE[2] / SDO 2 PIOE[3] / SDA PIOE[4] / SCL 5 AIN[3:0] VREF 5 I2C VDD_CORE VDD_IO GND AVDD AGND DRAME_N TEST BSEL[1:0] FWR JSEL 2 16 bit x 2ch 42 PIOA[7:0] PIOB[7:0] PIOC[7:0] PIOD[7:0] PIOE[9:0] 3/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 PIN CONFIGURATION (TOP VIEW) 144-Pin Plastic LFBGA 5 4 3 2 1 N PIOD[6]/ XIOCS_ XIOCS_ XRAMC XBWE_ PIOC[4]/ XDQM[1 XOE_N XA[16] N[3] N[1] S_N N[0] XA[21] ] 13 12 XA[14] XA[11] XA[9] XA[7] XA[6] M PIOD[7]/ XIOCS_ XIOCS_ PIOC[7]/ PIOC[6]/ PIOC[2]/ XWE_N XA[17] XDQM[0 N[2] N[0] XWR XA[23] XA[19] ] XA[15] XA[13] XA[10] XA[4] XA[5] L PIOB[1]/ PIOB[2]/ PIOB[0]/ XROMC XBWE_ PIOC[5]/ PIOC[3]/ DREQC XA[18] DREQ[1] DREQ[0] S_N N[1] XA[22] XA[20] LR[0] XA[12] VDD_IO XA[8] XA[2] GND K PIOB[3]/ PIOB[5]/ DREQC TCOUT[ VDD_IO 1] LR[1] GND XA[3] XA[0] XD[13] XA[1] J PIOC[0]/ PWMOU T[0] VDD_IO XD[15] XD[11] XD[14] H XBS_N[ XBS_N[ PIOD[0]/ VDD_C 0] 1] XWAIT ORE G PIOD[2]/ PIOD[1]/ VDD_IO XRAS_N XCAS_N F GND 11 10 GND 9 VDD_IO 8 7 VDD_C VDD_IO ORE 6 GND PIOB[4]/ PIOC[1]/ TCOUT[ PWMOU T[1] 0] VDD_C ORE XD[10] NC XD[12] VDD_IO XD[8] NC XD[9] PIOD[4]/ PIOD[5]/ PIOD[3]/ XSDCS_ BSEL[1] XSDCK XSDCLK N E GND XD[7] XD[6] XD[5] E PIOE[7]/ PIOE[8]/ PIOE[5]/ BSEL[0] EXINT[2] EXINT[3] EXINT[0] GND XD[2] NC XD[4] D PIOE[0]/ PIOE[6]/ PIOE[9]/ PIOE[2]/ PIOA[1]/ OSC1_N SCLK EXINT[1] EFIQ_N SDO SOUT GND VDD_IO XD[3] XD[1] FWR XD[0] RESET_ N 144pin LFBGA (TOP VIEW) GND AIN[0] NC C TDI PIOE[1]/ SDI CKO TMS CKOE_ N AVDD AIN[1] AIN[3] B nTRST TDO TCK GND VDD_IO PIOA[0]/ SIN VREF AGND A NC NC JSEL DRAME _N OSC0 TEST AIN[2] 13 12 11 10 9 8 7 Notes: VDD_IO VDD_C PIOA[5]/ ORE DTR GND PIOA[3]/ PIOA[7]/ PIOE[4]/ PIOB[7]/ DSR RI SCL SRXD PIOA[2]/ PIOA[4]/ PIOA[6]/ PIOE[3]/ PIOB[6]/ CTS DCD RTS SDA STXD 6 5 4 3 2 NC 1 NC pins are electrically unconnected in the package. NC pins can be connected to Vdd or GND. 4/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 CTS DSR DCD DTR RTS RI SDA SCL STXD XDQM[0]/XCAS_N[0] XDQM[1]/XCAS_N[1] DREQCLR[0] DREQ[0] PWMOUT[1] PWMOUT[0] TCOUT[1] TCOUT[0] DREQCLR[1] DREQ[1] XCAS_N XWAIT XSDCKE XSDCS_N XSDCLK XRAS_N (Primary functi (Secondary f 74 73 75 77 76 79 78 80 82 81 84 83 85 87 86 89 88 90 92 91 94 93 95 97 96 101 100 99 98 102 104 103 106 105 107 (Primary f SIN SOUT NC NC CKO JSEL TMS TCK DRAME_N CKOE_N GND OSC0 OSC1_N VDD_IO TEST PIOA[0] PIOA[1] AVDD VREF AIN[0] AIN[1] AIN[2] AIN[3] NC AGND GND PIOA[2] VDD_IO PIOA[3] PIOA[4] VDD_CORE PIOA[5] PIOA[6] PIOA[7] GND PIOE[3] PIOE[4] PIOB[6] 108 (Secondary fun(Primary function) nTRST TDO TDI PIOE[2] PIOE[1] PIOE[0] PIOE[9] PIOE[8] PIOE[7] PIOE[6] PIOE[5] BSEL[1] BSEL[0] PIOD[5] PIOD[4] PIOD[3] PIOD[2] VDD_IO GND PIOD[1] PIOD[0] VDD_CORE XBS_N[1] XBS_N[0] GND PIOC[1] PIOC[0] PIOB[5] PIOB[4] PIOB[3] PIOB[2] VDD_IO PIOB[1] PIOB[0] PIOD[7] PIOD[6] (Seconda SDO SDI SCLK EFIQ_N EXINT[3] EXINT[2] EXINT[1] EXINT[0] 144-Pin Plastic LQFP 109 72 110 111 71 70 112 113 69 68 114 115 67 66 116 65 117 118 64 63 119 120 62 61 121 60 122 123 59 58 144pin LQFP (TOP VIEW) 124 125 126 57 56 55 127 128 54 53 129 130 52 51 131 50 132 133 49 48 134 135 47 46 136 45 137 138 44 43 139 140 42 41 141 142 40 39 143 38 144 37 XIOCS_N[3] XIOCS_N[2] XIOCS_N[1] GND XIOCS_N[0] XRAMCS_N XROMCS_N XBWE_N[1] XBWE_N[0] XWE_N VDD_IO XOE_N PIOC[7] PIOC[6] VDD_CORE PIOC[5] PIOC[4] PIOC[3] VDD_IO PIOC[2] XA[18] GND XA[17] XA[16] XA[15] GND XA[14] XA[13] XA[12] XA[11] XA[10] VDD_IO XA[9] XA[8] XA[7] XA[6] XWR XA[23] XA[22] XA[21] XA[20] XA[19] SRXD (Primary f (Seconda Notes: NC PIOB[7] FWR RESET_N VDD_IO XD[0] XD[1] XD[2] XD[3] XD[4] GND NC XD[5] XD[6] GND XD[7] NC VDD_IO XD[8] XD[9] XD[10] VDD_CORE NC XD[11] XD[12] VDD_IO XD[13] XD[14] XD[15] XA[0] XA[1] XA[2] XA[3] GND XA[4] XA[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC pins are electrically unconnected in the package. NC pins can be connected to Vdd or GND. 5/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 LIST OF PINS Pin Primary Function Symbol Secondary Function Description I/O Symbol LQFP BGA 1 A1 NC — NC 2 B1 PIOB[7] I/O General port (with interrupt function) SRXD 3 C3 FWR I Test mode — — 4 C1 RESET_N I Reset input — — 5 D3 VDD_IO VDD IO power supply — — 6 C2 XD[0] I/O External data bus — — 7 D1 XD[1] I/O External data bus — — 8 E3 XD[2] I/O External data bus — — 9 D2 XD[3] I/O External data bus — — 10 E1 XD[4] I/O 11 E4 GND GND 12 E2 NC 13 F1 14 F2 15 16 — I/O — I External data bus — — GND — — — NC — — XD[5] I/O External data bus — — XD[6] I/O External data bus — — F4 GND GND GND — — F3 XD[7] I/O External data bus — — 17 G2 NC — NC — — 18 G4 VDD_IO VDD I/O power supply — — 19 G3 XD[8] I/O External data bus — — 20 G1 XD[9] I/O External data bus — — 21 H3 XD[10] 22 H4 VDD_CORE 23 H2 NC — NC — — 24 J2 XD[11] I/O External data bus — — 25 H1 XD[12] I/O External data bus — — 26 J4 VDD_IO VDD I/O power supply — — 27 K2 XD[13] I/O External data bus — — 28 J1 XD[14] I/O External data bus — — 29 J3 XD[15] I/O External data bus — — 30 K3 XA[0] O External address output — — 31 K1 XA[1] O External address output — — 32 L2 XA[2] O External address output — — 33 K4 XA[3] O External address output — — 34 L1 GND GND GND — — 35 M2 XA[4] O External address output — — 36 M1 XA[5] O External address output — — 37 N1 XA[6] O External address output — — 38 N2 XA[7] O External address output — — 39 L3 XA[8] O External address output — — 40 N3 XA[9] O External address output — — I/O VDD Description External data bus — — CORE power supply — — SIO receive signal 6/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 Pin LQFP Primary Function BGA Symbol Description I/O VDD Secondary Function Symbol 41 L4 VDD_IO I/O power supply — — 42 M3 XA[10] O External address output — — 43 N4 XA[11] O External address output — — 44 L5 XA[12] O External address output — — 45 M4 XA[13] O External address output — — 46 N5 XA[14] 47 K5 GND 48 M5 XA[15] O GND O External address output — — GND — — External address output — — 49 N6 XA[16] O External address output — — 50 M6 XA[17] O External address output — — 51 K6 GND GND — — GND Description I/O 52 L6 XA[18] O External address output — — 53 M7 PIOC[2] I/O General port (with interrupt function) XA[19] O 54 K7 VDD_IO VDD I/O power supply — — 55 L7 PIOC[3] I/O General port (with interrupt function) XA[20] O External address output 56 N7 PIOC[4] I/O General port (with interrupt function) XA[21] O External address output External address output 57 L8 PIOC[5] 58 K8 VDD_CORE 59 M8 PIOC[6] 60 M9 61 I/O External address output General port (with interrupt function) XA[22] O CORE power supply — — I/O General port (with interrupt function) XA[23] O External address output PIOC[7] I/O General port (with interrupt function) XWR O Transfer direction of external bus N8 XOE_N O Output enable (excluding SDRAM) — — 62 K9 VDD_IO VDD I/O power supply — — 63 M10 XWE_N O Write enable — — 64 N9 XBWE_N[0] O Byte write enable (LSB) — — 65 L9 XBWE_N[1] O Byte write enable (MSB) — — 66 L10 XROMCS_N O External ROM chip select — — 67 N10 XRAMCS_N O External RAM chip select — — 68 M11 XIOCS_N[0] 69 K10 GND 70 N11 XIOCS_N[1] 71 M12 72 N12 73 N13 VDD O IO chip select 0 — — GND — — O IO chip select 1 — — XIOCS_N[2] O IO chip select 2 — — XIOCS_N[3] O IO chip select 3 — — PIOD[6] I/O General port (with interrupt function) XDQM[1]/XCAS O GND _N[1] INPUT/OUTPUT mask/CAS (MSB) 74 M13 PIOD[7] I/O General port (with interrupt function) XDQM[0]/XCAS _N[0] O INPUT/OUTPUT mask/CAS (LSB) 75 L11 PIOB[0] I/O General port (with interrupt function) DREQ[0] I DMA request signal (CH0) 76 L13 PIOB[1] I/O General port (with interrupt function) DREQCLR[0] O DREQ Clear Signal (CH0) 77 K11 VDD_IO VDD 78 L12 PIOB[2] I/O I/O power supply — General port (with interrupt function) DREQ[1] — I DMA request signal (CH1) 7/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 Pin Primary Function LQFP BGA 79 K13 Symbol PIOB[3] I/O Description I/O General port (with interrupt function) Secondary Function Symbol DREQCLR[1] Description I/O O DREQ Clear Signal (CH1) 80 J11 PIOB[4] I/O General port (with interrupt function) TCOUT[0] O 81 K12 PIOB[5] I/O General port (with interrupt function) TCOUT[1] O DMAC Terminal Count (CH0) DMAC Terminal Count (CH1) 82 J13 PIOC[0] I/O General port (with interrupt function) PWMOUT[0] O PWM output (CH0) 83 J10 PIOC[1] I/O General port (with interrupt function) PWMOUT[1] O PWM output (CH1) 84 J12 GND GND — — 85 H13 XBS_N[0] O External bus byte select (LSB) — — 86 H12 XBS_N[1] O External bus byte select (MSB) — — CORE power supply — — General port (with interrupt function) XWAIT 87 H10 VDD_CORE 88 H11 PIOD[0] GND VDD I/O I Wait input signal for I/O Banks 89 G12 PIOD[1] I/O 90 G10 GND GND GND — — 91 G11 VDD_IO VDD I/O power supply — — 92 G13 PIOD[2] I/O General port (with interrupt function) XRAS_N O Row address strobe (SDRAM/EDO) 93 F11 PIOD[3] I/O General port (with interrupt function) XSDCLK O Clock for SDRAM 94 F10 PIOD[4] I/O General port (with interrupt function) XSDCS_N O Chip select for SDRAM 95 F12 PIOD[5] I/O General port (with interrupt function) XSDCKE O Clock enable (SDRAM) 96 E12 BSEL[0] I Select boot device — — 97 F13 BSEL[1] I Select boot device — — 98 E10 PIOE[5] I/O General port (with interrupt function) EXINT[0] I Interrupt input 99 D12 PIOE[6] I/O General port (with interrupt function) EXINT[1] I Interrupt input 100 E13 PIOE[7] I/O General port (with interrupt function) EXINT[2] I Interrupt input 101 E11 PIOE[8] I/O General port (with interrupt function) EXINT[3] I Interrupt input 102 D11 PIOE[9] I/O General port (with interrupt function) EFIQ_N I FIQ input 103 D13 PIOE[0] I/O General port (with interrupt function) SCLK 104 C12 PIOE[1] I/O General port (with interrupt function) SDI I SSIO Serial Data In 105 D10 PIOE[2] I/O General port (with interrupt function) SDO O SSIO Serial Data Out 106 C13 TDI I JTAG data Input — — 107 B12 TDO O JTAG data out — — I General port (with interrupt function) XCAS_N O I/O 108 B13 nTRST JTAG reset — — 109 A13 NC — NC — — 110 A12 NC — NC — — 111 C11 CKO O Clock output — — 112 A11 JSEL I JTAG select — — 113 C10 TMS I JTAG mode select — — 114 B11 TCK I JTAG clock — — 115 A10 DRAME_N I DRAM enable — — Column address strobe (SDRAM) SSIO clock 8/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 Pin LQFP Primary Function BGA Symbol Description I/O 116 C9 CKOE_N 117 B10 GND GND I 118 A9 OSC0 I 119 D9 OSC1_N O 120 B9 VDD_IO VDD I Secondary Function Symbol I/O Clock out enable — — GND — — Oscillation input pin — — Oscillation output pin — — IO power supply — — — Description 121 A8 TEST Test mode input — 122 B8 PIOA[0] I/O General port (with interrupt function) SIN I UART Serial Data In 123 D8 PIOA[1] I/O General port (with interrupt function) SOUT O UART Serial Data Out 124 C8 AVDD VDD A/D CONVERTER power supply — — 125 B7 VREF I A/D CONVERTER Reference — — voltage 126 D7 AIN[0] I A/D CONVERTER analog input port — — 127 C7 AIN[1] I A/D CONVERTER — — — — A/D CONVERTER analog input port — — NC — — GND for A/D CONVERTER — — — analog input port 128 A7 AIN[2] I A/D CONVERTER analog input port 129 C6 AIN[3] I 130 D6 NC 131 B6 AGND GND 132 B5 GND GND 133 A6 PIOA[2] I/O 134 D5 VDD_IO VDD — GND — General port (with interrupt function) CTS IO power supply — I UART Clear To Send — 135 B4 PIOA[3] I/O General port (with interrupt function) DSR I UART Set Ready 136 A5 PIOA[4] I/O General port (with interrupt function) DCD I UART Carrier Detect 137 C5 VDD_CORE CORE power supply — — 138 C4 PIOA[5] I/O General port (with interrupt function) DTR O UART Data Terminal Ready 139 A4 PIOA[6] I/O General port (with interrupt function) RTS O UART Request To Send I/O General port (with interrupt function) RI I UART Ring Indicator GND — — General port (with interrupt function) SDA I/O 140 B3 PIOA[7] 141 D4 GND 142 A3 PIOE[3] VDD GND I/O I2C Data In/Out 143 B2 PIOE[4] I/O General port (with interrupt function) SCL O I2C Clock out 144 A2 PIOB[6] I/O General port (with interrupt function) STXD O SIO send data output 9/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 PIN DESCRIPTION Pin Name Description I/O Primary/ Logic Secondary System RESET_N I Reset input BSEL[1:0] I Boot device select signal BSEL[1] BSEL[0] — Negative — Positive — — — — Boot device 0 0 Internal Flash (External ROM for ML674001) 0 1 External ROM 1 * Boot mode The selected device is mapped to BANK0 (0x0000_0000 - 0x07FF_FFFF) after reset. OSC0 I Crystal connection or external clock input. Connect a crystal (16 MHz to 33 MHz), if used, to OSC0 and OSC1_N. It is also possible to input a direct clock. OSC1_N O Crystal connection. When not using a crystal, leave this pin unconnected. CKO O Clock out — — CKOE_N I Clock out enable — Negative TCK I Debugging pin. Normally connect to ground level. — — TMS I Debugging pin. Normally drive at High level. — Positive nTRST I Debugging pin. Normally connect to ground level. — Negative TDI I Debugging pin. Normally drive at High level. — Positive TDO O Debugging pin. Normally leave open. — Positive Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive Debugging support. General-purpose I/O ports PIOA[7:0] I/O General-purpose port. Not available for use as port pins when secondary functions are in use. PIOB[7:0] I/O General-purpose port. Not available for use as port pins when secondary functions are in use. PIOC[7:0] I/O PIOD[7:0] I/O General-purpose port. Not available for use as port pins when secondary functions are in use. General-purpose port. Not available for use as port pins when secondary functions are in use. Note that enabling DRAM controller with DRAME_N inputs permanently configures PIOD[7:0] for their secondary functions, making them unavailable for use as port pins. PIOE[9:0] I/O General-purpose port. Not available for use as port pins when secondary functions are in use. 10/24 FEDL674001-01 OKI Semiconductor Pin Name ML674001/67Q4002/67Q4003 Description I/O Primary / Secondary Logic External Bus XA[23:19] O Address bus to external RAM, external ROM, external I/O banks, and Secondary Positive — Positive — Positive external DRAM. After a reset, these pins are configured for their primary function (PIOC[6:2]). XA[18:0] O Address bus to external RAM, external ROM, external I/O banks, and external DRAM. XD[15:0] I/O Data bus to external RAM, external ROM, external I/O banks, and external DRAM. External bus control signals (ROM/SRAM/IO) XROMCS_N O ROM bank chip select — Negative XRAMCS_N O SRAM bank chip select — Negative XIOCS_N[0] O IO chip select 0 — Negative XIOCS_N[1] O IO chip select 1 — Negative XIOCS_N[2] O IO chip select 2 — Negative XIOCS_N[3] O IO chip select 3 — Negative XOE_N O Output enable/ Read enable — Negative XWE_N O Write enable — Negative XBS_N[1:0] O Byte select: XBS_N[1] is for MSB, XBS_N[0] is for LSB — Negative XBWE_N[0] O LSB Write enable — Negative XBWE_N[1] O MSB Write enable XWR O Data transfer direction for external bus, used when connecting to Motorola I/O devices. This represent the secondary function of pin PIOC[7]. L: read , H: write. XWAIT I — Negative Secondary — Secondary Positive Available for I/O bank 0/1. External I/O bank 0/1, 2/3 WAIT signal. This input permits access to devices slower than register settings. External bus control signals (DRAM) XRAS_N O Row address strobe. Used for both EDO DRAM and SDRAM Secondary Negative XCAS_N O Column address strobe signal (SDRAM) Secondary Negative XSDCLK O SDRAM clock (same frequency as internal HCLK) Secondary — XSDCKE O Clock enable (SDRAM) Secondary — XSDCS_N O Chip select (SDRAM) Secondary Negative XDQM[1]/XCAS_N[1] O Connected to SDRAM: DQM (MSB) Secondary Connected to EDO DRAM: column address strobe signal (MSB) XDQM[0]/XCAS_N[0] O Connected to SDRAM: DQM (LSB) Connected to EDO DRAM: column address strobe signal (LSB) Positive/ Negative Secondary Positive/ Negative 11/24 FEDL674001-01 OKI Semiconductor Pin Name ML674001/67Q4002/67Q4003 I/O Primary / Description Secondary Logic DMA control signals DREQ[0] I Ch 0 DMA request signal, used when DMA controller configured for Secondary Positive Secondary Positive DREQ type DREQCLR[0] O Ch 0 DREQ signal clear request. The DMA device responds to this output by negating DREQ. TCOUT[0] O Indicates to Ch 0 DMA device that last transfer has started. Secondary Positive DREQ[1] I Ch 1 DMA request signal, used when DMA controller configured for Secondary Positive Secondary Positive DREQ type DREQCLR[1] O Ch 1 DREQ signal clear request. The DMA device responds to this output by negating DREQ. TCOUT[1] O Indicates to Ch 1 DMA device that last transfer has started Secondary Positive SIN I SIO receive signal Secondary Positive SOUT O SIO transmit signal Secondary Positive CTS I Clear To Send. Secondary Negative Secondary Negative Secondary Negative Secondary Negative Secondary Negative Secondary Negative UART Indicates that modem or data set is ready to transfer data. Bit 4 in modem status register reflects this input. DSR I Data Set Ready. Indicates that modem or data set is ready to establish a communications link with UART. Bit 5 in modem status register reflects this input. DCD I Data Carrier Detect. Indicates that modem or data set has detected data carrier signal. 7 in modem status register reflects this input. Bit Data Carrier Detect DTR O Data Terminal Ready. Indicates that UART is ready to establish a communications link with modem or data set. output. RTS O Bit 0 in modem control register controls this Request To Send. Indicates that UART is ready to transfer data to modem or data set. Bit 1 in modem control register controls this output. RI I Ring Indicator. Indicates that modem or data set has received telephone ring indicator. Bit 6 in modem status register reflects this input. 12/24 FEDL674001-01 OKI Semiconductor Pin Name ML674001/67Q4002/67Q4003 I/O Description Primary / Secondary Logic SIO STXD O SIO transmit signal Secondary Positive SRXD I SIO receive signal Secondary Positive I2C Data. Secondary Positive Secondary — I2C SDA I/O This pin operates as NMOS Open drain. Connect pull-up resistor. SCL O I2C Clock. resistor. This pin operates as NMOS Open drain. Connect pull-up Synchronous SIO SCLK Serial clock Secondary — SDI I/O I Serial receive data Secondary Positive SDO O Serial transmit data Secondary Positive PWMOUT[0] O PWM output of CH0 Secondary Positive PWMOUT[1] O PWM output of CH1 Secondary Positive PWM signals Analog-to-digital converter AIN[0] I Ch0 analog input — — AIN[1] I Ch1 analog input — — AIN[2] I Ch2 analog input — — AIN[3] I Ch3 analog input — — VREF I Analog-to-digital converter convert reference voltage — — AVDD Analog-to-digital converter power supply — — AGND Analog-to-digital converter ground — — External interrupt input signals. Secondary Positive / Negative External fast interrupt input signal. Secondary Negative — Negative Interrupt signals EXINT[3:0] I EFIQ_N I Interrupt controller connects this to CPU FIQ input. MODE configuration DRAME_N I DRAM enable mode TEST I Test mode — Positive FWR I Test mode — Positive JSEL I JTAG select signal. — — L: On-board debug, H: Boundary scan. Power supplies VDD_CORE Core power supply — — VDD_IO I/O power supply — — GND GND for core and I/O — — 13/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 DESCRIPTION OF FUNCTIONS CPU CPU core: Operating frequency: Byte ordering: Instructions: General register bank: Built-in barrel shifter: Multiplier: Built-in debug function: ARM7TDMI 1 MHz to 33 MHz Little endian ARM instruction (32-bit length) and Thumb instruction (16-bit length) can be mixed. 31 × 32 bits ALU and barrel shift operations can be executed by one instruction. 32 bits × 8 bits (Modified Booth’s Algorithm) JTAG interface, break point register Built-in Memory FLASH ROM: ML674001 : ROM-less version ML67Q4002 : 256Kbytes (128K x 16 bits) ML67Q4003 : 512Kbytes (256K x 16 bits) Access timing of this FLASH memory is configured by the ROM bank control register of the external memory controller. RAM: 32KB (8K x 32bits) Read access(8/16/32bit): 1 cycle, Write access(32bit): 1 cycle, Write aceess(8/16bit): 2 cycle, Interrupt Controller Fast interrupt request (FIQ) and interrupt request (IRQ) are employed as interrupt input signals. The interrupt controller controls these interrupt signals going to ARM core. (1) Interrupt sources FIQ: 1 external source (external pin: EFIQ_N) IRQ: total of 27 sources. 23 internal sources, and 4 external sources (external pins: EXINT[3:0]) (2) Interrupt priority level Configurable, 8-level priority for each source (3) External interrupt pin input EXINT[3:0] can be set as Level or Edge sensing. Configurable High or Low when Level sensing. Configurable Rise or Falling edge triggering when Edge sensing. EFIQ_N is set as Falling edge triggering. Timers 7 channels of 16-bit reload timers are employed. Of these, 1 channel is used as system timer for OS. The timers of other 6 channels are used in application software. (1) System timer: 1 channel 16-bit auto reload timer: Used as system timer for OS. Interrupt request by timer overflow. (2) Application timer: 6 channels 16-bit auto reload timer. Interrupt request by compare match. One shot, interval Clock can be independently set for each channel 14/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 WDT Functions as an interval timer or a watch dog timer. (1) (2) (3) (4) 16-bit timer Watch dog timer or interval timer mode can be selected Interrupt or reset generation. Maximum period: longer than 200 msec PWM This LSI contains two channels of PWM (Pulse Width Modulation) function which can change the duty cycle of a waveform with a constant period. The PWM output resolution is 16 bits for each channel. Serial Interface This LSI contains four serial interface. (1) UART without FIFO : 1 channel This is the serial port which performs data transmission, taking a synchronization per character. Selection of various parameters, such as addition of data length, a stop bit, and a parity bit, is possible. - Asynchronous full duplex operation - Sampling Rate = Baud rate x 16sample - Character Length : 7, 8 bit - Stop Bit Length : 1, 2 bit - Parity : Even, Odd, none - Error Detection : Parity, Framing, Over run - Loop Back Function : ON/OFF, Parity, framing, Over run Compulsive addition - Baud Rate Generation : Exclusive baud rate generator built-in (8bit counter) Independent from a bus clock - Internal-Baud-Rate-Clock-Stop at the time of HALT Mode. (2) UART with 16bytes FIFO : 1channel Features 16bytes FIFO in both send and receive. Uses the industry standard 16550A ACE (Asynchronous Communication Element). - Asynchronous full duplex operation - Reporting function for all status - 16 Byte Transmission and reception FIFO - Transmission, reception, interrupt of line status Data set and Independent FIFO control. - Modem control signals : CTS, DCD, DSR, DTR, RI and RTS - Data length : 5, 6, 7, 8 bit - Stop bit length : 1, 1.5, 2 bit - parity : Even, Odd, none - Error Detection : Parity, Framing, Overrun - Baud Rate Generation : Exclusive baud rate generator built-in (3) Synchronous serial interface : 1channel It is a clock synchronous 8bit serial port - selectable 1/8, 1/16 or 1/32 of HCLK frequency. - Choose LSB First or MSB First. - Choose Master / Slave Mode - Transceiver Interruption, Transceiver buffer empty interrupt - Loopback Test Function (4) I2C : 1channel Based on the I2C BUS specifications. Operates as a single master device. - Communication mode : Master transmitter /master receiver - Transmission Speed : 100kbps (Standard mode) / 400kbps (Fast mode) - Addressing format : 7 bit / 10 bit - Data buffer : 1 Byte(1step) - Communication Voltage : 2.7V to 3.3V 15/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 GPIO 42-bits parallel port (four 8-bit ports and one 10-bit port). (1) (2) (3) (4) (5) PIOA[7:0] Combination port UART PIOB[7:0] Combination port DMAC, UART(uPLAT-7B), PIOC[7:0] Combination port PWM, XA[23:19], XWR PIOD[7:0] Combination port DRAM contorol signal etc. PIOE[9:0] Combination port SSIO, I2C, External interrupt signal Input/output selectable at bit level. Each bit can be used as an interrupt source. Interrupt mask and interrupt polarity can be set for all bits. The ports are configured as input, immediately after reset. Primary/secondary function of each port can be set independently. AD Converter Successive approximation type AD converter. (1) (2) (3) (4) (5) 10 bits × 4 channels Sample hold function Scan mode and select mode are supported Interrupt is generated after completion of conversion. Conversion time: 5 µs minimum. DMAC Two channels of direct memory access controller which transfers data between memory and memory, between I/O and memory and between I/O and I/O. (1) Number of channels: 2 channels (2) Channel priority level: Fixed mode Channel priority level is always fixed (channel 0 > 1). Roundrobin Priority level of the channel requested for transfer is kept lowest. (3) Maximum number of transfers: 65,536 times (64K times) (4) Data transfer size: Byte (8 bits), half-word (16 bits), word (32 bits) (5) Bus request system: Cycle steal mode Bus request signal is asserted for each DMA transfer cycle. Burst mode Bus request signal is asserted until all transfers of transfer cycles are complete. (6) DMA transfer request: Software request By setting the software transfer request bit inside DMAC, the CPU starts DMA transfer. External request DMA transfer is started by external request allocated to each channel. (7) Interrupt request: Interrupt request is generated to CPU after the end of DMA transfers for the set number of transfer cycles or after occurrence of error. Interrupt request signal is output separately for each channel. Interrupt request signal output can be masked for each channel. 16/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 External memory controller Controls access of externally connected devices such as ROM (FLASH), SRAM, SDRAM (EDO DRAM), IO devices, and internal FLASH memory. (1) ROM (FLASH) access function : 1 bank Supports 16-bit devices. Supports FLASH memory: Byte write (can be written only by IF equivalent to SRAM). In ML67Q4002/ML67Q4003, control internal FLASH access. Configurable access timing. (2) SRAM access function : 1 bank Supports 16-bit devices. Supports asynchronous SRAM Configurable access timing. (3) DRAM access function : 1 bank Supports 16-bit device Supports EDO/SDRAM : Simultaneous connections to EDO-DRAM and SDRAM cannot be made. Configurable access timing. (4) External IO access function : 2 banks Supports 8-bit/16-bit access : Independent configuration for each bank Each bank has two chip selects : XIOCS_N[3:0] Supports external wait input : XWAIT Access Timing configurable for each bank independently Power Management HALT, STANDBY, clock gear, clock control functions are supported as power save functions. (1) HALT mode HALT object CPU, internal RAM, AHB bus control HALT mode setting: Set by the system control register. Exit HALT mode due to: Reset, interrupt (2) STANDBY mode Stops the clock of entire LSI. STANDBY mode setting: Specified by the system control register. Exit STANDBY mode due to: Reset, external interrupt (other than EFIQ_N) (3) Clock gear This LSI has two clock systems, HCLK and CCLK. Configure HCLK and CCLK frequency. HCLK: CPU, bus control, synchronous serial interface, I2C. CCLK: Timers, PWM, UART, AD converter, etc. (4) Clock control by each function unit AD converter, PWM, Timers, DRAMC, DMAC, UART(FIFO), UART, Synchronous SIO, I2C. 17/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 BUILT-IN FLASH ROM PROGRAMMING The robust features of the flash permit simple and optimized programming as well as maintaining the flash-ROM. (1) Programming Method • Programming via JTAG interface • Programming using boot mode Boot mode of this LSI is used for downloading data to be written to the FLASH through the UART interface of the MCU from a host system. In boot mode, the program on the on-chip boot ROM downloads a flash writing application, that will handle the serial transfer and writing of internal flash, to internal RAM area of the MCU through the UART interface of the MCU. • Programming via user application running from external memory Internal flash can be programmed by executing a user flash programming application from external memory. (2) Single power source for Read/Program of FLASH: 3.0V to 3.6V (3) Programming units : 2 bytes (4) Selectable erasing size • Sector erase: 2Kbytes/sector • Block erase: 64Kbytes/block • Chip erase: All memory cell (5) Word program time: 30usec (6) Sector/block erase time: 25msec (7) Chip erase time: 100msec (8) Write protection • Block protect: top address 8Kwords can be protected • Chip protect: all words can be protected (9) Number of commands: 9 (10) Highly reliable read/program • Sector programming: 1000 times • Data hold period: 10 years 18/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 ABSOLUTE MAXIMUM RATINGS*1 Item Symbol Conditions Rating Digital power supply voltage (core) VDD_CORE –0.3 to +3.6 Digital power supply voltage (I/O) VDD_IO –0.3 to +4.6 Input voltage VI –0.3 to VDD_IO+0.3 Output voltage VO –0.3 to VDD_IO+0.3 Analog power supply voltage AVDD Analog reference voltage Input current *2 Output current 3 Ta = 25°C –0.3 to VDD_IO+0.3 –0.3 to AVDD +0.3 VAI –0.3 to VREF II –10 to +10 Power losses (LFBGA) PD Power losses (LQFP) Storage temperature TSTG mA –20 to +20 IO * V –0.3 to VDD_IO+0.3 and VREF Analog input voltage Output current GND = AGND = 0 V Unit –30 to +30 Ta = 85°C 680 per package 1000 — mW °C –50 to +150 Note 1. These are maximum ratings not for general operation. Exceeding these maximum ratings could cause damage or lead to permanent deterioration of the device. 2. All output pins except XA[15:0] 3. XA[15:0] OPERATING CONDITIONS (GND = 0 V) Item Symbol Digital power supply voltage (core) VDD_CORE Digital power supply voltage (I/O) VDD_IO Analog power supply voltage AVDD Analog reference voltage VREF Conditions Minimum Typical Maximum Unit 2.25 2.5 2.75 3.0 3.3 3.6 AVDD = VDD_IO 3.0 3.3 3.6 VREF = AVDD = VDD_IO 3.0 3.3 3.6 1 — 33.333 MHz –40 25 +85 °C VDD_IO ≥ VDD_CORE Operating frequency * fOP Ambient temperature Ta VDD_CORE = 2.25 to 2.75 VDD_IO = 3.0 to 3.6 — V Note Operating frequencies between 16 MHz and 33 MHz. Minimum of 2.56 MHz for external SDRAM. Minimum of 6.4 MHz for external EDO DRAM. Minimum of 2 MHz for analog-to-digital converter. 19/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD_CORE = 2.25 to 2.75V, VDD_IO = 3.0 to 3.6V, Ta = –40 to +85°C) Minimum Typical Maximum High level input voltage Item Symbol VIH Conditions VDD_IOx0.8 — VDD_IO+0.3 Low level input voltage VIL –0.3 — VDD_IOx0.2 — VT+ Schmitt input buffer threshold voltage VT− VHYS High level output voltage VOH Low level output voltage — 1.6 2.1 0.7 1.1 — 0.4 0.5 — IOH = –100 µA VDD–0.2 — — IOH = –4 mA 2.35 — — IOL = 100 µA — — 0.2 IOL = 4 mA — — 0.45 IOL = 6 mA — — 0.45 IIH/IIL VI = 0 V/VDD_IO –50 — 50 Input leak current *4 IIL VI = 0 V Pull-up resistance of 50 kΩ –200 –66 –10 5 II VI = AVDD / 0 V –5 — 5 Output leak current ILO VO = 0 V/VDD_IO –50 — 50 Input pin capacitance CI — — 6 — Output pin capacitance CO — — 9 — I/O pin capacitance CIO 1 Low level output voltage * VOL Low level output voltage *2 3 Input leak current * Input leak current * Analog reference power supply current IREF Current consumption (STANDBY) IDDS_CORE Current consumption 8 (HALT) * IDDH_CORE Current consumption (RUN) *9 IDD_CORE — — 10 — Analog-to-digital converter operative *6 — 320 650 Analog-to-digital converter stopped — 1 2 — 20 100 — 5 20 — 20 40 IDDS_IO IDDH_IO IDD_IO 7 Ta = 25°C * fOP = 33 MHz CL = 30 pF — 5 10 — 40 70 — 18 30 Unit V µA pF µA mA Notes 1. All output pins except XA[15:0] 2. XA[15:0] 3. All input pins except RESET_N 4. 5. 6. 7. 8. 9. RESET_N pin, with 50 kΩ pull-up resistance Analog input pins (AIN0 to AIN3) Analog-Digital Converter operation ratio is 20% VDD_IO or 0 V for input ports; no load for other pins DRAM controller blocks stopped by DRAME_N pin setting External ROM used 20/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 Analog-to-Digital Converter Characteristics (VDD_CORE = 2.50 V, VDD_IO = 3.3 V, Ta = 25°C) Item Symbol Conditions n — — — 10 Analog input source impedance — ±3 — — ±3 — — ±3 — Resolution Linearity error EL Differential linearity error ED Zero scale error EZS Full scale error Conversion time EFS tCONV Throughput Ri ≤ 1kΩ Minimum Typical Maximum Unit bit LSB — ±3 — — 5 — — µs — 10 — 200 kHz Notes: VDD_IO and AVDD should be supplied separately • Definition of Terms (1) Resolution: Minimum input analog value recognized. For 10-bit resolution, this is (VREF – Aground) ÷ 1024. (2) Linearity error: Difference between the theoretical and actual conversion characteristics. (Note that it does not include quantization error.) The theoretical conversion characteristic divides the voltage range between VREF and AGND into 1024 equal steps. (3) Differential linearity error: Difference between the theoretical and actual input voltage change producing a 1-bit change in the digital output anywhere within the conversion range. This is an indicator of conversion characteristic smoothness. The theoretical value is (VREF – Aground) ÷ 1024. (4) Zero scale error: Difference between the theoretical and actual conversion characteristics at the point where the digital output switches from “0x000” to “0x001.” (5) Full scale error: Difference between the theoretical and actual conversion characteristics at the point where the digital output switches from “0x3FE” to “0x3FF.” 21/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 22/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 REVISION HISTORY Document No. Date Page Previous Current Edition Edition Description PEDL674001-01 Jan.15, 2003 – – Preliminary edition 1 PEDL674001-02 Feb.17, 2003 3 3 Preliminary edition 2 Modified PIOB[4:5] assignment of bloc diagram FEDL674001-01 Dec. 15, 2003 – – Final edition 1 23/24 FEDL674001-01 OKI Semiconductor ML674001/67Q4002/67Q4003 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2003 Oki Electric Industry Co., Ltd. 24/24