GaAs MMIC 1.9 GHz Power Amplifier in High Power Plastic Package AP107-81 Features ■ PCS TDMA (1S136) ■ PCS CDMA (1S95) ■ Linear Power Up to 31 dBm (PEP) ■ 6 Volt Operation ■ Efficiency Greater Than 30% 1,2 ■ High Power 16 Lead SOIC Package Electrical Specifications at 25°C Characteristic Condition Min. Typ. Max. Unit Description Frequency The AP107-81 is a low cost MMIC power amplifier designed for the 1.85 to 1.91 GHz frequency band. It features 5 cell battery operation and operates with excellent linearity and high efficiency. The amplifier is designed to be stable over a temperature range of –30 to 100°C and over 3:1 VSWR loads. Output Power (PEP) PIN ≤ 2dBm (avg.) 31 dBm Efficiency POUT (PEP) = 31 dBm 30 35 % Gain (Small Signal) PIN = –20 dBm 27 30 33 dB Gain (Large Signal) POUT (PEP) = 31 dBm 25 28 31 dB Noise in the Receive Band POUT (PEP) = 31 dBm RX band = 1930-1990 MHz RX bandwidth = 30 KHz –100 –95 dBm Negative Bias Current POUT (PEP) = 31 dBm 6 mA Input VSWR PIN = –30 to +2 (Avg.) IM3@ Rated POUT POUT = 31 dBm (PEP) –26 dBc IM5@ Rated POUT POUT = 31 dBm (PEP) –35 dBc Harmonic Power POUT = 31 dBm (PEP) –30 –45 dBc dBc Modulation Channel Spacing = 30 KHz, 832 Channels, Pi/4 QPSK Absolute Maximum Ratings Characteristics Symbol Value Drain Voltage VDD 10 V Bias Voltage VSS –6 V Reference Voltage VREF 6V Power Input PIN 12 dBm Operating Temperature TOPT –30 to 100°C Storage Temperature TSTG –35 to 120°C 1.85 to 1.91 GHz Padj 2:1 2fo 3fo 30 KHz –30 dBc 60 KHz –50 dBc 90 KHz –55 dBc 50 Ohms Input Impedance Load Impedance (measured at pins 12 & 13) 9-j5.4 Alpha Industries, Inc. [781] 935-5150 • Fax [617] 824-4579 • Email [email protected] • www.alphaind.com Specifications subject to change without notice. 9/97 8 Ohms 1 GaAs MMIC 1.9 MHz Power Amplifier in High Power Plastic Package AP107-81 Performance Data at 25°C 45 15 29 40 20 35 25 Gain 27 30 26 25 PAE 25 20 PAE (%) 30 40 IM5 45 15 23 10 55 22 5 60 21 0 65 50 IM7 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 POUT (dBm) POUT (dBm) Figure 1. Gain, P.A.E. vs. Output Power Figure 2. Intermodulation Distortion vs. Output Power (VDD = 5.8 V) 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6.5 V 5.8 V POUT (dBm) 5.0 V -20 -18 -16 -14 -12-10 -8 -6 -4 -2 0 2 30.0 29.5 29.0 28.5 28.0 27.5 27.0 26.5 26.0 25.5 25.0 24.5 24.0 4 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 6 8 –30°C Room +85°C -20 -18 -16 -14 -12-10 -8 -6 -4 -2 0 2 PIN (dBm) PIN (dBm) Figure 3. POUT vs. PI N Over Drain Voltage Figure 4. POUT vs. PI N Over Temperature 6 8 200 1.85 GHz Ghz 1.91 GHz Idq 150 100 1.88 GHz 50 0 8 10 12 14 16 18 20 22 24 26 27 28 30 3.9 3.95 4.0 4.05 4.1 4.15 4.2 4.25 4.3 POUT (dBm) VREF (V) Figure 5. Gain vs. POUT Over Frequency Figure 6. Quiescent Current vs. Reference Voltage 1. Performance in Figures 1, 2, 3, 4 and 5 is with VREF set to 4.1 V through resistive voltage divider as shown in schematic. 2. Performance shown in Figures 1 and 2 is with a two-tone input signal at 1.88 GHz and 1.88001 GHz. 3. Performance in Figures 3, 4 and 7 is with a 1.88 GHz CW input signal. 4. For Figures 6 and 7, VREF was varied using a DC supply connected directly to the VREF pin. 2 4 250 Idq (mA) Gain (dB) IM3 35 24 POUT (dB) Gain (dB) 28 Distortion (dBc) 30 Alpha Industries, Inc. [781] 935-5150 • Fax [617] 824-4579 • Email [email protected] • www.alphaind.com Specifications subject to change without notice. 9/97 Gain (dB) GaAs MMIC 1.9 MHz Power Amplifier in High Power Plastic Package AP107-81 30.0 Output Matching Circuit 29.0 The output match for the AP107 is provided externally in order to improve performance, reduce cost and add flexibility. By making use of either ceramic surface mount components or a distributed microstrip network, a much lower loss match is achievable than could be obtained using integrated elements on GaAs. This lower loss results in better linearity and efficiency at rated output power for the amplifier. Also, by keeping these elements external to the GaAs IC, die size is smaller and the overall cost is thus reduced. This off-chip approach also permits the flexibility to tweak the amplifier for optimum performance at different powers, and/or frequencies. The board schematic demonstrates a distributed load matching network on FR4 substrate, which presents the optimum load match while also providing a path for DC bias to the output stage. 4.3 V 28.0 4.1 V 27.0 3.9 V 26.0 25.0 24.0 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT (dBm) Figure 7. Gain vs. POUT vs. Reference Voltage Power Amplifier Typical Configuration C28 1000pF 10 uF C21 C27 C12 1000pF Vdd 100pF C26 L3 12nH 1.8 nH L2 RFin 3.3 nH 50 ohm RF input C9 1000pF mline W=50 L=50 C29 C7 C8 8.2pF 100pF FR4 Substrate Parameters Er=4.5 H=14 T=0.7 Rho=1.2 mline mline W=50 L=230 W=26 L=70 W=50 L=100 C4 C5 100pF 8.2pF mline L1 C6 1000pF AP107-81 VDD2 1 VG2 15 VREF 14 VDD1 RFOUT GND RFOUT RFIN 11 VG1 VG3 VDBC VSS W=50 L=410 C2 C1 100pF 8.2pF mline C3 1000pF 8.2pF W=50 L=130 Power Supply Voltage + 5.8V C11 C10 100pF 8.2pF C22 15pF RFout 50 ohm RF output mstub 1.2pF C16 C17 100pF C18 8.2pF 100pF C19 100pF R1 R2 3.3k 8.2k C13 8.2pF C14 100pF C15 1000pF C30 10uF C20 1000pF + Vss -4V Negative Supply Voltage - Bias Controller Circuit Standby Mode An on-chip bias controller eliminates the need to individually adjust the gate bias voltages. This circuit uses +5.8 V and an externally supplied negative voltage (–4 Volts) to set the gate voltages on each stage for the proper bias current. The voltage on Pin 3 (Vreg), which can be adjusted using the off-chip resistors R1 and R2, can be used to vary the quiescent current thus providing some gain control and also allowing higher efficiency operation at lower output power levels. However, to obtain the specified linearity at rated power, the amplifier should be biased with 150-200 mA of quiescent current. The power amplifier should be turned off whenever possible to reduce overall power consumption. The AP107 can be turned off in a number of ways. The simplest method is to switch the bias controller voltage (Pin 8) open, which has the effect of setting the gate voltages to approximately VSS (–4 V). The bias current of the amplifier in this condition will drop to less than 1 mA. By adding PMOS switches to the drain lines, bias-off currents of the order of a few µA can be obtained. Alpha Industries, Inc. [781] 935-5150 • Fax [617] 824-4579 • Email [email protected] • www.alphaind.com Specifications subject to change without notice. 9/97 3 GaAs MMIC 1.9 MHz Power Amplifier in High Power Plastic Package Pin Out Assignments AP107-81 Pin Configuration Pin 2: VG2 Second stage gate voltage tap. Should be RF bypassed. Terminal Symbol Function 1 N/C Not Connected 2 VG2 Gate Voltage 2 3 VREF Reference Voltage 4 VDD1 Drain Voltage 1 5 GND Ground 6 RFIN RF Input 7 VG1 Gate Voltage 1 8 VDBC Positive Bias Controller Supply Voltage 9 VSS Negative Bias Controller Supply Voltage 10 VG3 Gate Voltage 3 11 N/C Not Connected 12 RFOUT RF Output/Drain Voltage 3 Pin 7: VG1 First stage gate voltage tap. Requires good RF bypassing. 13 RFOUT RF Output/Drain Voltage 3 14 N/C Not Connected Pin 8: VDBC Bias controller supply voltage. Connect to +5.8 V nominal supply voltage. 15 N/C Not Connected 16 VDD2 Drain Voltage 2 Pin 3: VREF Sets quiescent current of amplifier. Nominal value of ~4.1 V can be set, by voltage dividing from VDBC (5.8 V) using resistors R1 and R2 as shown in the schematic. Pin 4: VDD1 Drain of stage 1. Requires matching inductor, good RF bypassing and the +5.8 V nominal supply voltage. Pin 5: GND DC and RF ground. Pin 6: RF IN 50Ω RF input. Series inductor on input line improves input match. Pin 9: VSS Negative voltage for bias controller circuit. Nominally –4 V. Outline Drawing SOIC-16 Pin 10: VG3 Third stage gate voltage tap. Requires good RF bypassing. Pin 12, 13: RF OUT/VDD3 RF output and bias feed for third stage drain. Output matching is required to transform the optimum load impedance to 50Ω. The circuit must also provide a path for the +5.8 V nominal DC bias and have good RF bypassing. 0.050 BSC 16 0.244 MAX. 0.228 MIN. 0.158 MAX. 0.150 MIN. 1 4 VDD2 VG2 NC VREF NC VDD1 RF Out GND RF Out RF In NC VG1 VG3 VDBC VSS 8 8 1 0.394 MAX. 0.386 MIN. 0.004 Pin Out TOP VIEW HEAT SLUG 0.066 X 0.140 LOCATED ON CENTER-LINE OF THE PACKAGE Pin 16: VDD2 Second stage drain voltage. Requires matching inductor, good RF bypassing and connection to the +5.8 V nominal supply voltage. N/C 9 16 0.010 TYP. 9 BOTTOM VIEW Alpha Industries, Inc. [781] 935-5150 • Fax [617] 824-4579 • Email [email protected] • www.alphaind.com Specifications subject to change without notice. 9/97