Features • EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1- and • • • • • • • • • • • 2,097,152 x 1-bit Serial Memories Designed to Store Configuration Programs for Altera FLEX ® and APEX FPGAs (Device Selection Guide Included) Available as a 3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) Version In-System Programmable (ISP) via 2-wire Bus Simple Interface to SRAM FPGAs Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX ®, APEX™ Devices, Lucent ORCA® FPGAs, Xilinx XC3000™, XC4000™, XC5200™, Spartan®, Virtex® FPGAs, Motorola MPA1000 FPGAs Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Very Low-power CMOS EEPROM Process Programmable Reset Polarity Available 8-lead PDIP, 20-lead PLCC and 32-lead TQFP Packages (Pin Compatible Across Product Family) Emulation of Atmel’s AT24CXXX Serial EEPROMs Low-power Standby Mode High-reliability – Endurance: 100,000 Write Cycles – Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for Commercial Parts (at 70°C) Description The AT17A series FPGA configuration EEPROMs (Configurators) provide an easy-touse, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17A series device is packaged in the 8-lead PDIP (1), 20-lead PLCC and 32-lead TQFP, see Table 1. The AT17A series configurator uses a simple serial-access procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes.These devices also support a write-protection mechanism within its programming mode. Note: 1. The 8-lead LAP, PDIP and SOIC packages for the AT17LV65A/128A/256A do not have an A label. However, the 8-lead packages are pin compatible with the 8-lead package of Altera’s EEPROMs, refer to the AT17LV65/128/256/512/010/002/040 datasheet available on the Atmel web site for more information. The AT17A series configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. FPGA Configuration EEPROM Memory AT17LV65A AT17LV128A AT17LV256A AT17LV512A AT17LV010A AT17LV002A 3.3V and 5V System Support Table 1. AT17A Series Packages AT17LV65A/ AT17LV128A/ AT17LV256A AT17LV512A AT17LV010A AT17LV002A 8-lead PDIP Yes Yes Yes – 20-lead PLCC Yes Yes Yes Yes 32-lead TQFP – – Yes Yes Package Rev. 2322D–CNFG–07/02 1 Pin Configuration 8-lead PDIP DATA DCLK (1) (WP ) RESET/OE nCS 1 2 3 4 VCC SER_EN (A2) nCASC GND 8 7 6 5 18 17 16 15 14 9 10 11 12 13 4 5 6 7 8 SER_EN NC NC NC (READY(2)) NC nCS GND NC (A2) nCASC NC DCLK WP1(2) NC NC (WP(1)) RESET/OE 3 2 1 20 19 NC DATA NC VCC NC 20-lead PLCC 32 31 30 29 28 27 26 25 NC DATA NC NC NC VCC NC NC 32-lead TQFP 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 NC SER_EN NC NC READY NC NC NC NC nCS NC GND NC NC (A2) nCASC NC 9 10 11 12 13 14 15 16 NC DCLK NC (3) (WP1 ) NC NC NC RESET/OE NC Notes: 2 1. This pin is only available on AT17LV65A/128A/256A devices. 2. This pin is only available on AT17LV512A/010A/002A devices. 3. This pin is only available on AT17LV010A/002A devices. AT17LV65A/128A/256A/512A/002A 2322D–CNFG–07/02 AT17LV65A/128A/256A/512A/002A Block Diagram SER_EN WP1(2) OSCILLATOR CONTROLL (3) OSCILLATOR POWER ON RESET (2) DCLK READY Notes: RESET/OE (1) (WP ) nCS nCASC 1. This pin is only available on AT17LV65A/128A/256A devices. 2. This pin is only available on AT17LV512A/010A/002A devices. 3 2322D–CNFG–07/02 Device Description The control signals for the configuration EEPROM (nCS, RESET/OE and DCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external controller. The configuration EEPROM’s RESET/OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address counter and the oscillator. When RESET/OE is driven Low, the configuration EEPROM resets its address counter and tristates its DATA pin. The nCS pin also controls the output of the AT17A series configurator. If nCS is held High after the RESET/OE pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven subsequently Low, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS. When the configurator has driven out all of its data and nCASC is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document will describe RESET/OE. 4 AT17LV65A/128A/256A/512A/002A 2322D–CNFG–07/02 AT17LV65A/128A/256A/512A/002A Pin Description AT17LV65A/ AT17LV128A/ AT17LV256A AT17LV512A/ AT17LV010A AT17LV002A Name I/O 20 PLCC 8 PDIP 20 PLCC 32 TQFP 20 PLCC 32 TQFP DATA I/O 2 1 2 31 2 31 DCLK I 4 2 4 2 4 2 WP1 I – – 5 4 5 4 RESET/OE I 8 3 8 7 8 7 nCS I 9 4 9 10 9 10 10 5 10 12 10 12 12 6 12 15 12 15 GND nCASC O A2 I READY O – – 15 20 15 20 SER_EN I 18 7 18 23 18 23 20 8 20 27 20 27 VCC DATA Three-state DATA output for configuration. Open-collector bi-directional pin for programming. DCLK Clock output or clock input. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The counter is incremented only if the RESET/OE input is held High, the nCS input is held Low, and all configuration data has not been transferred to the target device (otherwise, as the master device, the DCLK pin drives Low). WP1 WRITE PROTECT (1). This pin is used to protect portions of memory during programming, and it is disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. This pin is only available on AT17LV512A/010A/002A devices. RESET/OE Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low logic level resets the address counter. A High logic level (with nCS Low) enables DATA and permits the address counter to count. In the mode, if this pin is Low (reset), the internal oscillator becomes inactive and DCLK drives Low. The logic polarity of this input is programmable and must be programmed active High (RESET active Low) by the user during programming for Altera applications. WP Write protect (WP) input (when nCS is Low) during programming only (SER_EN Low). When WP is Low, the entire memory can be written. When WP is enabled (High), the lowest block of th e memory cann ot be written . This p in is o nly ava ila ble o n AT17LV65A/128A/256A devices. 5 2322D–CNFG–07/02 nCS Chip Select input (active Low). A Low input (with OE High) allows DCLK to increment the address counter and enables DATA to drive out. If the AT17A series is reset with nCS Low, the device initializes as the first (and master) device in a daisy-chain. If the AT17A series is reset with nCS High, the device initializes as a subsequent AT17A series device in the chain. GND Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended. nCASC Cascade Select Output (active Low). This output goes Low when the address counter has reached its maximum value. In a daisy-chain of AT17A series devices, the nCASC pin of one device is usually connected to the nCS input pin of the next device in the chain, which permits DCLK from the master configurator to clock data from a subsequent AT17A series device in the chain. A2 Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor. READY Open collector reset state indicator. Driven Low during power-on reset cycle, released when power-up is complete. (recommended 4.7 kΩ pull-up on this pin if used). SER_EN Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. VCC 3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin. 6 AT17LV65A/128A/256A/512A/002A 2322D–CNFG–07/02 AT17LV65A/128A/256A/512A/002A FPGA Master Serial Mode Summary The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17A Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode. This document discusses the Altera FLEX FPGA device interfaces Control of Configuration Cascading Serial Configuration EEPROMs Most connections between the FPGA device and the AT17A Serial EEPROM are simple and self-explanatory. • The DATA output of the AT17A series configurator drives DIN of the FPGA devices. • The master FPGA DCLK output or external clock source drives the DCLK input of the AT17A series configurator. • The nCASC output of any AT17A series configurator drives the nCS input of the next configurator in a cascaded chain of EEPROMs. • SER_EN must be connected to VCC (except during ISP). For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the next clock signal to the configurator asserts its nCASC output low and disables its DATA line driver. The second configurator recognizes the low level on its nCS input and enables its DATA output. After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE on each configurator is driven to a Low level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to a High level. AT17A Series Reset Polarity The AT17A series configurator allows the user to program the polarity of the RESET/OE pin as either RESET/OE or RESET/OE. This feature is supported by industry-standard programmer algorithms. Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. Standby Mode The AT17LV65A/128A/256A enters a low-power standby mode whenever nCS is asserted High. In this mode, the configurator consumes less than 50 µA of current at 3.3V (100 µA for the AT17LV512A/010A/002A). The output remains in a high-impedance state regardless of the state of the RESET/OE input. 7 2322D–CNFG–07/02 Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85 °C *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Storage Temperature ..................................... -65 °C to +150°C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC ) .........................................-0.5V to +7.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.)............. 260°C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V Operating Conditions 3.3V Symbol Description Min Max Min Max Units Commercial Supply voltage relative to GND -0°C to +70°C 3.0 3.6 4.75 5.25 V Industrial Supply voltage relative to GND -40°C to +85°C 3.0 3.6 4.5 5.5 V VCC 8 5V AT17LV65A/128A/256A/512A/002A 2322D–CNFG–07/02 AT17LV65A/128A/256A/512A/002A DC Characteristics VCC = 3.3V ± 10% AT17LV65A/ AT17LV128A/ AT17LV256A AT17LV512A/ AT17LV010A Min Max Min Max Min Max Units AT17LV002A Symbol Description VIH High-level Input Voltage 2.0 VCC 2.0 V CC 2.0 V CC V VIL Low-level Input Voltage 0 0.8 0 0.8 0 0.8 V VOH High-level Output Voltage (IOH = -2.5 mA) VOL Low-level Output Voltage (IOL = +3 mA) VOH High-level Output Voltage (IOH = -2 mA) VOL Low-level Output Voltage (IOL = +3 mA) ICCA Supply Current, Active Mode IL Input or Output Leakage Current (VIN = VCC or GND) ICCS Supply Current, Standby Mode 2.4 2.4 2.4 V Commercial 0.4 2.4 0.4 2.4 0.4 2.4 V V Industrial -10 0.4 0.4 0.4 V 5 5 5 mA 10 µA 10 -10 10 -10 Commercial 50 100 150 µA Industrial 100 100 150 µA DC Characteristics VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial AT17LV65A/ AT17LV128A/ AT17LV256A AT17LV512A/ AT17LV010A Min Max Min Max Min Max Units AT17LV002A Symbol Description VIH High-level Input Voltage 2.0 VCC 2.0 V CC 2.0 V CC V VIL Low-level Input Voltage 0 0.8 0 0.8 0 0.8 V VOH High-level Output Voltage (IOH = -2.5 mA) VOL Low-level Output Voltage (IOL = +3 mA) VOH High-level Output Voltage (IOH = -2 mA) VOL Low-level Output Voltage (IOL = +3 mA) ICCA Supply Current, Active Mode IL Input or Output Leakage Current (VIN = VCC or GND) ICCS1 Supply Current, Standby Mode 3.7 3.86 3.86 V Commercial 0.32 3.6 0.32 3.76 0.32 3.76 V V Industrial -10 0.37 0.37 0.37 V 10 10 10 mA 10 µA 10 -10 10 -10 Commercial 75 200 350 µA Industrial 150 200 350 µA 9 2322D–CNFG–07/02 AC Characteristics nCS TSCE TSCE THCE RESET/OE TLC THOE THC DCLK TOE TCAC TOH TDF TCE DATA TOH AC Characteristics when Cascading RESET/OE nCS DCLK TCDF DATA LAST BIT TOCK FIRST BIT TOCE TOOE nCASL TOCE 10 AT17LV65A/128A/256A/512A/002A 2322D–CNFG–07/02 AT17LV65A/128A/256A/512A/002A AC Characteristics VCC = 3.3V ± 10% AT17LV65A/128A/256A Commercial Symbol Description Min Max AT17LV512A/010A/002A Industrial Min Max Units 50 55 ns 60 55 60 ns 80 55 60 ns TOE OE to Data Delay 50 55 TCE (1) CE to Data Delay 60 CLK to Data Delay 75 TCAC 0 Min Data Hold from CE, OE, or CLK TDF(2) CE or OE to Data Float Delay TLC CLK Low Time 25 25 25 25 ns THC CLK High Time 25 25 25 25 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 35 60 30 35 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 0 0 ns THOE OE High Time (guarantees counter is reset) 25 25 25 25 ns Maximum Input Clock Frequency 10 10 15 10 MHz FMAX 0 Max TOH Notes: 0 Min Industrial Max (1) (1) Commercial 55 0 55 ns 50 50 ns 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. AC Characteristics when Cascading VCC = 3.3V ± 10% AT17LV65A/128A/256A Commercial Description TCDF(2) CLK to Data Float Delay 60 60 TOCK(1) CLK to CEO Delay 55 TOCE(1) CE to CEO Delay TOOE(1) RESET/OE to CEO Delay FMAX Maximum Input Clock Frequency 8 Max Industrial Symbol Notes: Min AT17LV512A/010A/002A Min Min Units 50 50 ns 60 50 55 ns 55 60 35 40 ns 40 45 35 35 ns 12.5 Max Industrial Max 8 Max Commercial Min 10 MHz 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. 11 2322D–CNFG–07/02 AC Characteristics VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial AT17LV65A/128A/256A Commercial Symbol Description Min Max AT17LV512A/010A/002A Industrial Min Max Units 30 35 ns 45 45 45 ns 55 50 50 ns TOE OE to Data Delay 30 35 TCE (1) CE to Data Delay 45 CLK to Data Delay 50 TCAC Min Max Industrial Max (1) (1) Commercial Min TOH Data Hold from CE, OE, or CLK TDF(2) CE or OE to Data Float Delay TLC CLK Low Time 20 20 20 20 ns THC CLK High Time 20 20 20 20 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 35 40 20 25 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 0 0 ns THOE OE High Time (guarantees counter is reset) 20 20 20 20 ns FMAX Maximum Input Clock Frequency 12.5 12.5 15 15 MHz Notes: 0 0 0 50 0 50 ns 50 50 ns 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. AC Characteristics when Cascading VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial AT17LV65A/128A/256A Commercial Symbol Description TCDF(2) Min Max AT17LV512A/010A/002A Industrial Min Max Commercial Min Max Industrial Min Max Units CLK to Data Float Delay 50 50 50 50 ns TOCK (1) CLK to CEO Delay 35 40 35 40 ns TOCE (1) CE to CEO Delay 35 35 35 35 ns TOOE(1) RESET/OE to CEO Delay 30 35 30 30 ns FMAX Maximum Input Clock Frequency Notes: 12 10 10 12.5 12.5 MHz 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. AT17LV65A/128A/256A/512A/002A 2322D–CNFG–07/02 AT17LV65A/128A/256A/512A/002A Thermal Resistance Coefficients(1) AT17LV65A/ AT17LV128A/ AT17LV256A Package Type 8P3 20J Plastic Dual Inline Package (PDIP) Plastic Leaded Chip Carrier (PLCC) 32A Thin Plastic Quad Flat Package (TQFP) 44J Plastic Leaded Chip Carrier (PLCC) Notes: θJC [°C/W] AT17LV512A/ AT17LV010A AT17LV002A 37 θJA [°C/W] (2) 107 θJC [°C/W] 35 35 35 θJA [°C/W](2) 90 90 90 θJC [°C/W] – – 15 θJA [°C/W](2) – – 50 θJC [°C/W] θJA [°C/W](2) 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site. 2. Airflow = 0 ft/min. 13 2322D–CNFG–07/02 Figure 1. Ordering Code(1) AT17LV65A-10PC Note: Voltage Size (Bits) Special Pinouts Package Temperature 3.3V Nominal to 65 = 65K A = Altera P = 8P3 C = Commercial 5V Nominal 128 = 128K Blank = Xilinx/Atmel/ Other J = 20J I = Industrial 256 = 256K A = 32A 512 = 512K 010 = 1M 002 = 2M 1. The 8-lead LAP and SOIC packages for the AT17LV65A/128A/256A do not have an A label. However, the 8-lead packages are pin compatible with the 8-lead package of Altera’s EEPROMs, refer to the AT17LV65/128/256/512/010/002/040 datasheet available on the Atmel web site for more information. Package Type 14 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20J 20-lead, Plastic J-leaded Chip Carrier (PLCC) 32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) AT17LV65A/128A/256A/512A/002A 2322D–CNFG–07/02 AT17LV65A/128A/256A/512A/002A Ordering Information(1) Memory Size (2)(7) 64-Kbit 128-Kbit(7) 256-Kbit(3)(7) 512-Kbit(4)(7) 1-Mbit(5)(7) 2-Mbit(6)(7) Notes: Ordering Code Package Operation Range AT17LV65A-10JC 20J Commercial (0°C to 70°C) AT17LV65A-10JI 20J Industrial (-40°C to 85°C) AT17LV128A-10JC 20J Commercial (0°C to 70°C) AT17LV128A-10JI 20J Industrial (-40°C to 85°C) AT17LV256A-10JC 20J Commercial (0°C to 70°C) AT17LV256A-10JI 20J Industrial (-40°C to 85°C) AT17LV512A-10PC AT17LV512A-10JC 8P3 20J Commercial (0°C to 70°C) AT17LV512A-10PI AT17LV512A-10JI 8P3 20J Industrial (-40°C to 85°C) AT17LV010A-10PC AT17LV010A-10JC AT17LV010A-10QC 8P3 20J 32A Commercial (0°C to 70°C) AT17LV010A-10PI AT17LV010A-10JI AT17LV010A-10QI 8P3 20J 32A Industrial (-40°C to 85°C) AT17LV002A-10JC AT17LV002A-10QC 20J 32A Commercial (0°C to 70°C) AT17LV002A-10JI AT17LV002A-10QI 20J 32A Industrial (-40°C to 85°C) 1. Currently, there are two types of low-density configurators. The new version will be identified by a “B” after the datacode. The “B” version is fully backward-compatible with the original devices so existing customers will not be affected. The new parts no longer require a MUX for ISP. See programming specification for more details. 2. Use 64-Kbit density parts to replace Altera EPC1064. 3. Use 256-Kbit density parts to replace Altera EPC1213. 4. Use 512-Kbit density parts to replace Altera EPC1441. 5. Use 1-Mbit density parts to replace Altera EPC1 6. Use 2-Mbit density parts to replace Altera EPC2. Atmel AT17LV002A devices do not support JTAG programming; Atmel AT17LV002A devices use a 2-wire serial interface for in-system programming. 7. For operating voltage of 5V ±10%, please refer to the 5V ±10% AC and DC Characteristics. 15 2322D–CNFG–07/02 Packaging Information 8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A MIN NOM A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 SYMBOL A b2 L b3 b 4 PLCS Side View Notes: NOTE 0.210 0.100 BSC eA 0.300 BSC 0.115 2 3 3 e L MAX 0.130 4 0.150 2 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 R 16 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. REV. 8P3 B AT17LV65A/128A/256A/512A/002A 2322D–CNFG–07/02 AT17LV65A/128A/256A/512A/002A 20J – PLCC PIN NO. 1 1.14(0.045) X 45˚ 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER e E1 E D2/E2 B1 B A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 9.779 – 10.033 D1 8.890 – 9.042 E 9.779 – 10.033 E1 8.890 – 9.042 D2/E2 7.366 – 8.382 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 20J B 17 2322D–CNFG–07/02 32A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 8.75 9.00 9.25 D1 6.90 7.00 7.10 E 8.75 9.00 9.25 E1 6.90 7.00 7.10 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e NOTE Note 2 Note 2 0.80 TYP 10/5/2001 R 18 2325 Orchard Parkway San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 32A B AT17LV65A/128A/256A/512A/002A 2322D–CNFG–07/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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