ETC AT17C65-10NI

Features
• EE Programmable 65,536 x 1-, 131,072 x 1-, and 262,144 x 1-bit Serial Memories
•
•
•
•
•
•
•
•
•
•
Designed to Store Configuration Programs for Field Programmable Gate
Arrays (FPGAs)
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX ®, APEX™
Devices, Lucent ORCA® FPGAs, Xilinx XC3000™, XC4000™, XC5200™, Spartan®,
Virtex™ FPGAs, Motorola MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 8-lead PDIP, 8-lead SOIC and 20-lead PLCC Packages (Pin Compatible
Across Product Family)
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Available in 3.3V ± 10% LV and 5V ± 5% C Versions
Low-power Standby Mode
Description
The AT17C65/128/256 and AT17LV65/128/256 (low-density AT17 Series) FPGA
configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The low-density AT17 Series is
packaged in the 8-lead LAP, the 8-lead PDIP, the 8-lead SOIC and the popular 20-lead
PLCC. The AT17 Series uses a simple serial-access procedure to configure one or
more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes. These devices also support a write-protection mechanism
within its programming mode.
The AT17 Series Configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
FPGA
Configuration
EEPROM
Memory
64-kilobit, 128-kilobit
and 256-kilobit
AT17C65
AT17LV65
AT17C128
AT17LV128
AT17C256
AT17LV256
Rev. 1636E––CONF–03/02
1
Pin Configurations
8-lead LAP
8
7
6
5
VCC
SER_EN
CEO (A2)
GND
DATA
CLK
(WP) RESET/OE
CE
1
2
3
4
VCC
SER_EN
CEO (A2)
GND
20-lead PLCC
8
7
6
5
VCC
SER_EN
CEO (A2)
GND
CLK
NC
(WP) RESET/OE
NC
CE
4
5
6
7
8
18
17
16
15
14
NC
SER_EN
NC
NC
CEO (A2)
NC
GND
NC
NC
NC
DATA
CLK
(WP) RESET/OE
CE
8
7
6
5
NC
DATA
NC
VCC
NC
8-lead SOIC
1
2
3
4
3
2
1
20
19
1
2
3
4
9
10
11
12
13
DATA
CLK
RESET/OE
CE
8-lead PDIP
2
AT17C/LV65/128/256
1636E–CONF–03/02
AT17C/LV65/128/256
Block Diagram
POWER ON
RESET
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17 Series Configurator. If CE is held High after the
RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated.
When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET/OE.
3
1636E–CONF–03/02
-+
Pin Description
8
DIP/
LAP/
SOIC
Pin
20
PLCC
Pin
Name
I/O
Description
1
2
DATA
I/O
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
2
4
CLK
I
Clock input. Used to increment the internal address and bit counter for reading and
programming.
3
6
RESET/OE
I
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE Low)
enables the data output driver. The logic polarity of this input is programmable as either
RESET/OE or RESET/OE. For most applications, RESET should be programmed active
Low. This document describes the pin as RESET/OE.
WP(1)
I
Write protect (WP) input (when CE is Low) during programming only (SER_EN Low).
When WP is Low, the entire memory can be written. When WP is enabled (High), the
lowest block of the memory cannot be written.
I
Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment
the address counter and enables the data output driver. A High level on CE disables
both the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the 2-wire Serial Programming
mode ( SER_EN Low).
4
8
CE
5
10
GND
6
14
CEO
O
Chip Enable Output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17 Series devices, the CEO pin of one
device must be connected to the CE input of the next device in the chain. It will stay Low
as long as CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter,
CEO will stay High until the entire EEPROM is read again.
A2
I
Device selection input, A2. This is used to enable (or select) the device during
programming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
I
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN
should be tied to VCC.
7
17
SER_EN
8
20
VCC
Note:
4
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
+3.3V/+5V power supply pin.
1. This pin is not available for the LAP package.
AT17C/LV65/128/256
1636E–CONF–03/02
AT17C/LV65/128/256
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master mode, the FPGA
automatically loads the configuration program from an external memory. The AT17
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as
well as Xilinx applications.
Control of
Configuration
Cascading Serial
Configuration
EEPROMs
Most connections between the FPGA device and the AT17 Serial EEPROM are simple
and self-explanatory.
•
The DATA output of the AT17 Series Configurator drives DIN of the FPGA devices.
•
The master FPGA CCLK output drives the CLK input of the AT17 Series
Configurator.
•
The CEO output of any AT17 Series Configurator drives the CE input of the next
Configurator in a cascade chain of EEPROMs.
•
SER_EN must be connected to VCC (except during ISP).
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator
asserts its CEO output low and disables its DATA line driver. The second configurator
recognizes the low level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are
reset if the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input
can be tied to its inactive (High) level.
AT17 Series Reset
Polarity
The AT17 Series Configurator allows the user to program the reset polarity as either
RESET/OE or RESET/OE. This feature is supported by industry-standard programmer
algorithms.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the 2-wire serial bus. The programming is done at VCC supply only.
Programming super voltages are generated inside the chip. The AT17C parts are
read/write at 5V nominal. The AT17LV parts are read/write at 3.3V nominal.
Standby Mode
The AT17C/LV65/128/256 enters a low-power standby mode whenever CE is asserted
High. In this mode, the configurator consumes less than 75 µA of current at 5.0V. The
output remains in a high-impedance state regardless of the state of the OE input.
5
1636E–CONF–03/02
Example Circuits
Figure 1. AT17 Series Device for Programming PSLI Devices
AT17 Series Device
AT40K/AT40KAL/AT94K
RESET
RESET
M2
M1
M0
VCC
SER_EN
DATA
CLK
CE
(2)
(1)
RESET/OE READY
DATA0
CCLK
CON
INIT
GND
Notes:
1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
The FPGA CON/DONE output drives the CE input of the AT17 Series Configurator, while the RESET/OE input is driven by
the FPGA INIT pin. This connection works under all normal circumstances, even when the user aborts the configuration
before CON/DONE has gone High. A Low level on the RESET/OE input, during FPGA reset, clears the configurator’s internal address pointer so that the reconfiguration starts at the beginning.
Figure 2. Drop-In Replacement of XC17/ATT17 PROMs for Xilinx/Lucent FPGA Applications
VCC
4.7 kW
XILINX FPGA
PROGRAM
PROGRAM
M2
M1
M0
DIN
CCLK
DONE(3)
INIT
AT17 Series Device
VCC
SER_EN
DATA
CLK
CE
(2)
RESET/OE(1) READY
GND
Notes:
6
1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
3. An internal pull-up resistor is enabled here for DONE.
AT17C/LV65/128/256
1636E–CONF–03/02
AT17C/LV65/128/256
For details of ISP, please refer to the “Programming Specification for Atmel's AT17 and AT17A Series FPGA Configuration
EEPROMs”, available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0437.pdf.
Figure 3. In-System Programming of AT17 Series for PSLI Applications
VCC VCC
4.7 kW
4.7 kW
DATA 1
SCLK 3
2
5
6
7
8
9
10
4
VCC
GND
AT17 Series Device
AT40K/AT40KAL/AT94K
RESET
RESET
M2
M1
M0
DATA0
CCLK
CON
INIT
SER_EN
SER_EN
DATA
CLK
CE
(2)
RESET/OE(1) READY
GND
Notes:
1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
Figure 4. In-System Programming of AT17 Series for Xilinx/Lucent FPGA Applications
VCC VCC
4.7 kW
DATA 1
SCLK 3
2
5
6
7
8
9
10
VCC
VCC
4.7 kW
4
VCC
4.7 kW
XILINX FPGA
PROGRAM
PROGRAM
4.7 kW
M2
M1
M0
DIN
CCLK
DONE(3)
INIT
AT17 Series Device
GND
SER_EN
SER_EN
DATA
CLK
CE
(1)
READY(2)
RESET/OE
GND
Notes:
1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
3. An internal pull-up resistor is enabled here for DONE.
7
1636E–CONF–03/02
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125 °C
*NOTICE:
Storage Temperature ..................................... -65 °C to +150°C
Voltage on Any Pin
with Respect to Ground ..............................-0.1V to VCC +0.5V
Supply Voltage (VCC ) .........................................-0.5V to +7.0V
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods of time may affect device reliability.
Maximum Soldering Temp. (10 sec. @ 1/16 in.)............. 260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
Operating Conditions
AT17CXXX
Symbol
VCC
8
Description
AT17LVXXX
Min
Max
Min
Max
Units
Commercial
Supply voltage relative to GND
-0°C to +70°C
4.75
5.25
3.0
3.6
V
Industrial
Supply voltage relative to GND
-40°C to +85°C
4.5
5.5
3.0
3.6
V
Military
Supply voltage relative to GND
-55°C to +125°C
4.5
5.5
3.0
3.6
V
AT17C/LV65/128/256
1636E–CONF–03/02
AT17C/LV65/128/256
DC Characteristics
VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial/Military
Symbol
Description
Min
Max
Units
VIH
High-level Input Voltage
2.0
VCC
V
VIL
Low-level Input Voltage
0
0.8
V
VOH
High-level Output Voltage (IOH = -4 mA)
VOL
Low-level Output Voltage (IOL = +4 mA)
VOH
High-level Output Voltage (IOH = -4 mA)
VOL
Low-level Output Voltage (IOL = +4 mA)
VOH
High-level Output Voltage (IOH = -4 mA)
VOL
Low-level Output Voltage (IOL = +4 mA)
0.4
V
ICCA
Supply Current, Active Mode
10
mA
IL
Input or Output Leakage Current (VIN = VCC or GND)
10
µA
Commercial
75
µA
ICCS
Supply Current, Standby Mode
Industrial/Military
150
µA
3.7
V
Commercial
0.32
3.6
V
V
Industrial
0.37
3.5
V
V
Military
-10
DC Characteristics
VCC = 3.3V ± 10%
Symbol
Description
Min
Max
Units
VIH
High-level Input Voltage
2.0
VCC
V
VIL
Low-level Input Voltage
0
0.8
V
VOH
High-level Output Voltage (IOH = -2.5 mA)
VOL
Low-level Output Voltage (IOL = +3 mA)
VOH
High-level Output Voltage (IOH = -2 mA)
VOL
Low-level Output Voltage (IOL = +3 mA)
VOH
High-level Output Voltage (IOH = -2 mA)
VOL
Low-level Output Voltage (IOL = +2.5 mA)
ICCA
Supply Current, Active Mode
IL
Input or Output Leakage Current (VIN = VCC or GND)
ICCS
Supply Current, Standby Mode
2.4
V
Commercial
0.4
2.4
V
V
Industrial
0.4
2.4
V
V
Military
0.4
V
5
mA
10
µA
Commercial
50
µA
Industrial/Military
100
µA
-10
9
1636E–CONF–03/02
AC Characteristics
CE
TSCE
TSCE
THCE
RESET/OE
TLC
THOE
THC
CLK
TOE
TOH
TCAC
TDF
TCE
DATA
TOH
AC Characteristics when Cascading
RESET/OE
CE
CLK
TCDF
DATA
FIRST BIT
LAST BIT
TOCK
TOCE
TOOE
CEO
TOCE
10
AT17C/LV65/128/256
1636E–CONF–03/02
AT17C/LV65/128/256
AC Characteristics for AT17C65/128/256
VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial/Military
Commercial
Symbol
Description
TOE(2)
OE to Data Delay
TCE(2)
TCAC
(2)
TOH
TDF
Max
Units
30
35
ns
CE to Data Delay
45
45
ns
CLK to Data Delay
50
55
ns
Data Hold from CE, OE, or CLK
(3)
Min
Max
Industrial/Military(1)
0
CE or OE to Data Float Delay
Min
0
50
ns
50
ns
TLC
CLK Low Time
20
20
ns
THC
CLK High Time
20
20
ns
TSCE
CE Setup Time to CLK (to guarantee proper counting)
35
40
ns
THCE
CE Hold Time from CLK (to guarantee proper counting)
0
0
ns
THOE
OE High Time (guarantees counter is reset)
20
20
ns
FMAX
Maximum Input Clock Frequency
12.5
12.5
MHz
Notes:
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
AC Characteristics for AT17C65/128/256 when Cascading
VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial/Military
Commercial
Symbol
Max
Units
50
50
ns
CLK to CEO Delay
35
40
ns
TOCE(2)
CE to CEO Delay
35
35
ns
TOOE(2)
RESET/OE to CEO Delay
30
35
ns
FMAX
Maximum Input Clock Frequency
TCDF
Description
(3)
CLK to Data Float Delay
(2)
TOCK
Notes:
Min
10
Max
Industrial/Military(1)
Min
10
MHz
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
11
1636E–CONF–03/02
AC Characteristics for AT17LV65/128/256
VCC = 3.3V ± 10%
Commercial
Symbol
Description
TOE(2)
OE to Data Delay
TCE(2)
TCAC
(2)
TOH
TDF
Max
Units
50
55
ns
CE to Data Delay
60
60
ns
CLK to Data Delay
75
80
ns
Data Hold from CE, OE, or CLK
(3)
Min
Max
Industrial/Military(1)
0
CE or OE to Data Float Delay
Min
0
55
ns
55
ns
TLC
CLK Low Time
25
25
ns
THC
CLK High Time
25
25
ns
TSCE
CE Setup Time to CLK (to guarantee proper counting)
35
60
ns
THCE
CE Hold Time from CLK (to guarantee proper counting)
0
0
ns
THOE
OE High Time (guarantees counter is reset)
25
25
ns
FMAX
Maximum Input Clock Frequency
10
10
MHz
Notes:
1. Preliminary specifications for military operating range only.
2. AC test lead = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
AC Characteristics for AT17LV65/128/256 when Cascading
VCC = 3.3V ± 10%
Commercial
Symbol
Description
TCDF (3)
Min
Max
Industrial/Military(1)
Min
Max
Units
CLK to Data Float Delay
60
60
ns
TOCK
(2)
CLK to CEO Delay
55
60
ns
TOCE
(2)
CE to CEO Delay
55
60
ns
(2)
RESET/OE to CEO Delay
40
45
ns
TOOE
FMAX
Notes:
12
Maximum Input Clock Frequency
8
8
MHz
1. Preliminary specifications for military operating range only.
2. AC test lead = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
AT17C/LV65/128/256
1636E–CONF–03/02
AT17C/LV65/128/256
Thermal Resistance Coefficients(1)
θJC [°C/W]
θJA [°C/W]
Airflow = 0 ft/min
8CN4
45
115.71
Plastic Dual Inline Package
(PDIP)
8P3
37
107
Plastic Gull Wing Small Outline
(SOIC)
8S1
45
150
Plastic Leaded Chip Carrier
(PLCC)
20J
35
90
Package Type
Leadless Array Package
(LAP)
Note:
1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site, at
http://www.atmel.com/atmel/acrobat/doc0636.pdf.
13
1636E–CONF–03/02
Ordering Information – 5V Devices(1)
Memory Size
Ordering Code
Package
Operation Range
64-Kbit
AT17C65-10CC
AT17C65-10PC
AT17C65-10NC
AT17C65-10JC
8CN4
8P3
8S1
20J
Commercial
(0°C to 70°C)
AT17C65-10CI
AT17C65-10PI
AT17C65-10NI
AT17C65-10JI
8CN4
8P3
8S1
20J
Industrial
(-40°C to 85°C)
AT17C128-10CC
AT17C128-10PC
AT17C128-10NC
AT17C128-10JC
8CN4
8P3
8S1
20J
Commercial
(0°C to 70°C)
AT17C128-10CI
AT17C128-10PI
AT17C128-10NI
AT17C128-10JI
8CN4
8P3
8S1
20J
Industrial
(-40°C to 85°C)
AT17C256-10CC
AT17C256-10PC
AT17C256-10NC
AT17C256-10JC
8CN4
8P3
8S1
20J
Commercial
(0°C to 70°C)
AT17C256-10CI
AT17C256-10PI
AT17C256-10NI
AT17C256-10JI
8CN4
8P3
8S1
20J
Industrial
(-40°C to 85°C)
128-Kbit
256-Kbit
Note:
1. Currently there are two types of low-density configurators. The new version will be identified by a “B” after the date code.
Only the “B” version is available in the 8-lead SOIC devices. The “B” version is fully backward-compatible with the original
devices so existing customers will not be affected. The new parts no longer require a mux for ISP. See the programming
specification for more details.
Package Type
8CN4
8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
20J
20-lead, Plastic J-leaded Chip Carrier (PLCC)
14
AT17C/LV65/128/256
1636E–CONF–03/02
AT17C/LV65/128/256
Ordering Information – 3.3V Devices(1)
Memory Size
Ordering Code
Package
Operation Range
64-Kbit
AT17LV65-10CC
AT17LV65-10PC
AT17LV65-10NC
AT17LV65-10JC
8CN4
8P3
8S1
20J
Commercial
(0°C to 70°C)
AT17LV65-10CI
AT17LV65-10PI
AT17LV65-10NI
AT17LV65-10JI
8CN4
8P3
8S1
20J
Industrial
(-40°C to 85°C)
AT17LV128-10CC
AT17LV128-10PC
AT17LV128-10NC
AT17LV128-10JC
8CN4
8P3
8S1
20J
Commercial
(0°C to 70°C)
AT17LV128-10CI
AT17LV128-10PI
AT17LV128-10NI
AT17LV128-10JI
8CN4
8P3
8S1
20J
Industrial
(-40°C to 85°C)
AT17LV256-10CC
AT17LV256-10PC
AT17LV256-10NC
AT17LV256-10JC
8CN4
8P3
8S1
20J
Commercial
(0°C to 70°C)
AT17LV256-10CI
AT17LV256-10PI
AT17LV256-10NI
AT17LV256-10JI
8CN4
8P3
8S1
20J
Industrial
(-40°C to 85°C)
128-Kbit
256-Kbit
Note:
1. Currently there are two types of low-density configurators. The new version will be identified by a “B” after the date code.
Only the “B” version is available in the 8-lead SOIC devices. The “B” version is fully backward-compatible with the original
devices so existing customers will not be affected. The new parts no longer require a mux for ISP. See the programming
specification for more details.
Package Type
8CN4
8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
20J
20-lead, Plastic J-leaded Chip Carrier (PLCC)
15
1636E–CONF–03/02
Packaging Information
8CN4 – LAP
Marked Pin1 Indentifier
E
A
A1
D
Top View
Side View
Pin1 Corner
L1
0.10 mm
TYP
8
1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
2
7
3
6
b
5
4
e1
L
Bottom View
SYMBOL
MIN
NOM
MAX
A
0.94
1.04
1.14
A1
0.30
0.34
0.38
b
0.45
0.50
0.55
D
5.89
5.99
6.09
E
4.89
5.99
6.09
e
1.27 BSC
e1
1.10 REF
NOTE
1
L
0.95
1.00
1.05
1
L1
1.25
1.30
1.35
1
Note: 1. Metal Pad Dimensions.
11/14/01
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP)
DRAWING NO.
8CN4
REV.
A
AT17C/LV65/128/256
1636E–CONF–03/02
AT17C/LV65/128/256
8P3 – PDIP
D
PIN
1
E1
A
B1
SEATING PLANE
A1
L
B
B2
e
(4 PLACES)
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
eC
eB
Notes:
1. This package conforms to JEDEC reference MS-001 BA.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
NOM
MAX
–
–
4.318
A1
0.381
–
–
D
9.144
–
9.652
E
7.620
–
8.255
E1
6.096
–
6.604
B
0.406
–
0.508
B1
1.397
–
1.651
B2
0.762
–
1.143
L
3.175
–
3.429
C
0.203
–
0.356
eB
–
–
10.922
eC
0.000
–
1.524
e
R
TITLE
2325 Orchard Parkway
8P3, 8-lead (0.300"/7.62 mm Wide) Plastic Dual
San Jose, CA 95131
Inline Package (PDIP)
MIN
A
SYMBOL
NOTE
Note 2
Note 2
2.540 TYP
09/28/01
DRAWING NO. REV.
8P3
B
17
1636E–CONF–03/02
8S1 – SOIC
3
2
1
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
A2
C
L
SYMBOL
MIN
NOM
MAX
A
–
–
1.75
B
–
–
0.51
C
–
–
0.25
D
–
–
5.00
E
–
–
4.00
e
E
End View
NOTE
1.27 BSC
H
–
–
6.20
L
–
–
1.27
Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
R
18
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
REV.
8S1
A
AT17C/LV65/128/256
1636E–CONF–03/02
AT17C/LV65/128/256
20J – PLCC
PIN NO. 1
1.14(0.045) X 45˚
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
9.779
–
10.033
D1
8.890
–
9.042
E
9.779
–
10.033
E1
8.890
–
9.042
D2/E2
7.366
–
8.382
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
20J
B
19
1636E–CONF–03/02
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1636E–03/02 /xM