ATMEL AT17F16

Features
• Programmable 16,777,216 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
• 3.3V Output Capability
• 5V Tolerant I/O Pins
• Program Support using the Atmel ATDH2200E System or Industry Third Party
Programmers
• In-System Programmable (ISP) via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT40K and AT94K Devices, Altera FLEX®, APEX™ Devices,
•
•
•
•
•
•
•
•
Lucent ORCA® FPGAs, Xilinx XC3000™, XC4000™, XC5200™, Spartan®, Virtex® FPGAs,
Motorola MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Low-power CMOS FLASH Process
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Footprint Packages), 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Low-power Standby Mode
Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System
Reconfiguration
Fast Serial Download Speeds up to 33 MHz
Endurance: 10,000 Write Cycles Typical
Description
The AT17F Series of In-System Programmable Configuration PROMs (Configurators)
provide an easy-to-use, cost-effective configuration memory for Field Programmable
Gate Arrays. The AT17F Series device is packaged in the 8-lead LAP, 20-lead PLCC,
44-lead PLCC and 44-lead TQFP, see Table 1. The AT17F Series Configurator uses a
simple serial-access procedure to configure one or more FPGA devices.
FPGA
Configuration
Flash Memory
AT17F16
Advance
Information
The AT17F Series Configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1. AT17F Series Packages
Package
AT17F16
8-lead LAP
Yes
20-lead PLCC
Yes
44-lead PLCC
Yes
44-lead TQFP
Yes
Rev. 3392A–CNFG–10/03
1
Pin Configuration
8-lead LAP
DATA
CLK
RESET/OE
CE
1
2
3
4
8
7
6
5
VCC
SER_EN
CEO (A2)
GND
18
17
16
15
14
9
10
11
12
13
4
5
6
7
8
NC
SER_EN
PAGE_EN
READY
CEO (A2)
NC
GND
PAGESEL0
NC
NC
CLK
NC
RESET/OE
PAGESEL1
CE
3
2
1
20
19
NC
DATA
NC
VCC
NC
20-lead PLCC
2
AT17F16
3392A–CNFG–10/03
NC
RESET/OE
PAGESEL0
CE
NC
NC
GND
PAGESEL1
NC
CEO(A2)
NC
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
NC
CLK
NC
NC
DATA
PAGE_EN
VCC
NC
NC
SER_EN
NC
NC
RESET/OE
PAGESEL0
CE
NC
NC
GND
PAGESEL1
NC
CEO/A2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
3392A–CNFG–10/03
6
5
4
3
2
1
44
43
42
41
40
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NC
CLK
NC
NC
DATA
PAGE_EN
VCC
NC
NC
SER_EN
NC
AT17F16
44 PLCC
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
44 TQFP
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
3
Block Diagram
Power-on
Reset
READY
PAGE_EN
PAGESEL0
PAGESEL1
Reset
Clock/Oscillator
Logic
CEO(A2)
Config. Page
Select
Serial Download Logic
2-wire Serial Programming
Flash
Memory
CLK
CE/WE/OE
Data
Address
DATA
CE
Control Logic
RESET/OE
SER_EN
Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK)
interface directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration device without
requiring an external intelligent controller.
The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and
enable the address counter. When RESET/OE is driven Low, the configuration device
resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F Series Configurator. If CE is held High after the RESET/OE reset
pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA output pin are enabled. When
RESET/OE is driven Low again, the address counter is reset and the DATA output pin is
tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
4
AT17F16
3392A–CNFG–10/03
AT17F16
Pin Description
AT17F16
Name
I/O
8
LAP
20
PLCC
44
PLCC
44
TQFP
DATA
I/O
1
2
2
40
CLK
I
2
4
5
43
PAGE_EN
I
–
16
1
39
PAGESEL0
I
–
11
20
14
PAGESEL1
I
–
7
25
19
RESET/OE
I
3
6
19
13
CE
I
4
8
21
15
GND
–
5
10
24
18
CEO
O
A2
I
6
14
27
21
READY
O
–
15
29
23
SER_EN
I
7
17
41
35
VCC
–
8
20
44
38
DATA(1)
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
CLK(1)
Clock input. Used to increment the internal address and bit counter for reading and
programming.
PAGE_EN(2)
Input used to enable page download mode. When PAGE_EN is high the configuration
download address space is partitioned into 4 equal pages. This gives users the ability to
easily store and retrieve multiple configuration bitstreams from a single configuration
device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be
remain low if paging is not desired. When SER_EN is Low (ISP mode) this pin has no
effect.
Notes:
1. This pin has an internal 20 KΩ pull-up resistor.
2. This pin has an internal 30 KΩ pull-down resistor.
5
3392A–CNFG–10/03
PAGESEL[1:0](2)
Page select inputs. Used to determine which of the 4 memory pages are targeted during
a serial configuration download. The address space for each of the pages is shown in
Table 2. When SER_EN is Low (ISP mode) these pins have no effect.
Table 2. Address Space
Paging Decodes
AT17F16 (16 Mbits)
PAGESEL = 00, PAGE_EN = 1
00000 – 3FFFFh
PAGESEL = 01, PAGE_EN = 1
40000 – 7FFFFh
PAGESEL = 10, PAGE_EN = 1
80000 – BFFFFh
PAGESEL = 11, PAGE_EN = 1
C0000 – FFFFFh
PAGESEL = XX, PAGE_EN = 0
00000 – FFFFFh
RESET/OE(1)
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver.
CE(1)
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the 2-wire Serial Programming
mode (SER_EN Low).
GND
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
CEO
Chip Enable Output (when SER_EN is High). This output goes Low when the internal
address counter has reached its maximum value. If the PAGE_EN input is set High, the
maximum value is the highest address in the selected partition. The PAGESEL[1:0]
inputs are used to make the 4 partition selections. If the PAGE_EN input is set Low, the
device is not partitioned and the address maximum value is the highest address in the
device, see Table 2 on page 6. In a daisy chain of AT17F Series devices, the CEO pin of
one device must be connected to the CE input of the next device in the chain. It will stay
Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low;
thereafter, CEO will stay High until the entire EEPROM is read again.
A2(1)
Device selection input, (when SER_EN Low). The input is used to enable (or chip
select) the device during programming (i.e., when SER_EN is Low). Refer to the AT17F
Programming Specification available on the Atmel web site for additional details.
READY
Open collector reset state indicator. Driven Low during power-up reset, released when
power-up is complete. (recommended 4.7 kΩ pull-up on this pin if used).
SER_EN(1)
The serial enable input must remain High during FPGA configuration operations. Bringing SER_EN Low enables the 2-Wire Serial Programming Mode. For non-ISP
applications, SER_EN should be tied to VCC.
VCC
+3.3V (±10%).
Notes:
6
1. This pin has an internal 20 KΩ pull-up resistor.
2. This pin has an internal 30 KΩ pull-down resistor.
AT17F16
3392A–CNFG–10/03
AT17F16
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master mode, the FPGA
automatically loads the configuration program from an external memory. The AT17F
Serial Configuration PROM has been designed for compatibility with the Master Serial
mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as
well as Xilinx applications.
Control of
Configuration
Cascading Serial
Configuration
Devices
Most connections between the FPGA device and the AT17F Serial Configurator PROM
are simple and self-explanatory.
•
The DATA output of the AT17F Series Configurator drives DIN of the FPGA devices.
•
The master FPGA CCLK output drives the CLK input of the AT17F Series
Configurator.
•
The CEO output of any AT17F Series Configurator drives the CE input of the next
Configurator in a cascade chain of configurator devices.
•
SER_EN must be connected to VCC or allowed to float to logic High via the internal
pull-up resistor (except during ISP).
•
The READY pin is available as an open-collector indicator of the device’s reset
status; it is driven Low while the device is in its power-on reset cycle and released
(tri-stated) when the cycle is complete.
•
PAGE_EN must be held Low if download paging is not desired. The PAGESEL[1:0]
inputs must be tied off High or Low. If paging is desired, PAGE_EN must be High
and the PAGESEL pins must be set to High or Low such that the desired page is
selected, see Table 2 on page 6.
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator
asserts its CEO output Low and disables its DATA line driver. The second configurator
recognizes the Low level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are
reset if the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input
can be tied to its inactive (High) level.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the 2-wire serial bus. The programming is done at VCC supply only.
Programming super voltages are generated inside the chip. The AT17F parts are
read/write at 3.3V nominal. Refer to the AT17F Programming Specification available on
the Atmel web site (www.atmel.com) for more programming details. AT17F devices are
supported by the Atmel ATDH2200E programming system along with many third party
programmers.
Standby Mode
The AT17F Series Configurators enter a low-power standby mode whenever SER_EN
is High and CE is asserted High. In this mode, the AT17F Configurator consumes less
than 5 mA of current at 3.6V. The output remains in a high-impedance state regardless
of the state of the OE input.
7
3392A–CNFG–10/03
Absolute Maximum Ratings*
Operating Temperature.................................... -40°C to +85 °C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground ..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +4.0V
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods of time may affect device reliability.
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
Operating Conditions
AT17F Series Configurator
Symbol
Description
Min
Max
Units
Commercial
Supply voltage relative to GND
-0°C to +70°C
2.97
3.63
V
Industrial
Supply voltage relative to GND
-40°C to +85°C
2.97
3.63
V
VCC
DC Characteristics
AT17F16
Symbol
Description
Min
Max
Units
VIH
High-level Input Voltage
2.0
VCC
V
VIL
Low-level Input Voltage
0
0.8
V
VOH
High-level Output Voltage (IOH = -2.5 mA)
VOL
Low-level Output Voltage (IOL = +3 mA)
VOH
High-level Output Voltage (IOH = -2 mA)
VOL
Low-level Output Voltage (IOL = +3 mA)
ICCA
Supply Current, Active Mode (3.6V 33 MHz)
IL
Input or Output Leakage Current (VIN = VCC or GND)
ICCS
Supply Current, Standby Mode
8
Commercial
Industrial
2.4
V
0.4
2.4
V
V
0.4
V
40
mA
10
µA
Commercial
2
mA
Industrial
2
mA
-10
AT17F16
3392A–CNFG–10/03
AT17F16
AC Characteristics
CE
TSCE
TSCE
THCE
RESET/OE
TLC
THOE
THC
CLK
TOE
TOH
TCAC
TDF
TCE
DATA
TOH
AC Characteristics when Cascading
RESET/OE
CE
CLK
TCDF
DATA
FIRST BIT
LAST BIT
TOCK
TOCE
TOOE
CEO
TOCE
9
3392A–CNFG–10/03
AC Characteristics
AT17F16
Symbol
Description
TOE(2)
OE to Data Delay
TCE(2)
CE to Data Delay
TCAC(2)
CLK to Data Delay
TOH
Data Hold from CE, OE, or CLK
TDF(3)
CE or OE to Data Float Delay
TLC
CLK Low Time
THC
CLK High Time
TSCE
CE Setup Time to CLK
(to guarantee proper counting)
Commercial
THCE
CE Hold Time from CLK
(to guarantee proper counting)
Commercial
THOE
Reset/OE Low Time
(guarantees counter is reset)
Commercial
FMAX
Maximum Input Clock Frequency
SEREN = 0
Commercial
FMAX
Maximum Input Clock Frequency
SEREN = 1
TWR
Write Cycle Time(4)
TEC
Erase Cycle Time(4)
Notes:
10
1.
2.
3.
4.
Min
Commercial
Industrial
(1)
Commercial
Industrial
(1)
Commercial
Industrial
3
(1)
Max
Units
50
ns
55
ns
55
ns
60
ns
30
ns
30
ns
Commercial
0
ns
Industrial(1)
0
ns
Commercial
Industrial
(1)
15
ns
15
ns
Commercial
15
ns
Industrial(1)
15
ns
Commercial
15
ns
15
ns
20
ns
25
ns
0
ns
0
ns
20
ns
20
ns
Industrial
Industrial
Industrial
Industrial
(1)
(1)
(1)
(1)
10
MHz
10
MHz
Commercial
33
MHz
Industrial(1)
33
MHz
Commercial
30
µs
30
µs
60
s
60
s
Industrial
Industrial
(1)
(1)
Commercial
Industrial
(1)
Preliminary specifications for military operating range only.
AC test lead = 50 pF.
Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
See the AT17F Programming Specfication for procedural information.
AT17F16
3392A–CNFG–10/03
AT17F16
AC Characteristics When Cascading
AT17F16
Symbol
Description
TCDF(3)
CLK to Data Float Delay
TOCK(2)
CLK to CEO Delay
TOCE(2)
CE to CEO Delay
TOOE(2)
RESET/OE to CEO Delay
FMAX
Maximum Input Clock Frequency
Notes:
Min
Max
Units
Commercial
50
ns
Industrial
50
ns
Commercial
50
ns
Industrial
55
ns
Commercial
35
ns
Industrial
40
ns
Commercial
35
ns
Industrial
35
ns
Commercial
33
MHz
Industrial
33
MHz
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
11
3392A–CNFG–10/03
Thermal Resistance Coefficients
Package Type
8CN4
Leadless Array Package (LAP)
20J
Plastic Leaded Chip Carrier (PLCC)
44A
Thin Plastic Quad Flat Package (TQFP)
44J
Plastic Leaded Chip Carrier (PLCC)
Note:
12
AT17F16
θJC [°C/W]
θJA [°C/W]
(1)
–
–
θJC [°C/W]
–
θJA [°C/W](1)
–
θJC [°C/W]
17
θJA [°C/W]
(1)
62
θJC [°C/W]
15
θJA [°C/W](1)
50
1. Airflow = 0 ft/min.
AT17F16
3392A–CNFG–10/03
AT17F16
Ordering Information
Memory Size
16-Mbit
Ordering Code
Package
Operation Range
AT17F16-30CC
AT17F16-30JC
AT17F16-30TQC
AT17F16-30BJC
8CN4 - 8 LAP
20J - 20 PLCC
44A - 44 TQFP
44J - 44 PLCC
Commercial
(0°C to 70°C)
AT17F16-30CI
AT17F16-30JI
AT17F16-30TQI
AT17F16-30BJI
8CN4 - 8 LAP
20J - 20 PLCC
44A - 44 TQFP
44J - 44 PLCC
Industrial
(-40°C to 85°C)
Package Type
8CN4
8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages
20J
20-lead, Plastic J-leaded Chip Carrier (PLCC)
44A
44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
44J
44-lead, Plastic J-leaded Chip Carrier (PLCC)
13
3392A–CNFG–10/03
Packaging Information
8CN4 – LAP
Marked Pin1 Indentifier
E
A
A1
D
Top View
Side View
Pin1 Corner
L1
0.10 mm
TYP
8
1
e
7
COMMON DIMENSIONS
(Unit of Measure = mm)
2
3
6
b
5
4
e1
L
Bottom View
SYMBOL
MIN
NOM
MAX
A
0.94
1.04
1.14
A1
0.30
0.34
0.38
b
0.45
0.50
0.55
D
5.89
5.99
6.09
E
4.89
5.99
6.09
e
NOTE
1
1.27 BSC
e1
1.10 REF
L
0.95
1.00
1.05
1
L1
1.25
1.30
1.35
1
Note: 1. Metal Pad Dimensions.
11/14/01
R
14
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP)
DRAWING NO.
8CN4
REV.
A
AT17F16
3392A–CNFG–10/03
AT17F16
20J – PLCC
PIN NO. 1
1.14(0.045) X 45˚
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
9.779
–
10.033
D1
8.890
–
9.042
E
9.779
–
10.033
E1
8.890
–
9.042
D2/E2
7.366
–
8.382
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
20J
B
15
3392A–CNFG–10/03
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
44A
B
AT17F16
3392A–CNFG–10/03
AT17F16
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
17.399
–
17.653
D1
16.510
–
16.662
E
17.399
–
17.653
E1
16.510
–
16.662
D2/E2
14.986
–
16.002
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
44J
B
17
3392A–CNFG–10/03
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Atmel Programmable SLI Hotline
(408) 436-4119
Atmel Programmable SLI e-mail
[email protected]
Atmel Operations
Memory
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
e-mail
[email protected]
Web Site
http://www.atmel.com
FAQ
Available on web site
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
© Atmel Corporation 2003. All rights reserved. Atmel® and combinations thereof, are the registered
trademarks of Atmel Corporation or its subsidiaries. FLEX ™ is the trademarks of Altera Corporation. ORCA ™ is
the trademark of Lucent Technologies, Inc. SPARTAN® and Virtex ® are the registered trademarks, and
XC3000 ™, XC4000 ™ and XC5200 ™ are the trademarks of Xilinx, Inc. APEX™ is the trademark of MIPS Technologies. Other terms and product names may be the trademarks of others.
Printed on recycled paper.
3392A–CNFG–10/03
xM
WWW.ALLDATASHEET.COM
Copyright © Each Manufacturing Company.
All Datasheets cannot be modified without permission.
This datasheet has been download from :
www.AllDataSheet.com
100% Free DataSheet Search Site.
Free Download.
No Register.
Fast Search System.
www.AllDataSheet.com