ETC BUK107-50DS

Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
DESCRIPTION
Monolithic overload protected logic
level power MOSFET in a surface
mount plastic envelope, intended as
a general purpose switch for
automotive systems and other
applications.
APPLICATIONS
General controller for driving
lamps
small motors
solenoids
FEATURES
Vertical power DMOS output
stage
Overload protected up to
85˚C ambient
Overload protection by current
limiting and overtemperature
sensing
Latched overload protection
reset by input
Input clamping suitable for
pull-up resistor drive circuit
Control of power MOSFET
and supply of overload
protection circuits
derived from input
ESD protection on all pins
Overvoltage clamping for turn
off of inductive loads
BUK107-50DS
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MAX.
UNIT
VDS
Continuous drain source voltage
50
V
ID
Continuous drain current
0.7
A
PD
Total power dissipation
1.8
W
Tj
Continuous junction temperature
150
˚C
RDS(ON)
Drain-source on-state resistance
175
mΩ
FUNCTIONAL BLOCK DIAGRAM
DRAIN
O/V
CLAMP
POWER
INPUT
MOSFET
RIG
LOGIC AND
PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT223
PIN
PIN CONFIGURATION
DESCRIPTION
1
input
2
drain
3
source
4
drain (tab)
March 1997
SYMBOL
4
D
TOPFET
I
2
1
1
3
P
S
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DS
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
VDS
ID
II
IIRM
PD
Tstg
Tj
PARAMETER
CONDITIONS
1
Continuous drain source voltage
Continuous drain current2
Continuous input current
Non-repetitive peak input current
Total power dissipation
Storage temperature
Continuous junction temperature
clamping
tp ≤ 1 ms
Tamb = 25 ˚C
normal operation3
MIN.
MAX.
UNIT
-55
-
50
self limiting
3
10
1.8
150
150
V
A
mA
mA
W
˚C
˚C
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
VC
Electrostatic discharge capacitor
voltage
Human body model;
C = 250 pF; R = 1.5 kΩ
MIN.
MAX.
UNIT
-
2
kV
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL
PARAMETER
CONDITIONS
EDSM
Non-repetitive clamping energy
EDRM
Repetitive clamping energy
Tb ≤ 25 ˚C; IDM < ID(lim);
inductive load
Tb ≤ 75 ˚C; IDM = 50 mA;
f = 250 Hz
MIN.
MAX.
UNIT
-
100
mJ
-
4
mJ
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from short circuit loads.
Overload protection operates by means of drain current limiting and activating the overtemperature protection.
SYMBOL
PARAMETER
CONDITIONS
VDDP
Protected drain source supply voltage II = 1.5 mA
VIS = 6 V
MIN.
MAX.
UNIT
-
35
16
V
V
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off to protect itself when there is an overload fault condition.
It remains latched off until reset by the input.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
0.7
1.1
1.5
A
100
130
160
˚C
Overload protection
ID(lim)
Drain current limiting
II = 1.5 mA
Tj(TO)
Overtemperature protection
only in drain current limiting
Threshold junction temperature II = 1.5 mA
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 Refer to OVERLOAD PROTECTION CHARACTERISTICS.
3 Not in an overload condition with drain current limiting.
March 1997
2
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DS
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
Rth j-sp
Rth j-b
Rth j-a
Thermal resistance
Junction to solder point
Junction to board1
Junction to ambient
CONDITIONS
Mounted on any PCB
Mounted on PCB of fig. 19
MIN.
TYP.
MAX.
UNIT
-
12
40
-
18
70
K/W
K/W
K/W
MIN.
TYP.
MAX.
UNIT
50
-
55
56
70
V
V
-
0.5
1
10
125
2
20
100
175
µA
µA
µA
mΩ
STATIC CHARACTERISTICS
Tb = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
V(CL)DSS
V(CL)DSS
Drain-source clamping voltage
Drain-source clamping voltage
IDSS
IDSS
IDSS
RDS(ON)
Off-state drain current
Off-state drain current
Off-state drain current
Drain-source on-state
resistance2
VIS = 0 V; ID = 10 mA
VIS = 0 V; IDM = 200 mA;
tp ≤ 300 µs; δ ≤ 0.01
VDS = 45 V; VIS = 0 V
VDS = 50 V; VIS = 0 V
VDS = 40 V; VIS = 0 V; Tj = 100 ˚C
II = 1.5 mA; IDM = 100 mA;
tp ≤ 300 µs; δ ≤ 0.01
INPUT CHARACTERISTICS
Tb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
The input clamping is suitable for a drive circuit with a pull-up resistor.
SYMBOL
PARAMETER
CONDITIONS
VIS(TO)
IIS
IISL
Input threshold voltage
Input supply current
Input supply current
VDS = 5 V; ID = 1 mA
normal operation;
protection latched;
VISR
V(CL)IS
RIG
Protection latch reset voltage3
Input clamping voltage
Input series resistance
II = 1.5 mA
to gate of power MOSFET
VIS = 6 V
VIS = 5 V
VIS = 3.5 V
MIN.
TYP.
MAX.
UNIT
1.7
1
6
-
2.2
550
500
250
2.2
7.5
33
2.7
750
650
400
3.5
-
V
µA
µA
µA
V
V
kΩ
SWITCHING CHARACTERISTICS
Tamb = 25 ˚C; resistive load RL = 50 Ω; adjust VDD to obtain ID = 250 mA; refer to test circuit and waveforms
SYMBOL
PARAMETER
CONDITIONS
td on
Turn-on delay time
VIS = 0 V to II = 1.5 mA
tr
Rise time
td off
Turn-off delay time
tf
Fall time
II = 1.5 mA to VIS = 0 V
MIN.
TYP.
MAX.
UNIT
-
4
-
µs
-
16
-
µs
-
3
-
µs
-
6
-
µs
1 Temperature measured 1.3 mm from tab.
2 Continuous input voltage. The specified pulse width is for the drain current.
3 The input voltage below which the overload protection circuits will be reset.
March 1997
3
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
120
BUK107-50DS
Normalised Power Derating
PD%
a
Normalised RDS(ON) = f(Tj)
110
100
90
1.5
80
70
1.0
60
50
40
0.5
30
20
10
0
0
20
40
60
80
100
Tmb / C
120
0
140
Fig.2. Normalised limiting power dissipation.
PD% = 100⋅PD/PD(25 ˚C) = f(Tmb)
2.0
ID / A
-60 -40 -20
0
20
40 60
Tj / C
80
100 120 140
Fig.5. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 100 mA; II = 1.5 mA
BUK107-50DS
RDS(ON) / mOhm
BUK107-50DS
240
CURRENT LIMITING OCCURS
WITHIN THE SHADED REGION
200
1.5
160
1.0
TYP.
TYP.
120
80
0.5
40
0
0
20
40
60
80
Tamb / C
100
120
0
140
0
4
6
8
10
VIS / V
Fig.3. Continuous drain current.
ID = f(Tamb); condition: II = 1.5 mA
1.5
2
ID / A
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(VIS); conditions: ID = 100 mA, tp = 300 µs
BUK107-50DS
1.5
ID / A
BUK107-50DS
VIS / V =
8
1
1
7
6
5
0.5
0.5
0
0
0
4
8
12
16
VDS / V
20
24
28
0
32
4
6
8
10
VIS / V
Fig.7. Typical transfer characteristics, Tj = 25 ˚C.
ID = f(VIS); conditions: VDS = 10 V, tp = 300 µs
Fig.4. Typical on-state characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 300 µs
March 1997
2
4
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
200
BUK107-50DS
Tj(TO) / C
VIS(TO) / V
BUK107-50DS
180
BUK107-50DS
3
MAX.
160
140
TYP.
TYP.
2
120
MIN.
100
1
80
60
0
2
4
6
8
10
0
-50
IIS & IISL / mA
BUK107-50DS
II / mA
10
BUK107-50DS
9
0.9
8
0.8
LATCHED
0.7
7
6
0.6
5
0.5
NORMAL
0.4
4
IISL
RESET
0.3
3
IIS
0.2
2
0.1
1
0
0
0
2
4
VIS / V
6
0
8
IIS / uA
2
4
6
8
10
VIS / V
Fig.9. Typical DC input characteristics, Tj = 25 ˚C.
IIS & IISL = f(VIS); normal operation & protection latched
500
150
Fig.11. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
Fig.8. Typical overtemperature protection threshold.
Tj(TO) = f(VIS); condition: VDS = 10 V
1.0
100
50
Tj / C
VIS / V
Fig.12. Typical input clamping characteristic.
II = f(VIS); normal operation, Tj = 25 ˚C.
BUK107-50DS
200
ID / mA
BUK107-50DS
VIS / V =
400
150
5V
300
TYP.
100
200
4V
50
100
0
0
-50
0
50
Tj / C
100
50
150
54
56
58
60
VDS / V
Fig.10. Typical DC input current.
IIS = f(Tj); parameter VIS; normal operation
March 1997
52
Fig.13. Overvoltage clamping characteristic, 25 ˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 300 µs
5
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DS
VDD
10 uA
IDSS
BUK107-50DS
RL
RI
1 uA
VDS
VIS
TOPFET
10 kO
measure
D
100 nA
I
D.U.T.
P
S
BC337
10 nA
0
-50
50
Tj / C
0V
VIS & VDS / V
150
Fig.16. Typical drain source leakage current
IDSS = f(Tj); conditions: VDS = 40 V; VIS = 0 V.
Fig.14. Test circuit for resistive load switching times.
Select RI to give II = 1.5 mA, ie 3.3 kΩ approx.
15
100
BUK107-50DS
VDS
10
VIS
5
0
-10
10
30
50
70
90
time / us
Fig.15. Typical switching waveforms, resistive load .
RL = 50 Ω; adjust VDD to obtain ID = 250 mA; Tj = 25˚C
1E+02
BUK107-50DS
Zth j-amb / (K/W)
D=
0.5
0.2
0.1
0.05
1E+01
0.02
1E+00
PD
tp
D=
tp
T
1E-01
T
t
0
1E-02
1E-07
1E-05
1E-03
1E-01
1E+01
1E+03
t/s
Fig.17. Transient thermal impedance, TOPFET mounted on PCB of fig 19.
Zth j-amb = f(t); parameter D = tp/T
March 1997
6
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DS
MOUNTING INSTRUCTIONS
PRINTED CIRCUIT BOARD
Dimensions in mm.
Dimensions in mm.
3.8
36
min
1.5
min
18
60
1.5
min
4.5
4.6
9
2.3
6.3
10
(3x)
1.5
min
7
4.6
15
50
Fig.19. PCB for thermal resistance and power rating.
PCB: FR4 epoxy glass (1.6 mm thick),
copper laminate (35 µm thick).
Fig.18. Soldering pattern for surface mounting.
March 1997
7
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DS
MECHANICAL DATA
Dimensions in mm
Net Mass: 0.11 g
0.95
0.85
handbook, full pagewidth
S
0.1 S
seating plane
6.7
6.3
0.32
0.24
B
3.1
2.9
0.2 M A
4
A
0.10
0.01
16 o
max
16
3.7
3.3
o
1
1.80
max
7.3
6.7
10 o
max
2
0.80
0.60
2.3
3
0.1 M B
(4x)
4.6
MSA035 - 1
Fig.20. SOT223 surface mounting package1.
1 For further information, refer to surface mounting instructions for SOT223 envelope. Epoxy meets UL94 V0 at 1/8".
March 1997
8
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DS
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
March 1997
9
Rev 1.200