Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET DESCRIPTION Monolithic temperature and overload protected logic level power MOSFET in TOPFET2 technology assembled in a 3 pin plastic package. APPLICATIONS General purpose switch for driving lamps motors solenoids heaters in automotive systems and other applications. FEATURES TrenchMOS output stage Current limiting Overload protection Overtemperature protection Protection latched reset by input 5 V logic compatible input level Control of output stage and supply of overload protection circuits derived from input Low operating input current permits direct drive by micro-controller ESD protection on all pins Overvoltage clamping for turn off of inductive loads BUK117-50DL QUICK REFERENCE DATA SYMBOL PARAMETER MAX. UNIT VDS ID PD Tj RDS(ON) Continuous drain source voltage Continuous drain current Total power dissipation Continuous junction temperature Drain-source on-state resistance 50 8 40 150 100 V A W ˚C mΩ IISL Input supply current 650 µA VIS = 5 V FUNCTIONAL BLOCK DIAGRAM DRAIN O/V CLAMP POWER INPUT MOSFET RIG LOGIC AND PROTECTION SOURCE Fig.1. Elements of the TOPFET. PINNING - SOT78B PIN DESCRIPTION 1 input 2 drain 3 source tab drain PIN CONFIGURATION mb mb D TOPFET I 1 2 3 Front view May 2001 SYMBOL MBL292 1 P S Rev 1.800 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK117-50DL LIMITING VALUES Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS ID Continuous drain source voltage1 Continuous drain current VIS = 5 V; Tmb = 25 ˚C - V A Continuous drain current Continuous input current Non-repetitive peak input current Total power dissipation Storage temperature Continuous junction temperature2 VIS = 5 V; Tmb ≤ 110 ˚C tp ≤ 1 ms Tmb ≤ 25 ˚C normal operation -5 -10 -55 - 50 self limited 8 5 10 40 175 150 ID II IIRM PD Tstg Tj A mA mA W ˚C ˚C Tsold Lead temperature during soldering - 260 ˚C MIN. MAX. UNIT - 2 kV ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS VC Electrostatic discharge capacitor voltage Human body model; C = 250 pF; R = 1.5 kΩ OVERVOLTAGE CLAMPING LIMITING VALUES At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL PARAMETER CONDITIONS EDSM EDRM Inductive load turn-off Non-repetitive clamping energy Repetitive clamping energy IDM = 8 A; VDD ≤ 20 V Tmb ≤ 25 ˚C Tmb ≤ 95 ˚C; f = 250 Hz MIN. MAX. UNIT - 100 20 mJ mJ OVERLOAD PROTECTION LIMITING VALUE With an adequate protection supply provided via the input pin, TOPFET can protect itself from two types of overload - overtemperature and short circuit load. SYMBOL VDS PARAMETER REQUIRED CONDITION MIN. MAX. UNIT 0 35 V 4 V ≤ VIS ≤ 5.5 V 3 Drain source voltage THERMAL CHARACTERISTIC SYMBOL PARAMETER Rth j-mb Thermal resistance Junction to mounting base CONDITIONS - MIN. TYP. MAX. UNIT - 2.5 3.1 K/W 1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch. 3 All control logic and protection functions are disabled during conduction of the source drain diode. May 2001 2 Rev 1.800 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK117-50DL OUTPUT CHARACTERISTICS Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25 ˚C unless otherwise specified SYMBOL V(CL)DSS IDSS PARAMETER CONDITIONS Off-state VIS = 0 V Drain-source clamping voltage Drain source leakage current MIN. TYP. MAX. UNIT ID = 10 mA 50 - - V IDM = 1 A; tp ≤ 300 µs; δ ≤ 0.01 50 60 70 V - 0.1 100 10 µA µA Tmb = 25 ˚C - 68 190 100 mΩ mΩ Tmb = 25 ˚C - 72 200 105 mΩ mΩ MIN. TYP. MAX. UNIT 8 6 12 - 16 18 A A 5 - 18 A 20 200 55 350 80 600 W µs 150 170 - ˚C VDS = 40 V Tmb = 25 ˚C RDS(ON) On-state IDM = 3 A; tp ≤ 300 µs; δ ≤ 0.01 Drain-source resistance VIS ≥ 4.4 V VIS ≥ 4 V OVERLOAD CHARACTERISTICS -40˚C ≤ Tmb ≤ 150˚C unless otherwise specified. SYMBOL PARAMETER CONDITIONS ID Short circuit load Drain current limiting VDS = 13 V VIS = 5 V; 4.4 V ≤ VIS ≤ 5.5 V Tmb = 25˚C 4 V ≤ VIS ≤ 5.5 V PD(TO) TDSC Overload protection Overload power threshold Characteristic time VIS = 5 V; Tmb = 25˚C device trips if PD > PD(TO) which determines trip time1 Overtemperature protection Tj(TO) Threshold junction temperature2 1 Trip time td sc varies with overload dissipation PD according to the formula td sc ≈ TDSC / ln[ PD / PD(TO) ]. 2 This is independent of the dV/dt of input voltage VIS. May 2001 3 Rev 1.800 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK117-50DL INPUT CHARACTERISTICS The supply for the logic and overload protection is taken from the input. Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS VIS(TO) Input threshold voltage VDS = 5 V; ID = 1 mA MIN. TYP. MAX. UNIT Tmb = 25˚C 0.6 1.1 1.6 2.4 2.1 V V IIS Input supply current normal operation; VIS = 5 V VIS = 4 V 100 80 220 195 400 330 µA µA IISL Input supply current protection latched; VIS = 5 V VIS = 3 V 200 130 400 250 650 430 µA µA VISR Protection reset voltage1 reset time tr ≥ 100 µs 1.5 2 2.9 V tlr Latch reset time VIS1 = 5 V, VIS2 < 1 V 10 40 100 µs V(CL)IS Input clamping voltage II = 1.5 mA 5.5 - 8.5 V - 33 - kΩ MIN. TYP. MAX. UNIT - 10 20 µs - 20 40 µs - 30 60 µs - 20 40 µs RIG 2 Input series resistance to gate of power MOSFET Tmb = 25˚C SWITCHING CHARACTERISTICS Tmb = 25 ˚C; VDD = 13 V; resistive load RL = 4 Ω. Refer to waveform figure and test circuit. SYMBOL PARAMETER CONDITIONS td on Turn-on delay time VIS = 5 V tr Rise time td off Turn-off delay time tf Fall time VIS = 0 V 1 The input voltage below which the overload protection circuits will be reset. 2 Not directly measureable from device terminals. May 2001 4 Rev 1.800 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK117-50DL MECHANICAL DATA Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-leads SOT78B E p1 A ∅p A1 q mounting base D1 (2) D L2 L1 Q b1 L 1 2 3 b(1) e c w M e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b(1) b1 c D D1 E e L L1 L2 max. ∅p p1 q Q w mm 4.5 4.1 1.39 1.27 0.85 0.60 1.3 1.0 0.7 0.4 15.8 15.2 6.4 5.9 10.3 9.7 2.54 15.0 13.5 3.30 2.79 3.0 3.8 3.6 4.3 4.1 3.0 2.7 2.6 2.2 0.4 Notes 1. The positional accuracy of the terminals is controlled within zone L1 max. 2. Mounting base configuration is not defined within the dimensions E and D OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 01-02-22 SOT78B Fig.2. SOT78B (TO220AB) package1, pin 2 connected to mounting base. 1 Refer to mounting instructions for SOT78 (TO220) envelopes. Epoxy meets UL94 V0 at 1/8". Net mass: 2 g May 2001 5 Rev 1.800 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK117-50DL DEFINITIONS DATA SHEET STATUS DATA SHEET STATUS1 PRODUCT STATUS2 DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in ordere to improve the design and supply the best possible product Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 2001 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1 Please consult the most recently issued datasheet before initiating or completing a design. 2 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. May 2001 6 Rev 1.800