CY2037 High Accuracy EPROM Programmable PLL Die for Crystal Oscillators 2.7 Features Benefits • EPROM-programmable die for in-package programming of crystal oscillators Enables quick turnaround of custom oscillators Lowers inventory costs through stocking of blank parts • High resolution PLL with 12 bit multiplier and 10 bit di- Enables synthesis of highly accurate and stable output clock vider frequencies with zero or low PPM • EPROM-programmable capacitor tuning array with Shadow register Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal • Twice programmable die (CY2037A and CY2037-2). Enables reprogramming of programmed part, to correct errors, and control excess inventory • Simple 4-wire programming interface Enables programming of output frequency after packaging • On-chip oscillator runs from 10–30 MHz fundamental tuned crystal Lowers cost of oscillator as PLL can be programmed to a high frequency using a low-frequency, low-cost crystal • EPROM-selectable TTL or CMOS duty cycle levels Duty cycle centered at 1.4V or VDD/2 Provides flexibility to service most TTL or CMOS applications • Operating frequency — 1–133 MHz at 5V — 1–100 MHz at 3.3V — 1–66.6 MHz at 2.7V Services most PC, networking, and consumer applications • Sixteen selectable post-divide options, using either PLL or reference oscillator output Provides flexibility in output configurations and testing • Programmable PWR_DWN or OE pin (CY2037A and CY2037-2) • Frequency Select (CY2037-3) Enables low-power operation or output enable function • Programmable asynchronous or synchronous OE and PWR_DWN modes (CY2037 and CY2037-2) Provides flexibility for system applications, through selectable instantaneous or synchronous change in outputs • Low Jitter outputs typically — < ± 100 ps (pk-pk) at 5V and f>33 MHz — < ± 125 ps (pk-pk) at 3.3V and f>33 MHz Suitable for most PC, consumer, and networking applications • 3.3V or 5V operation Lowers inventory cost as same die services both applications • Small Die Enables encapsulation in small-size, surface mount packages • Controlled rise and fall times and output slew rate Has lower EMI than oscillators Cypress Semiconductor Corporation • Enables two frequency options for meeting different industry standards, i.e., PAL/NTSC. 3901 North First Street • San Jose • CA 95134 • 408-943-2600 March 9, 2001 CY2037 CY2037 Logic Block Diagram Die Configuration PD/OE or FS Top View VDD 1 VDD 2 [1] XG XD CRYSTAL CONFIGURATION EPROM HIGH ACCURACY PLL OSCILLATOR N/C / Xx 11 CLKOUT 10 N/C 3 XD 4 N/C 5 XG 6 9 VSS PD/OE or FS 7 8 VSS 7C803xx MUX CLKOUT / 1, 2, 4, 8, 16, 32, 64, 128 The CY2037 PLL die has been designed for very high resolution. It has a 12 bit feedback counter multiplier and a 10 bit reference counter divider. This enables the synthesis of highly accurate and stable output clock frequencies with zero or low PPM error. The clock can be further modified by eight output divider options of 1, 2, 4, 8, 16, 32, 64 and 128. The divider input can be selected as either the PLL or crystal oscillator output providing a total of sixteen separate output options. For further flexibility, the ouput is selectable between TTL and CMOS duty cycle levels. Functional Description The CY2037 is an EPROM programmable, high accuracy, PLL-based die designed for the crystal oscillator market. The die attaches directly to a low-cost 10–30 MHz crystal and can be packaged into 4-pin through-hole or surface mount packages. The oscillator devices can be stocked as blank parts and custom frequencies programmed in-package at the last stage before shipping. This enables fast-turn manufacture of custom and standard crystal oscillators without the need for dedicated, expensive crystals. The CY2037A and CY2037-2 also contain flexible power management controls. These parts include both PWR_DWN and OE features with integrated pull-up resistors. The PWR_DWN and OE modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. When PWR_DWN or OE modes are enables, CLKOUT is pulled low by a weak pull down. The weak pull down is easily overdriven by another active CLKOUT for applications that require multiple CLKOUTs on a single signal path. The CY2037 contains an on-chip oscillator and an unique oscillator tuning circuit for fine-tuning of the output frequency. The crystal Cload can be selectively adjusted by programming a set of seven EPROM bits. This feature can be used to compensate for crystal variations or to obtain a more accurate synthesized frequency. The CY2037 uses EPROM programming with a simple 2-wire, 4-pin interface that includes VSS and VDD. Clock outputs can be generated up to 133 MHz at 5V or up to 100 MHz at 3.3V. The entire configuration can be re-programmed one time allowing programmed inventory to be altered or reused. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable the CY2037 to have low jitter and accurate outputs making it suitable for most PC, networking and consumer applications Note: 1. For Customers not bonding XD or XG pad to external pins, an alternative bonding option would be shorting the Xx pad to the XD pad. 2 CY2037 On the other hand, the CY2037-3 contains a frequency select function in place of the power down and output enable modes. For example, consumer products often require frequency compatibility with different electrical standards around the world. With this frequency select feature a product that incorporates the CY2037-3 could be compatible with both NTSC for North American and PAL for Europe simply by changing the FS line. The twice programmable feature is also lost in the CY2037-3, because the second EPROM row is now being used for the alternate frequency. goes low. In this mode the oscillator and PLL circuits continue to operate, allowing a rapid return to normal operation when the Control input is deasserted. In addition, the PWR_DWN and OE modes can be programmed to occur synchronously or asynchronously with respect to the output signal. When the asynchronous setting is used, the powerdown or output disable occurs immediately (allowing for logic delays) irrespective of position in the clock cycle. However, when the synchronous setting is used, the part waits for a falling edge at the output before powerdown or output enable signalis initiated, thus preventing output glitches. In either asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of the output. EPROM Configuration Block Table 1 summarizes the features which are configurable by EPROM. Please refer to the “7C8038x/7C8034X Programming Specification” for further details. The specifiction can be obtained from your Cypress factory representative. Crystal Oscillator Tuning Circuit The CY2037 contains a unique tuning circuit to fine-tune the output frequency of the device. The tuning circuit consists of an array of eleven load capacitors on both sides of the oscillator drive inverter. The capacitor load values are EPROM programmable and can be increased in small increments. As the capacitor load is increased the circuit is fine-tuned to a lower frequency. The capacitor load values vary from 0.17 pF to 8 pF for a 100:1 total control ratio. The tuning increments are shown in the table below. Please refer to the “7C8038x/7C8034x Programmimg Specification” for futher details. Table 1. EPROM Adjustable Features Adjust Frequency Feedback counter value (P) Reference counter value (Q) Output divider selection Oscillator Tuning (load capacitance values) Duty cycle levels (TTL or CMOS) Difference Between CY2037A and CY2037-2 Power management mode (OE or PWR_DWN) The CY2037A contains a shadow register in addition to the EPROM register. The shadow register is an exact copy of the EPROM register and is the default register when the Valid bit is not set. It is useful when the prototype or production environment calls for measuring and adjusting the CLKOUT frequency numerous times. Multiple adjustments can be performed with the shadow register. Once the desired frequency is achieved the EPROM register is permanently programmed. Power management timing (synchronous or asynchronous) PLL Output Frequency The CY2037 contains a high resolution PLL with 12 bit multiplier and 10 bit divider.The output frequency of the PLL is determined by the following formula: Some production flows do not require the use of the shadow register. If this is the case, then the CY2037-2 is the device of choice. The CY2037-2 has a disabled shadow register. 2 • (P + 5) F PLL = --------------------------- • F REF (Q + 2) The CY2037-3 contains the shadow register. where P is the feedback counter value and Q is the reference counter value. P and Q are EPROM programmable values. Frequency Select Feature of CY2037-3 The CY2037-3 contains a frequency select function in place of the powerdown and the output enable functions. With the frequency select feature, customers can switch two different frequencies that are configured in the two EPROM rows Thedefinition of the Frequency select pin (FS) is shown in the table below. Power Management features (except CY2037-3) The CY2037 contains EPROM programmable PWR_DWN and OE functions. If Powerdown is selected, all active circuitry on the chip is shut down when the control pin goes low. The oscillator and PLL circuits must re-lock when the part leaves Powerdown Mode. If Output Enable mode is selected, the output is tri-stated and weakly pulled low when the Control pin Die Pad Summary Name Die Pad Description VDD 1,2 Voltage supply VSS 8,9 Ground XD 4 Crystal connection. XX 3 No Connect. ( For customers not bonding XD or XG pad to external pins, an alternative bonding option would be shorting this pad to XD pad.) XG 6 Crystal connection. PD/OE or FS 7 CY2037A and CY2037-2 - EPROM programmable power down or output enable pad. CY2037-3 - Frequency Select. Serves as VPP in programming mode for all devices CLKOUT 11 Clock output. Also serves as three-state input during programming. N/C 5,10 No Connect. (Do not bond to these pads) 3 CY2037 Device Functionality: Output Frequencies Symbol Fo Description Output frequency Condition Min. Max. Unit VDD = 4.5–5.5V 1 133 MHz VDD = 3.0–3.6V 1 100 MHz VDD = 2.7–3.0V 1 66 MHz Crystal Oscillator Tuning Circuit Rf External Crystal CD6 C6 C5 C4 C3 C2 C1 CD5 CD4 CD3 CD2 CD1 CD0 C0 Cgo Cdo C7 C8 C9 CD3 CD4 C10 CD5 CD6 CD = EPROM BIT T = TRANSISTOR C = LOAD CAPACITOR Symbol Description Min. 0.5 1.0 Feedback resistor, VDD = 4.5–5.5V Feedback resistor, VDD = 2.7–3.6V Rf Typ. 2 4 Max. 3.5 9.0 Unit MΩ MΩ Capacitors have ± 20% Tolerance Cg Gate capacitor 13 pF Cd Drain Capacitor 9 pF C0 Series Cap 0.27 pF C1 Series Cap 0.52 pF C2 Series Cap 1.00 pF C3 Series Cap 0.7 pF C4 Series Cap 1.4 pF C5 Series Cap 2.6 pF C6 Series Cap 5.0 pF C7 Series Cap 0.45 pF C8 Series Cap 0.85 pF C9 Series Cap 1.7 pF C10 Series Cap 3.3 pF Table 2. Frequency Select Pin Decoding for CY2037-3 FS Pin Output Frequency 0 From EPROM Row 0 Configuration 1 From EPROM Row 1 Configuration 4 CY2037 Absolute Maximum Ratings Storage Temperature (Non-Condensing) ... 55°C to +150°C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature ...................................–40°C to +100°C Supply Voltage–0.5 to +7.0V Static Discharge Voltage ............................................ >2000V Input Voltage–0.5V to VDD+0.5 (per MIL-STD-883, Method 3015) Operating Conditions Min. Max. Unit VDD Parameter Supply Voltage (3.3V) Supply Voltage (5.0V) Description 2.7 4.5 3.6 5.5 V V TAJ [2] Operating Temperature, Junction –40 +100 °C CTTL Max. Capacitive Load on outputs for TTL levels VDD = 4.5–5.5V, Output frequency = 1–40 MHz VDD = 4.5–5.5V, Output frequency = 40–133 MHz 50 25 pF pF CCMOS Max. Capacitive Load on outputs for CMOS levels VDD = 4.5–5.5V, Output frequency = 1–66.6MHz VDD = 4.5–5.5V, Output frequency = 66.6–133MHz VDD = 3.0–3.6V, Output frequency = 1–40 MHz VDD = 3.0–3.6V, Output frequency = 40–100 MHz VDD = 2.7–3.0V, Output frequency = 1–66 MHz 50 25 30 15 15 pF pF pF pF pF XREF Reference Frequency, input crystal. Fundamental tuned crystals only. 30 MHz 10 Electrical Characteristics Over the Operating Range (Part was characterized in a 20 pin SOIC package with external crystal, Electrical Characteristics may change with other package types) Parameter Description Test Conditions Min. Typ. Max. Unit VIL Low-level Input Voltage VDD = 4.5–5.5V VDD = 2.7–3.6V 0.8 0.2VDD V V VIH High-level Input Voltage VDD = 4.5–5.5V VDD = 2.7–3.6V VOL Low-level Output Voltage VDD = 4.5–5.5V, IOL= 16 mA VDD = 2.7–3.6V, IOL= 8 mA VOHCMOS High-level Output Voltage, CMOS levels VDD = 4.5–5.5V, IOH= –16 mA VDD = 2.7–3.6V, IOH= –8 mA VDD–0.4 VDD–0.4 V V VOHTTL High-level Output Voltage, TTL levels VDD = 4.5–5.5V, IOH= –8 mA 2.4 V V V 2.0 0.7VDD 0.4 0.4 V V IIL Input Low Current VIN = 0V 10 µA IIH Input High Current VIN = VDD 5 µA IDD Power Supply Current, Unloaded VDD = 4.5–5.5V, Output frequency <= 133MHz VDD = 2.7–3.6V, Output frequency <= 100 MHz 45 25 mA mA IDDS Stand-by current VDD = 2.7-3.6V 10 50 µA RUP Input Pull-Up Resistor VDD = 4.5–5.5V, VIN = 0V VDD = 4.5–5.5V, VIN = 0.7VDD 3.0 100 8.0 200 MΩ kΩ IOE_CLKOUT CLKOUT Pulldown current VDD=5.0 1.1 50 20 Note: 2. This product is sold in die form so operating conditions are specified for the die, or junction temperature 5 µA CY2037 Output Clock Switching Characteristics Over the Operating Range[3] Max Unit t1w Symbol Output Duty Cycle at 1.4V, VDD = 4.5–5.5V t1w = t1A ÷ t1B Description 1–40 MHz, CL <= 50 pF 40–66 MHz, CL <= 15pF 66–125 MHz, CL <= 25pF 125–133 MHz, CL <= 15pF Test Conditions Min 45 45 40 40 Typ 55 55 60 60 % % % % t1x Output Duty Cycle at VDD/2, VDD = 4.5–5.5V t1x = t1A ÷ t1B 1–66.6 MHz, CL <= 25pF 66.6–125 MHz, CL <= 25 pF 125–133 MHz, CL <= 15pF 45 40 40 55 60 60 % % % t1y Output Duty Cycle at VDD/2, VDD = 3.0–3.6 t1y = t1A ÷ t1B 1–40 MHz, CL <= 30 pF 40–100 MHz, CL <= 15pF 45 40 55 60 % % t1z Output Duty Cycle at VDD/2, VDD = 2.7–3.0 t1y = t1A ÷ t1B 1–40 MHz, CL <= 15pF 40–66.6 MHz, CL <= 10pF 40 40 60 60 % % t2 Output Clock Rise time Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 50 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 25 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 15 pF Between 0.2VDD– 0.8VDD, VDD= 4.5V–5.5V, CL = 50 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 30 pF Between 0.2VDD– 0.8VDD, VDD= 2.7V–3.6V, CL = 15 pF 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t3 Output Clock Fall time Between 0.8V–2.0V, VDD = 4.5V–5.5V, CL = 50 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 25 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 15 pF Between 0.2VDD– 0.8VDD, VDD= 4.5V-5.5V, CL = 50 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 30 pF Between 0.2VDD– 0.8VDD, VDD= 2.7V–3.6V, CL = 15 pF 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t4 Start-up time out of power-down PWR_DWN or OE pin LOW to HIGH[3] 1 2 ms t5a Power Down delay time PWR_DWN pin LOW to output LOW (synchronous setting) (T=period of Output clk) T/2 T+10 ns t5b Power Down delay time PWR_DWN pin LOW to output LOW (asynchronous setting) 10 15 ns t6 Power Up time From power on[3] 1 2 ms t7a Output disable time (synchronous setting) OE pin LOW to output Hi-Z (T=period of output clk) T/2 T+10 ns t7b Output disable time (asynchronous setting) OE pin LOW to output Hi-Z 10 15 ns t8 Output enable time (always synchronous enable) PWR_DWN or OE pin LOW to HIGH (T=period of output clk) T 1.5T+25 ns t9 Peak-to-Peak Period Jitter VDD= 4.5V–5.5V, Fo > 33 MHz, VCO > 100 MHz VDD= 2.7V–3.6V, Fo > 33 MHz, VCO >100 MHz VDD= 2.7V–5.5V, Fo <33 MHz ±100 ±125 ±250 ±125 ±200 1% of FO ps ps ps Note: 3. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms. 4. Not all parameters measured in production testing. 6 CY2037 Switching Waveforms Duty Cycle Timing (t1w, t1x, t1y, t1z) t1A OUTPUT t1B Output Rise/Fall Time VDD OUTPUT 0V t2 t3 Power Down Timing (synchronous and asynchronous modes) POWER DOWN VDD VIH VIL 0V t4 CLKOUT (synchronous[5]) T t5a 1/f CLKOUT (asynchronous[6]) t5b 1/f Power Up Timing VDD POWER UP 0V VDD-10% t6 min 2ns CLKOUT 1/f Notes: 5. In synchronous mode the powerdown or output 3-state is not initiated until the next falling edge of the output clock. 6. In asynchronous mode the powerdown or output 3-state occurs within 25ns irrespective of position in the ouput clock cycle. 7 CY2037 Switching Waveforms (continued) Output Enable Timing (synchronous and asynchronous modes) VDD OUTPUT ENABLE VIH VIL 0V T CLKOUT (synchronous[4]) High Impedance t7a CLKOUT (asynchronous[5]) t8 High Impedance t7b t8 Ordering Information[7] Ordering Code Type Operating Range CY2037AWAF Wafer Industrial CY2037-2WAF Wafer Industrial CY2037-3WAF Wafer Industrial Document #: 38–00679-*D Die Information Wafer Thickness 14 ±0.5 mils Note: 7. The only difference between the CY2037A and the CY2037-2 is: The CY2037-2 has the shadow register disabled. The CY2037-3 replaces the power down options with a Frequency Select, and contains the shadow register. © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.