CY2077 High Accuracy EPROM Programmable Single-PLL Clock Generator Features Benefits • High accuracy PLL with 12-bit multiplier and 10-bit divider Enables synthesis of highly accurate and stable output clock frequencies with zero PPM • EPROM-programmability Enables quick turnaround of custom frequencies • 3.3V or 5V operation Supports industry standard design platforms • Operating frequency — 390 kHz–133 MHz at 5V — 390 kHz–100 MHz at 3.3V Services most PC, networking, and consumer applications • Reference input from either a 10-30 MHz fundamental toned crystal or a 1-75 MHz external clock Lowers cost of oscillator as PLL can be programmed to a high frequency using either a low-frequency, low-cost crystal, or an existing system clock • EPROM-selectable TTL or CMOS duty cycle levels Duty cycle centered at 1.5V or VDD/2 Provides flexibility to service most TTL or CMOS applications • Sixteen selectable post-divide options, using either PLL Provides flexibility in output configurations and testing or reference oscillator/external clock • Programmable PWR_DWN or OE pin, with asynchronous or synchronous modes Enables low-power operation or output enable function and flexibility for system applications, through selectable instantaneous or synchronous change in outputs • Low Jitter outputs typically — 80 ps at 3.3V/5V Suitable for most PC, consumer, and networking applications • Controlled rise and fall times and output slew rate Has lower EMI than oscillators • Available in both commercial and industrial temperature Suitable to fit most applications • Factory-programmable device options Easy customization and fast turnaround. either CY2077 Logic Block Diagram Pin Configuration PWR_DWN XTALIN or external clock Q 10 bits Phase Detector XTALOUT [1] CRYSTAL OSCILLATOR or OE Charge Pump 8-Pin Top View CONFIGURATION EPROM VDD XTALOUT XTALIN PD/OE VCO 1 2 3 4 8 7 6 5 CLKOUT VSS VSS VSS P 12 bits HIGH ACCURACY PLL MUX Note 1. When using an external clock source leave XTALOUT floating Cypress Semiconductor Corporation CLKOUT / 1, 2, 4, 8, 16, 32, 64, 128 • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 January 24, 2001 CY2077 Functional Description PLL Output Frequency The CY2077 is an EPROM-programmable, high-accuracy, general purpose, PLL-based design for use in applications such as modems, disk drives, CD-ROM drives, video CD players, DVD players, games, set-top boxes, and data/telecommunications. The CY2077 contains a high resolution PLL with 12 bit multiplier and 10 bit divider.The output frequency of the PLL is determined by the following formula: 2 • (P + 5) FPLL = --------------------------- • F REF (Q + 2) The CY2077 can generate a clock output up to 133 MHz at 5V or 100 MHz at 3.3V. It has been designed to give the customer a very accurate and stable clock frequency with little to zero PPM error. The CY2077 contains a 12-bit feedback counter divider and 10-bit reference counter divider to obtain a very high resolution to meet the needs of stringent design specifications. Further more, there are 8 output divide options of /1, /2, /4, /8, /16, /32, /64, and /128. The output divider can select between the PLL and crystal oscillator output/external clock, providing a total of 16 different options. To add more flexibility in designs. TTL or CMOS duty cycles can be selected. where P is the feedback counter value and Q is the reference counter value. P and Q are EPROM programmable values. The calculation of P and Q values for a given PLL output frequency is handled by the CyClocks software. Refer to the “Custom Configuration Request Procedure” section for details. Power Management Features PWR_DWN and OE options are configurable by EPROM programming for the CY2077. In PWR_DWN mode, all active circuits are powered down when the control pin is set to LOW. When the control pin is set back to HIGH, both the PLL and oscillator circuit must re-lock. In the case of OE, the output is three-stated and weakly pulled down when the control pin is set to LOW. The oscillator and PLL are still active in this state, which leads to a quick clock output return when the control pin is set back to HIGH. Power management with the CY2077 is also very flexible. The user may choose either a PWR_DWN or an OE feature with which both have integrated pull-up resistors. PWR_DWN and OE signals can be programmed to have asynchronous and synchronous timing with respect to the output siginal. There is a weak pull-down on the output that will pull CLKOUT low when either the PWR_DWN or OE siginal is active. This weak pull-down can easily be overridden by another clock signal in designs where multiple clock signals share a signal path. Additionally, PWR_DWN and OE can be configured to occur asynchronously or synchronously with respect to CLKOUT. In asynchronous mode, PWR_DWN or OE disables CLKOUT immediately (allowing for logic delays), without respect to the current state of CLKOUT. Synchronous mode will prevent output glitches by waiting for the next falling edge of CLKOUT after PWR_DWN or OE becomes asserted. In either asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of CLKOUT. Multiple options for output selection, better power distribution layout, and controlled rise and fall times enable the CY2077 to be used in applications which require low jitter and accurate reference frequencies. EPROM Configuration Block Table 1 summarizes the features which are configurable by EPROM . Table 1. EPROM Adjustable Features EPROM Adjustable Features Adjust Freq. Feedback counter value (P) Reference counter value (Q) Output divider selection Duty cycle levels (TTL or CMOS) Power management mode (OE or PWR_DWN) Power management timing (synchronous or asynchronous) Pin Summary Name Pin Description VDD 1 Voltage supply. VSS 5,6,7 Ground (all the pins have to be grounded). XD 2 Crystal output (leave this pin floating when external reference is used.). XG 3 Crystal input or external input reference. PWR_DWN / OE 4 EPROM programmable power down or output enable pin. Weak pull-up. CLKOUT Clock output. Weak pull-down. 8 2 CY2077 Device Functionality: Output Frequencies Symbol Fo Description Output frequency Condition Min. Max. Unit VDD = 4.5–5.5V 0.39 133 MHz VDD = 3.0–3.6V 0.39 100 MHz Absolute Maximum Ratings Storage Temperature (Non-Condensing) ... –55°C to +150°C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature .................................................. 150°C Static Discharge Voltage .......................................... >2000V (per MIL-STD-883, Method 3015) Supply Voltage ..................................................–0.5 to +7.0V Input Voltage ............................................–0.5V to VDD+0.5V Operating Conditions for Commercial Temperature Device Parameter Description VDD Supply Voltage TA Operating Temperature, Ambient CTTL Min. Max. Unit 3.0 5.5 V 0 +70 °C Max. Capacitive Load on outputs for TTL levels VDD = 4.5–5.5V, Output frequency = 1–40 MHz VDD = 4.5–5.5V, Output frequency = 40–125 MHz VDD = 4.5–5.5V, Output frequency = 125–133 MHz 50 25 15 pF pF pF CCMOS Max. Capacitive Load on outputs for CMOS levels VDD = 4.5–5.5V, Output frequency = 1–40 MHz VDD = 4.5–5.5V, Output frequency = 40–125 MHz VDD = 4.5–5.5V, Output frequency = 125–133 MHz VDD = 3.0–3.6V, Output frequency = 1–40 MHz VDD = 3.0–3.6V, Output frequency = 40–100 MHz 50 25 15 30 15 pF pF pF pF pF XREF Reference Frequency, input crystal with Cload = 10 pF 10 30 MHz Reference Frequency, external clock source 1 75 MHz Electrical Characteristics TA = 0°C to +70°C Parameter Description Test Conditions VIL Low-level Input Voltage VDD = 4.5–5.5V VDD = 3.0–3.6V Min. Typ. Max. Unit 0.8 0.2VDD V V VIH High-level Input Voltage VDD = 4.5–5.5V VDD = 3.0–3.6V VOL Low-level Output Voltage VDD = 4.5–5.5V, IOL= 16 mA VDD = 3.0–3.6V, IOL= 8 mA VOHCMOS High-level Output Voltage, CMOS levels VDD = 4.5–5.5V, IOH= –16 mA VDD = 3.0–3.6V, IOH= –8 mA VDD–0.4 VDD–0.4 V V VOHTTL High-level Output Voltage, TTL levels VDD = 4.5–5.5V, IOH= –8 mA 2.4 V V V 2.0 0.7VDD 0.4 0.4 V V IIL Input Low Current VIN = 0V 10 µA IIH Input High Current VIN = VDD 5 µA IDD Power Supply Current, Unloaded VDD = 4.5–5.5V, Output frequency <= 133 MHz VDD = 3.0–3.6V, Output frequency <= 100 MHz 45 25 mA mA IDDS Stand-by current (PD = 0) VDD = 4.5-5.5V VDD = 3.0-3.6V 25 10 100 50 µA RUP Input Pull-Up Resistor VDD = 4.5–5.5V, VIN = 0V VDD = 4.5–5.5V, VIN = 0.7VDD 3.0 100 8.0 200 MΩ kΩ IOE_CLKOUT CLKOUT Pulldown current VDD=5.0 1.1 50 20 µA Note: 1. When using CyClocks, please note that the PLL frequency range is from 50 MHz to 250 MHz for 5V VDD supply, and 50 MHz to 180 MHz for 3V VDD supply. The output frequency is determined by the selected output divider. 3 CY2077 Output Clock Switching Characteristics Commercial Over the Operating Range[2] Parameter Description Test Conditions Min. Typ. Max. Unit t1w Output Duty Cycle at 1.4V, VDD = 4.5–5.5V t1w = t1A ÷ t1B 1–40 MHz, CL <= 50 pF 40–125 MHz, CL <= 25 pF 125–133 MHz, CL <= 15 pF 45 45 45 55 55 55 % % % t1x Output Duty Cycle at VDD/2, VDD = 4.5–5.5V t1x = t1A ÷ t1B 1–40 MHz, CL <= 50 pF 40–125 MHz, CL <= 25 pF 125–133 MHz, CL <= 15 pF 45 45 45 55 55 55 % % % t1y Output Duty Cycle at VDD/2, VDD = 3.0–3.6V t1y = t1A ÷ t1B 1–40 MHz, CL <= 30 pF 40–100 MHz, CL <= 15 pF 45 40 55 60 % % t2 Output Clock Rise Time Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 50 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 25 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 15 pF Between 0.2VDD– 0.8VDD, VDD= 4.5V–5.5V, CL = 50 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 30 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 15 pF 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t3 Output Clock Fall Time Between 0.8V–2.0V, VDD = 4.5V–5.5V, CL = 50 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 25 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 15 pF Between 0.2VDD– 0.8VDD, VDD= 4.5V-5.5V, CL = 50 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 30 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 15 pF 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t4 Start-Up Time Out of Power-Down PWR_DWN pin LOW to HIGH[3] 1 2 ms t5a Power Down Delay Time PWR_DWN pin LOW to output LOW (synchronous setting) (T=period of output clk) T/2 T+10 ns t5b Power Down Delay Time PWR_DWN pin LOW to output LOW (asynchronous setting) 10 15 ns t6 Power Up Time From power-on[1] 1 2 ms t7a Output Disable Time (synchronous setting) OE pin LOW to output Hi-Z (T=period of output clk) T/2 T+10 ns t7b Output Disable Time (asynchronous setting) OE pin LOW to output Hi-Z 10 15 ns t8 Output Enable Time (always synchronous enable) OE pin LOW to HIGH (T=period of output clk) T 1.5T +25n s ns t9 Peak-to-Peak Period Jitter VDD=3.0V–3.6V, 4.5V–5.5V, Fo>33 MHz, VCO>100 MHz VDD= 3.0V–5.5V, Fo <33 MHz 80 0.3 % 150 1% ps % of FO Notes: 2. Not all parameters measured in production testing. 3. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70Ω. 4 CY2077 Operating Conditions for Industrial Temperature Device Parameter Description Min. Max. Unit VDD Supply Voltage 3.0 5.5 V TA Operating Temperature, Ambient –40 +85 °C CTTL Max. Capacitive Load on outputs for TTL levels VDD = 4.5–5.5V, Output frequency = 1–40 MHz VDD = 4.5–5.5V, Output frequency = 40–125 MHz VDD = 4.5–5.5V, Output frequency = 125–133 MHz 35 15 10 pF pF pF CCMOS Max. Capacitive Load on outputs for CMOS levels VDD = 4.5–5.5V, Output frequency = 1–40 MHz VDD = 4.5–5.5V, Output frequency = 40–125 MHz VDD = 4.5–5.5V, Output frequency = 125–133 MHz VDD = 3.0–3.6V, Output frequency = 1–40 MHz VDD = 3.0–3.6V, Output frequency = 40–100 MHz 35 15 10 20 10 pF pF pF pF pF XREF Reference Frequency, input crystal with Cload = 10 pF 10 30 MHz Reference Frequency, external clock source 1 75 MHz Electrical Characteristics TA = –40°C to +85°C Parameter Description Test Conditions VIL Low-level Input Voltage VDD = 4.5–5.5V VDD = 3.0–3.6V Min. Typ. Max. Unit 0.8 0.2VDD V V VIH High-level Input Voltage VDD = 4.5–5.5V VDD = 3.0–3.6V VOL Low-level Output Voltage VDD = 4.5–5.5V, IOL= 16 mA VDD = 3.0–3.6V, IOL= 8 mA VOHCMOS High-level Output Voltage, CMOS levels VDD = 4.5–5.5V, IOH= –16 mA VDD = 3.0–3.6V, IOH= –8 mA VDD–0.4 VDD–0.4 V V VOHTTL High-level Output Voltage, TTL levels VDD = 4.5–5.5V, IOH= –8 mA 2.4 V IIL Input Low Current VIN = 0V V V 2.0 0.7VDD 0.4 0.4 10 V V µA IIH Input High Current VIN = VDD 5 µA IDD Power Supply Current, Unloaded VDD = 4.5–5.5V, Output frequency <= 133 MHz VDD = 3.0–3.6V, Output frequency <= 100 MHz 45 25 mA mA IDDS Stand-by current (PD = 0) VDD = 4.5-5.5V VDD = 3.0-3.6V 25 10 100 50 µA RUP Input Pull-Up Resistor VDD = 4.5–5.5V, VIN = 0V VDD = 4.5–5.5V, VIN = 0.7VDD 3.0 100 8.0 200 MΩ kΩ IOE_CLKOUT CLKOUT Pulldown current VDD=5.0 1.1 50 20 5 µA CY2077 Output Clock Switching Characteristics Industrial Over the Operating Range[3] Parameter Description Test Conditions Min. Typ. Max. Unit t1w Output Duty Cycle at 1.4V, VDD = 4.5–5.5V t1w = t1A ÷ t1B 1–40 MHz, CL <= 35 pF 40–125 MHz, CL <= 15 pF 125–133 MHz, CL <= 10 pF 45 45 45 55 55 55 % % % t1x Output Duty Cycle at VDD/2, VDD = 4.5–5.5V t1x = t1A ÷ t1B 1–40 MHz, CL <= 35 pF 40–125 MHz, CL <= 15 pF 125–133 MHz, CL <= 10 pF 45 45 45 55 55 55 % % % t1y Output Duty Cycle at VDD/2, VDD = 3.0–3.6V t1y = t1A ÷ t1B 1–40 MHz, CL <= 20 pF 40–100 MHz, CL <= 10 pF 45 40 55 60 % % t2 Output Clock Rise Time Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 35 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 15 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 10 pF Between 0.2VDD– 0.8VDD, VDD= 4.5V–5.5V, CL = 35 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 20 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 10 pF 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t3 Output Clock Fall Time Between 0.8V–2.0V, VDD = 4.5V–5.5V, CL = 35 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 15 pF Between 0.8 –2.0V, VDD = 4.5V–5.5V, CL = 10 pF Between 0.2VDD– 0.8VDD, VDD= 4.5V-5.5V, CL = 35 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 20 pF Between 0.2VDD– 0.8VDD, VDD= 3.0V–3.6V, CL = 10 pF 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t4 Start-Up Time Out of Power-Down PWR_DWN pin LOW to HIGH[1] 1 2 ms t5a Power Down Delay Time PWR_DWN pin LOW to output LOW (synchronous setting) (T=period of output clk) T/2 T+10 ns t5b Power Down Delay Time PWR_DWN pin LOW to output LOW (asynchronous setting) 10 15 ns t6 Power Up Time From power on[1] 1 2 ms t7a Output Disable Time (synchronous setting) OE pin LOW to output Hi-Z (T=period of output clk) T/2 T+10 ns t7b Output Disable Time (asynchronous setting) OE pin LOW to output Hi-Z 10 15 ns t8 Output Enable Time (always synchronous enable) OE pin LOW to HIGH (T=period of output clk) T 1.5T+ 25ns ns t9 Peak-to-Peak Period Jitter VDD=3.0V–3.6V, 4.5V–5.5V, Fo>33 MHz, VCO>100 MHz VDD= 3.0V–5.5V, Fo <33 MHz 80 150 ps 0.3 % 1% % of FO Switching Waveforms Duty Cycle Timing (t1w, t1x, t1y) OUTPUT t1A t1B 6 CY2077 Switching Waveforms (continued) Output Rise/Fall Time VDD OUTPUT 0V t2 t3 Power Down Timing (synchronous and asynchronous modes) POWER DOWN VDD VIH VIL 0V t4 CLKOUT (synchronous[4]) T t5a 1/f CLKOUT (asynchronous[5]) t5b 1/f Power Up Timing VDD POWER UP 0V VDD-10% t6 min 2 ns CLKOUT 1/f Output Enable Timing (synchronous and asynchronous modes) VDD OUTPUT ENABLE VIH VIL 0V T CLKOUT (synchronous[4]) High Impedance t7a CLKOUT (asynchronous[5]) t8 High Impedance t7b t8 Notes: 4. In synchronous mode the power-down or output three-state is not initiated until the next falling edge of the output clock. 5. In asynchronous mode the power-down or output three-state occurs within 25 ns irrespective of position in the ouput clock cycle. 7 CY2077 Ordering Information Ordering Code Type Operating Range CY2077SC-XXX SOIC Commercial CY2077ZC-XXX TSSOP Commercial CY2077SI-XXX SOIC Industrial CY2077ZI-XXX TSSOP Industrial Custom Configuration Request Procedure The CY2077 is an EPROM-programmable device that is configured in the factory. The output frequencies requested will be matched as closely as the internal PLL divider and multiplier options allow. All custom requests must be submitted to your local Cypress Field Application Engineer (FAE) or sales representative. The method to use to request custom configurations is: Use CyClocks™ software of version 3.65 or greater. This software automatically calculates the output frequencies that can be generated by the CY2077 devices and provides a print-out of final pinout which can be submitted (in electronic or print format) to your local FAE or sales representative. The CyClocks software is available free of charge from the Cypress website (http://www.cypress.com) or from your local sales representative. Once the custom request has been processed you will receive a part number with a 3-digit extension (e.g., CY2077SC-103) specific to the frequencies and pinout of your device. This will be the part number used for samples requests and production orders. 8 CY2077 Typical Rise Time[6] and Fall Time[6] Trends for CY2077 Rise/Fall time vs. VDD over Temperatures 2.00 1.80 1.60 1.40 1.20 1.00 Fall Tim e vs. VDD -- CM OS duty Cycle Cload = 15pF Fall Time (ns) Rise Time (ns) Ris e Tim e vs . VDD -- CM OS duty Cycle Cload = 15pF -40C 25C 85C 2.7 3.0 3.3 3.6 2.00 1.80 1.60 1.40 1.20 1.00 3.9 -40C 25C 85C 2.7 3.0 VDD (V ) 0.70 0.60 0.50 0.40 0.30 0.20 -40C 25C 85C 4.5 5.0 3.6 3.9 Fall Tim e vs. VDD -- TTL duty Cycle Cload = 15pF Fall Time (ns) Rise Time (ns) Ris e Tim e vs . VDD -- TTL duty Cycle Cload = 15pF 4.0 3.3 VDD (V) 5.5 0.70 0.60 0.50 0.40 0.30 0.20 6.0 -40C 25C 85C 4.0 4.5 VDD (V) 5.0 5.5 6.0 VDD (V) Rise/Fall time vs. Output Loads over Temperatures Fall Tim e vs . CLoad ove r Te m pe r atur e V DD = 3.3v, CM OS outp ut 2.20 2.00 1.80 1.60 1.40 1.20 1.00 2.00 Fall Time (ns) Rise Time (ns) Ris e Tim e vs . CLoad ove r Te m pe rature V DD = 3.3v, CM OS output -40C 25C 85C 1.80 -40C 1.60 25C 1.40 85C 1.20 1.00 10 15 20 25 30 35 10 Cload (pF) 15 20 25 30 35 Cload (pF) Note: 6. Rise/Fall Time for CMOS output is measured between 1.2 VDD and 0.8 VDD. Rise/Fall Time for TTL output is measured between 0.8V and 2.0V. 9 CY2077 Typical Duty Cycle[7] Trends for CY2077 Duty Cycle vs . V DD ove r Tem pe r ature (TTL Duty Cycle Output, Fout=50MHz, Cload = 50pF) Duty Cycle vs. VDD over Tem perature (CMOS Duty Cycle Ouput, Fout=50MHz, Cload=50pF) 55.00 55.00 53.00 51.00 49.00 47.00 45.00 53.00 51.00 -40C 49.00 47.00 85C Duty Cycle (%) Duty Cycle (%) Duty Cycle vs. VDD over Temperatures 25C 45.00 4.0 4.5 5.0 5.5 Duty Cycle vs. Output Load Duty Cycle vs. CLoad w ith Various VDD (Fout = 50MHz, Temp = 25C) Duty Cycle (%) 85C VDD (v) V DD (V ) VDD=4.5V VDD=5.0V VDD=5.5V 10 15 20 25 30 35 40 45 50 55 Cload (pF) Duty Cycle vs. Output Frequency over Temperatures Output DC (%) 25C 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.0 55.00 53.00 51.00 49.00 47.00 45.00 -40C Output Duty Cycle vs . Fout ove r Te m pe rature (V dd = 5V , Cload = 15pF) 55.00% 54.00% 53.00% 25C 52.00% 85C 51.00% -40C 50.00% 20 30 40 50 60 70 80 Output Fre que ncy (M Hz) Note: 7. Duty Cycle is measured at 1.4V for TTL output and 0.5 VDD for CMOS output. 10 CY2077 Typical Jitter Trends for CY2077 Period Jitter (pk-pk) vs. VDD over Temperatures Period Jitter (pk-pk) vs. VDD over Temperatures (Fout=40MHz, Cload = 30pF) Period JItter (ps) 100 80 60 -40C 40 25C 20 85C 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) Period Jitter (pk-pk) vs. Output Frequency over Temperatures Output Jitter (pk-pk) vs. Output Frequency (VDD=3.3V, Cload=15pf, CMOS output) 100 Jitter (ps) 80 25C 60 -40C 40 85C 20 0 0 20 40 60 80 100 120 140 Output frequency (MHz) Output Jitter(pk-pk) vs. Output Frequency (VDD=5.0V, Cload=15pf, CMOS output) 100 Jitter (ps) 80 25C 60 -40C 40 85C 20 0 0 20 40 60 80 100 120 140 Output frequency (MHz) 11 CY2077 Package Diagrams 8-Lead (150-Mil) SOIC S8 8-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z8 51-85093 Document #: 38-01009-*B © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.