EDI8L3265C 64Kx32 SRAM 64Kx32 CMOS High Speed Static RAM Features 64Kx32 bit CMOS Static Random Access Memory Array • Fast Access Times: 12*, 15, 20, and 25ns • Individual Byte Selects • User Configurable Organization with Minimal Additional Logic • Master Output Enable and Write Control • TTL Compatible Inputs and Outputs • Fully Static, No Clocks Surface Mount Package • 68 Lead PLCC, No. 99 (JEDEC-M0-47AE) • Small Footprint, 0.990 Sq. In. • Multiple Ground Pins for Maximum Noise Immunity The EDI8L3265C is a high speed, high performance, four megabit density Static RAM organized as a 64Kx32 bit array. Four Byte Selects, two Chip Enables, Write Control, and Output Enable provide the user with a flexible memory solution. The user may independently enable each of the four bytes, and, with minimal additional peripheral logic, the unit may be configured as a 128Kx16 array. Fully asynchronous circuitry is used, requiring no clocks or refreshing for operation and providing equal access and cycle times for ease of use. The EDI8L3265C, allows 2 megabits of memory to be placed in less than 0.990 square inches of board space. The EDI8L3265C can be upgraded to 128K, 256K or 512Kx32 in the same footprint using the EDI8L32128, EDI8L32256 or the EDI8L32512C. (See page 6 for upgrade paths). Note: Solder Reflow temperatures should not exceed 260°C for 10 seconds. Single +5V (±5%) Supply Operation * Advance Information 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 DQ16 NC NC BS3\ BS2\ BS1\ BSØ\ E1\ VCC NC EØ\ G\ W\ NC A15 A14 DQ15 Pin Configurations and Block Diagram 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DQ31 A6 A5 A4 A3 A2 A1 AØ VCC A13 A12 A11 A10 A9 A8 A7 DQØ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 VCC DQ7 DQ6 DQ5 DQ4 VSS DQ3 DQ2 DQ1 Pin Names AØ-A15 EØ-E1 BSØ-BS3 W G DQØ-DQ31 VCC VSS NC AØ-A15 G W EØ E1 BSØ BS1 BS2 BS3 Address Inputs Chip Enables (one per word) Byte Selects (One per Byte) Master Write Enable Master Output Enable Common Data Input/Output Power (+5V±5%) Ground No Connection 16 64Kx32 Memory Array Notes: 1. See page 6 for upgrade paths. Electronic Designs Incorporated • One Research Drive • Westborough, MA 01581 USA • 508-366-5151 • FAX 508-836-4850 • http://www.electronic-designs.com 1 EDI8L3265C Rev. 4 3/97 ECO #8302 DQØ-DQ7 DQ8-DQ15 DQ16-DQ23 DQ24-DQ31 Absolute Maximum Ratings* Recommended DC Operating Conditions Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Storage Temperature Power Dissipation Output Current. Junction Temperature, TJ -0.5V to 7.0V 0°C to + 70°C -40°C to +85°C -55°C to +125°C 3.0 Watts 20 mA 175°C *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Sym Supply Voltage VCC Supply Voltage VSS Input High Voltage VIH Input Low Voltage VIL Min 4.75 0 2.2 -0.3 Typ Max Units 5.0 5.25 V 0 0 V -- VCC+0.5 V -0.8 V AC Test Conditions Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VSS to 3.0V 5ns 1.5V Figure 1 (note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF) Figure 1 Figure 2 VCC VCC 480 480 Q Q 255 255 50 pF 5 pF DC Electrical Characteristics Parameter Sym Conditions Operating Power Supply Current Standby (TTL) Supply Current Full Standby Supply Current CMOS Input Leakage Current Output Leakage Current Output High Volltage Output Low Voltage ICC1 W= VIL, II/O = 0mA, Min Cycle E ≥ VIH, VIN ≤ VIL or VIN ≥ VIH, f=ØMHz E ≥ VCC-0.2V VIN ≥ VCC-0.2V or VIN ≤ 0.2V VIN = 0V to VCC V I/O = 0V to VCC IOH = -4.0mA IOL = 8.0mA ICC2 ICC3 ILI ILO VOH VOL Min Max Units 12ns* 15ns 20/25ns ns 500 460 420 mA 60 60 60 mA 20 20 20 mA ±10 ±10 ±10 ±10 ±10 ±10 0.4 0.4 0.4 µA µA V V 2.4 *Typical: TA = 25°C, VCC = 5.0V *Advanced Information Truth Table E W G BSØ-3 Mode H X X X Standby L H H X Output Disable L X X H Output Disable L H L L Read L L X L Write X Means Don't Care Capacitance Output High Z High Z High Z Dout Din Power ICC2,ICC3 ICC1 ICC1 ICC1 ICC1 (f=1.0MHz, VIN=VCC or VSS) Parameter Address Lines Data Lines Write & Output Enable Lines Chip Enable Lines Sym CA CD/Q W, G Max 20 10 16 E, BS 9 These parameters are sampled, not 100% tested. EDI8L3265C 64Kx32 SRAM 2 EDI8L3265C Rev. 4 3/97 ECO#8302 Unit pF pF pF bF pF EDI8L3265C 64Kx32 SRAM AC Characteristics Read Cycle Parameter Read Cycle Time Address Access Time Chip Enable Access Time Byte Select Access Time Chip Enable to Output in Low Z (1) Byte Select to Output in Low Z Chip Disable to Output in High Z (1) Byte Select to Output in High Z Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Symbol 12ns* JEDEC Alt. Min Max TAVAV TRC 12 TAVQV TAA 12 TELQV TACS 12 TBLQV TBA 12 TELQX TCLZ 3 TBLQX TBLZ 3 TEHQZ TCHZ 7 TBHQZ TBHZ 7 TAVQX TOH 3 TGLQV TOE 5 TGLQX TOLZ 2 TGHQZ TOHZ 4 15ns 20ns Min Max Min Max 15 20 15 20 15 20 15 20 3 3 3 3 8 10 8 10 3 3 6 8 2 2 5 8 25ns Min Max 25 25 25 25 3 3 10 10 3 10 0 10 Note 1: Parameter guaranteed, but not tested. * Advanced Information Read Cycle 1 - W High, G, E Low TAVAV ADDRESS 1 A ADDRESS 2 TAVQV Q TAVQX DATA 1 DATA 2 Read Cycle 2 - W High TAVAV A BSx, E TAVQV TELQV TEHQZ TELQX G TGLQV TGHQZ TGLQX Q 3 EDI8L3265C Rev. 4 3/97 ECO #8302 Units ns ns ns ns ns ns ns ns ns ns ns ns AC Characteristics Write Cycle Parameter Write Cycle Time Chip Enable to End of Write Byte Select to end of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Symbol 12ns* JEDEC Alt. Min Max TAVAV TWC 12 TELWH TCW 8 TELEH TCW 8 TBLWH TBW 8 TAVWL TAS 0 TAVEL TAS 0 TAVWH TAW 9 TAVEH TAW 9 TWLWH TWP 9 TWLEH TWP 9 TWHAX TWR 0 TEHAX TWR 0 TWHDX TDH 0 TEHDX TDH 0 TWLQZ TWHZ 0 5 TDVWH TDW 5 TDVEH TDW 5 TWHQX TWLZ 2 15ns 20ns Min Max Min Max 15 20 9 15 9 15 9 15 0 0 0 0 10 15 10 15 10 15 10 15 0 0 0 0 0 0 0 0 0 6 0 7 6 8 6 8 2 2 25ns Min Max 25 20 20 20 0 0 15 15 15 15 0 0 0 0 0 10 12 12 2 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Parameter guaranteed, but not tested. * Advanced Information Write Cycle 1 - W Controlled TAVAV A BSx, E TELWH TAVWH TWHAX TWLWH W TAVWL TDVWH D TWHDX DATA VALID TWLQZ HIGH Z Q EDI8L3265C 64Kx32 SRAM 4 EDI8L3265C Rev. 4 3/97 ECO#8302 TWHQX EDI8L3265C 64Kx32 SRAM Write Cycle 2 - E Controlled TAVAV A TAVEL TELEH BSx, E TEHAX TAVEH TWLEH W TDVEH TEHDX DATA VALID D HIGH Z Q Ordering Information Commercial (0°C to 70°C) Part Number EDI8L3265C12AC* EDI8L3265C15AC EDI8L3265C20AC EDI8L3265C25AC Industrial (-40°C to +85°C) Speed (ns) 12 15 20 25 Part Number Package No. 99 99 99 99 Speed (ns) 15 20 25 EDI8L3265C15AI EDI8L3265C20AI EDI8L3265C25AI *Advanced Information Package Description Package No. 99 68 Lead PLCC JEDEC M0-47AE 0.995 Max 0.956 Max 0.995 Max 0.956 Max 0.180 Max 0.040 Max 0.020 0.015 0.930 0.890 5 EDI8L3265C Rev. 4 3/97 ECO #8302 0.050 BSC 0.115 Max Package No. 99 99 99 EDI MCM-L Upgrade Path Electronic Designs Incorporated • One Research Drive • Westborough, MA 01581USA • 508-366-5151 • FAX 508-836-4850 • http://www.electronic-designs.com Electronic Designs Inc. reserves the right to change specifications without notice. CAGE No. 66301 64Kx32 SRAM 6 EDI8L3265C Rev. 4 3/97 ECO#8302 EDI8L3265C