EDI8F32256C 256Kx32 Static RAM CMOS, High Speed Module FEATURES DESCRIPTION 256Kx32 bit CMOS Static The EDI8F32256C is a high speed 8Mb Static RAM module organized as 256K words by 32 bits. This module is constructed from eight 256Kx4 Static RAMs in SOJ packages on an epoxy laminate (FR4) board. Random Access Memory Access Times: 12, 15, 20, and 25ns Individual Byte Selects Four chip enables (EØ-E3) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. Fully Static, No Clocks TTL Compatible I/O High Density Package with JEDEC Standard Pinouts The EDI8F32256C is offered in 64 pin ZIP/SIMM package which enables eight megabits of memory to be placed in less than 1.4 square inches of board space. 64 Pin ZIP, No. 85 64 Lead Angled SIMM, No. 32 All inputs and outputs are TTL compatible and operate from a single 5V supply. Fully asynchronous circuitry requires no clocks or refreshing for operation and provides equal access and cycle times for ease of use. 64 Lead SIMM, No. 333 Common Data Inputs and Outputs Single +5V (±10%) Supply Operation The ZIP and SIMM modules contain two pins, PD1 and PD2, which are used to identify module memory density in applications where alternate modules can be interchanged. FIG. 1 PIN NAMES PIN CONFIGURATIONS AND BLOCK DIAGRAM Aug. 2001 Rev. 13 ECO #14561 1 AØ-A17 Address Inputs EØ-E3 Chip Enables W, Write Enables G Output Enable DQØ-DQ31 Common Data Input/Output VCC Power (+5V±10%) VSS Ground White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F32256C ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Storage Temperature, Plastic Power Dissipation Output Current RECOMMENDED DC OPERATING CONDITIONS -0.5V to 7.0V Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage 0°C to +70°C -40°C to +85°C -55°C to +125°C 8.0 Watt 20 mA *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Sym VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 --- Max Units 5.5 V 0 V VCC+0.3V V 0.8 V AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VSS to 3.0V 5ns 1.5V 1TTL, CL = 30pF (note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF) DC ELECTRICAL CHARACTERISTICS Parameter Sym Conditions Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current CMOS ICC1 ICC2 ICC3 W, E = VIL, II/O = 0mA, Min Cycle E ³ VIH, VIN £ VIL or VIN ³VIH E ³ VCC-0.2V VIN ³ VCC-0.2V or VIN £ 0.2V Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage ILI ILO VOH VOL VIN = 0V to VCC V I/O = 0V to VCC IOH = -4.0mA IOL = 8.0mA Min Max 12-25 800 240 40 Units ns mA mA mA --2.4 ±80 ±20 0.4 µA µA V V *Typical: TA = 25°C, VCC = 5.0V CAPACITANCE TRUTH TABLE E H L L L W X H L H G X L X H Mode Standby Read Write Output Deselect (f=1.0MHz, VIN=VCC or VSS) Output HIGH Z DOUT DIN HIGH Z Power ICC3 ICC1 ICC1 ICC1 Parameter Address Lines Data Lines Chip Enable Line Write Control Line Sym CI CD/Q CC CN Max 60 20 20 60 Unit pF pF pF pF These parameters are sampled, not 100% tested. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 2 Aug. 2001 Rev. 13 ECO #14561 EDI8F32256C AC CHARACTERISTICS READ CYCLE Parameter Symbol JEDEC Alt. 12ns Min Max 15ns Min Max Min Read Cycle Time TAVAV 12 15 20 TRC 20ns Max 25ns Min Max 25 Units ns Address Access Time TAVQV TAA 12 15 20 25 ns Chip Enable Access TELQV TACS 12 15 20 25 ns Chip Enable to Output in Low Z (1) TELQX TCLZ Chip Disable to Output in High Z (1) TEHQZ TCHZ Output Hold from Address Change TAVQX TOH Output Enable to Output Valid TGLQV TOE Output Enable to Output in Low Z (1) TGLQX TOLZ Output Disable to Output in High Z (1) TGHQZ TOHZ 3 3 6 3 7 3 3 6 3 7 0 0 6 3 9 3 9 0 7 ns 9 ns 9 ns 9 ns 0 9 ns ns Note 1: Parameter guaranteed, but not tested. FIG. 2 READ CYCLE 1 - W HIGH, G, E LOW TAVAV A ADDRESS 1 ADDRESS 2 TAVQV TAVQX Q DATA 2 DATA 1 FIG. 3 READ CYCLE 2 - W HIGH TAVAV A TAVQV E TELQV TEHQZ TELQX G TGLQV TGHQZ TGLQX Q Aug. 2001 Rev. 13 ECO #14561 3 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F32256C AC CHARACTERISTICS WRITE CYCLE Parameter Symbol JEDEC Alt. 10ns Min Max 12ns Min Max Min Write Cycle Time TAVAV TWC 10 12 Chip Enable to End of Write TELWH TWLEH TCW TCW 7 7 Address Setup Time TAVWL TAVEL TAS TAS Address Valid to End of Write TAVWH TAVEH Write Pulse Width 20ns Min Max 25ns Min Max 15 20 25 ns 8 8 12 10 10 10 10 10 ns ns 0 0 0 0 0 0 0 0 0 0 ns ns TAW TAW 7 7 8 8 10 10 10 10 10 10 ns ns TWLWH TELEH TWP TWP 7 7 8 8 10 10 10 10 10 10 ns ns Write Recovery Time TWHAX TEHAX TWR TWR 0 0 0 0 0 0 0 0 0 0 ns ns Data Hold Time TWHDX TEHDX TDH TDH 3 3 3 3 3 3 3 3 3 3 ns ns 5 0 6 0 15ns Max 9 0 9 0 9 Units Write to Output in High Z (1) TWLQZ TWHZ 0 Data to Write Time TDVWH TDVEH TDW TDW 5 5 6 6 7 7 8 8 8 8 ns ns ns Output Active from End of Write (1) TWHQX TWLZ 3 3 3 3 3 ns Note 1: Parameter guaranteed, but not tested. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 4 Aug. 2001 Rev. 13 ECO #14561 EDI8F32256C FIG. 4 WRITE CYCLE 1 - W CONTROLLED TAVAV A E TELWH TWHAX TAVWH TWLWH W TAVWL TDVWH D TWHDX DATA VALID TWHQX TWLQZ HIGH Z Q FIG. 5 WRITE CYCLE 2 - E CONTROLLED TAVAV A TAVEL TELEH E TAVEH TEHAX TWLEH W TDVEH D Q Aug. 2001 Rev. 13 ECO #14561 TEHDX DATA VALID HIGH Z 5 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F32256C ORDERING INFORMATION Part Number EDI8F32256C12MNC EDI8F32256C15MNC EDI8F32256C20MNC EDI8F32256C25MNC EDI8F32256C12MMC EDI8F32256C15MMC EDI8F32256C20MMC EDI8F32256C25MMC EDI8F32256C12MZC EDI8F32256C15MZC EDI8F32256C20MZC EDI8F32256C25MZC Speed (ns) 12 15 20 25 12 15 20 25 12 15 20 25 Package No. 32 32 32 32 333 333 333 333 85 85 85 85 NOTE: 1. For Gold SIMM change form EDI8F to EDI8G. PACKAGE DESCRIPTION PACKAGE NO. 32: 64 LEAD ANGLED SIMM White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 6 Aug. 2001 Rev. 13 ECO #14561 EDI8F32256C PACKAGE NO. 85: 64 PIN ZIP NS G I S E WD E N R D FO E D N MME O C E NOT R PACKAGE NO. 333: 64 LEAD SIMM ALL DIMENSIONS ARE IN INCHES Aug. 2001 Rev. 13 ECO #14561 7 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com