ETC HFCT

Agilent HFCT-701XB, 10 Gb Ethernet,
1310 nm, 10 km 10GBASE-LR, XENPAK
LAN-PHY
Data Sheet
Description
The HFCT-701XB is an
“intelligent” optical module
which incorporates the complete
physical layer functionality from
the 10.3125 Gb/s 64B/66B
encoded optical interface to a
XAUI compliant (4 channel x
3.125 Gb/s) 8B/10B encoded
electrical interface and vice
versa. The control interface
(MDIO) is also integrated.
The HFCT-701XB module
includes a transmitter that
incorporates an uncooled,
directly modulated 1310 nm
DFB laser. The receiver
subassembly includes a highly
reliable PIN photodiode. The
MUX/DEMUX, XAUI interface
and MDIO management
functions are all integrated into
the module, as is a precision
oscillator that removes any need
for an external reference clock.
Features
· IEEE Std 802.3ae type 10GBASELR PMD (10 Gigabit Ethernet
standard)
· Compliant with XENPAK MSA
Draft 3.0
· Standard SC Duplex fiber optic
connector
· Standard 70 pin electrical
connector
· Four wide XAUI Electrical
interface
· MDIO Management Interface
· Only 3.3 V and 1.8 V supplies
required (compatible with the
XENPAK APS)
· 5 diagnostic loopback modes
· Front panel hot pluggable
· Excellent thermal and EMI
integrity performance supports
high port densities
· Hot plug power up circuit
removes PSU sequence
dependency and reduces inrush
current
· Precision onboard oscillator - no
external clocks required
Applications
· Enterprise to Metro Uplinks
· Campus Trunking
· Data Aggregation
· Exchange Point-to-Point Links
Table of Contents
General Specifications
General Optical Specifications
General Electrical Specifications
Environmental Specifications
3
3
3
Technical Specifications
Absolute Maximum Ratings
Typical Operating Conditions
Optical Specifications
Electrical Control and Sense I/O Parameters
Electrical Specifications
Mechanical Specifications
4
4
5
5
8
13
Functional Descriptions
Block Diagram
Transmitter Path Summary
Receiver Path Summary
Management Data Input Output (MDIO) Interface
EEPROM Interface
Monitor and Diagnostic Features
Loopbacks
Reset Operation
Internal Clock Functionality
17
17
18
18
19
21
24
24
26
HFCT-701XB Registers
HFCT-701XB Device 1 PMA/PMD Registers
HFCT-701XB Device 3 PCS Registers
HFCT-701XB Device 4 PHYXS Registers
28
42
48
Regulatory Compliance
Electrostatic Discharge (ESD)
Electromagnetic Interference (EMI)
Immunity
53
53
53
Glossary
53
2
General Specifications
8B/10B
3.125 x 4
SerDes
Electrical Connector
MAC
with
RS
Other Signals
Agilent HFCT-701XB
MDIO
Opto
10G
8B/10B
3.125 x 4 64B/66B SerDes
SerDes
Opto
Figure 1. High level block diagram
General Optical Specifications
Optical Connector:
SC Duplex
Optical Line rate:
10.3125 Gb/s
Link Length:
10 km, with G.652 fiber
Laser:
1310 nm, directly modulated,
uncooled DFB
Detector:
PIN diode
3
General Electrical Specifications
Connector:
70-pin, mates to Tyco/AMP Part
No. 1367337-1 or equivalent
Supply Voltages:
+1.8 V and +3.3 V
E->O Coding (Transmit
Direction):
8B/10B coding removed, 64B/
66B added
O->E Coding (Receive
Direction):
64B/66B
removed, 8B/10B coding added
XAUI interface:
100 W Differential, AC- coupled
I/O on Tx and Rx, per IEEE
802.3ae Clause 47
Control interface:
MDIO, 1.2 V, per IEEE 802.3ae
Clause 45.3
Non Volatile memory:
48 byte user space
Environmental Specifications
Operating temperature:
0 °C to +70 °C case
Power consumption:
6.0 W maximum
Optical Connectors
System
Control
Technical Specifications
Absolute Maximum Ratings1
Parameter
Minimum
Storage Temperature
Operating Temperature
Maximum
Units
0
85
°C
0
70
°C
Supply Voltage (3.3 V)
3.6
V
Supply Voltage (1.8 V)
2.0
V
Voltage on any XAUI pin
2.5
V
4.0
V
Typical
Maximum
Units
0.5
5
sec
Voltage on any LVCMOS pin
Typical
-0.7
Notes
Case temperature
Recommended Operating Conditions2
Parameter
Minimum
Stabilization Time
Input Voltage
3.135
3.3
3.465
V
Input Voltage (APS)
1.71
1.8
1.89
V
Supply Current (@ 3.3 V)
1.5
1.6
A
Supply Current (@ 1.8 V)
0.15
0.4
A
Power Consumption
5.2
6.0
W
Inrush current during hot plug
50
mA/ms
Inrush current (per power pin)
0.75
A
Conditions
150% x 0.5A steady state
rating
Notes:
1. Absolute maximum ratings are those values beyond which functional performance is not intended, device reliability is not implied, and damage to the
device may occur.
2. Typical operating conditions are those values for which functional performance and device reliability is implied.
4
Optical Specifications
Parameter
Minimum
Typical
Maximum
Units
Notes
dBm OMA
1, 2
Transmitter
Laser OMA output power
-5.2
Laser mean output power
-8.2
0.5
dBm mean
1, 2, 3
Extinction ratio
3.5
-
dB
1, 2
Wavelength
1260
1355
nm
3.2
dB
1, 2
Transmitter and dispersion penalty
(TDP)
Side mode suppression ratio
30
dB
1
OMA - TDP
-6.2
dBm OMA
1, 2
1
RIN12OMA
-128
dB/Hz
Optical Return Loss
12
dB
TX eye definition
See Figure 2
Receiver
Stressed sensitivity
-
-10.3
dBm OMA
1
Nominal sensitivity
-
-12.6
dBm OMA
1, 3
Receive Power Overload
0.5
dBm mean
1, 4
-12
dB
1
1355
nm
1
Reflectance loss
Wavelength
1260
Signal detect On
-30
Signal detect Off
Signal detect Hysteresis
dBm
-16
0.5
dBm
dB
General Specification
Considerations (Notes)
1. IEEE 802.3ae compliant.
2. These parameters are
interrelated: see IEEE
802.3ae.
3. Information purposes only.
4. Up to 1.5 dB without damage.
Note: where X1, X2, X3, Y1, Y2, Y3 = 0.25, 0.40, 0.45, 0.25, 0.28, 0.40 respectively
Figure 2. Transmitter Eye Mask Definition
5
Electrical Control and Sense I/O Parameters
Table 1 - CMOS DC Parameters (MDC, PRTAD<4:0>, LASI)
Parameter
Description
Vol
Output low voltage
Voh
Output high voltage
Vih
Input high voltage
Vil
Input low voltage
Ipd
Input pad pulldown current
Trise
Rise time
Tfall
Fall time
Minimum
Maximum
Units
Conditions
0.15
V
ext. Rpullup = 10 kW
to 1.2 V
1.0
1.5
V
ext. Rpullup = 10 kW
to 1.2V
0.84
1.25
V
0.36
V
120
µA
Vin = 1.2 V
30
us
Cload = 300 pF
25
50
ns
Cload = 300 pF
Typical
Maximum
Units
Conditions
20
Typical
40
Electrical MDIO Parameters
Table 2 - MDIO 1.2 V dc parameters
Parameter
Description
Minimum
Voh
Output high voltage
1.0
1.5
V
Ioh = -100 uA
Vol
Output low voltage
-0.3
0.2
V
Iol = +100 uA
Iol
Output low current
-4
mA
Vin = 0.3
Vih
Input high voltage
0.84
1.5
V
Vil
Input low voltage
-0.3
0.36
V
Cin
Input capacitance
10
pF
Maximum
Units
Table 3 - MDIO AC Parameters
Parameter
Description
Minimum
Thold
MDIO data hold time
10
ns
Tsetup
MDIO data setup time
10
ns
Tdelay
Delay from MDC rising edge to
MDIO data change
0
Fmax
Maximum MDC clock rate
6
Typical
300
ns
2.5
MHz
Conditions
Electrical High Speed I/O Parameters
Table 4 - 3.125 Gb/s XAUI Input Interface
Parameter
Description
Minimum
BAUD rate
Typical
Maximum
3.125
Units
Conditions
Gb/s
BAUD rate tolerance
-100
100
ppm
Differential input amplitude
200
2500
mVpp
Note 1
Differential return loss
-10
dB
100 MHz to 2.5 GHz ref
to 100W impedance
Common mode return loss
-6
dB
100 MHz to 2.5 GHz ref
to 25W
Input Differential Skew
75
ps P-P
at crossing point, Note 2
Jitter amplitude tolerance
deterministic + random jitter +
Sj jitter
0.55 + Sj
UIpp
See Figure 2a for SJ
jitter graph
Maximum
Units
Table 5 - 3.125 Gb/s XAUI Driver Characteristics
Parameter
Description
Minimum
BAUD rate
Typical
3.125
Conditions
Gb/s
BAUD rate variation
-100
100
ppm
Differential amplitude
800
1600
mVpp
Transition times (20-80%)
60
130
ps
Note 2
Total output jitter
± 0.175
UI
no pre-equalization
Output deterministic jitter
± 0.085
UI
no pre-equalization
Output differential skew
15
ps
at crossing point
dB
312.5 MHz to 625
MHz: -10 dB
625 MHz to 3.125 GHz:
as per equation 47-1
IEEE 802.3ae
Differential output return loss
Electrical eye mask
90
See Figure 3
Note:
1. Maximum amplitude of 2500 mVpp is the combined effect of the driver maximum output signal of 1600 mVpp and the receiver input impedance
mismatch.
2. For information only.
Figure 2a. Single-tone sinusoidal jitter mask
7
Electrical Eye Mask
DIFFERENTIAL AMPLITUDE (mV)
800
400
0
-400
-800
0
X1 = 0.175
1
X2 = 0.390 1-X2 = 0.610
TIME IN UI
Figure 3 - XAUI Driver Near End Template
General Connector Considerations
1. Ground connections are
common for Tx and Rx.
2. VCC contacts are each rated at
0.5 A nominal.
3. See Figure 8 for layout of Host
PCB and location of Pin1.
8
1-X1 = 0.825
Table 6 - General I/O Pin Summary
Signal Type
Pins
Direction
Function
Power Supply Pins
Ground
1:3, 33:37, 40, 43, 46, 49, 52:54, 57,
60, 63, 66, 69:70
Electrical ground
3.3 V
5:6, 30:31
I
3.3 V power supply
5.0 V
4, 32
I
5.0 V power supply not used
Adaptive power supply
7:8, 28:29
I
Adaptive power supply (1.8 V)
Adaptive power supply set
25
I
APS set ccnnection
Adaptive power supply sense
27
I
APS sense connection
LASI
9
O
1.2 V CMOS pull up on host
Reset
10
I
1.2 V CMOS pull up on module
Transmitter ON/OFF
12
I
1.2 V CMOS pull up on module
Port address 4:0
19:23
I
1.2 V CMOS pull up on module
MOD DETECT
14
O
1 kW pull down to ground on
module
Management data IO
17
I/O
1.2 V per IEEE802.3ae clause 45.3
Management data clock
18
I
1.2 V per IEEE802.3ae clause 45.3
Receiver lane 0:3 +
41, 44, 47, 50
O
XAUI per IEEE802.3ae clause 47
Receiver lane 0:3 -
42, 45, 48, 51
O
XAUI per IEEE802.3ae clause 47
Transmitter lane 0:3 +
55, 58, 61, 64
I
XAUI per IEEE802.3ae clause 47
Transmitter lane 0:3 -
56, 59, 62, 65
I
XAUI per IEEE802.3ae clause 47
Control & Sense I/O Pins
MDIO Pins
High Speed I/O Pins
Non Connected Pins
Not connected
9
4, 11, 13, 15:16, 24, 26, 32, 38:39,
67:68
NC on module
Electrical Pin Out
70
GND
1
GND
69
GND
2
GND
68
NOT CONNECTED
3
GND
67
NOT CONNECTED
4
5.0V
66
GND
5
3.3V
65
TX LANE3-
6
3.3V
64
TX LANE3+
7
APS
63
GND
8
APS
62
TX LANE2-
9
LASI
61
TX LANE2+
10
RESET
60
GND
11
NOT CONNECTED
59
TX LANE1-
12
TX ON/OFF
58
TX LANE1+
13
NOT CONNECTED
57
GND
14
MOD DETECT
56
TX LANE0-
15
NOT CONNECTED
55
TX LANE0+
16
NOT CONNECTED
54
GND
17
MDIO
53
GND
18
MDC
52
GND
19
PRTAD4
51
RX LANE3-
20
PRTAD3
50
RX LANE3+
21
PRTAD2
49
GND
22
PRTAD1
48
RX LANE2-
23
PRTAD0
47
RX LANE2+
24
NOT CONNECTED
46
GND
25
APS SET
45
RX LANE1-
26
NOT CONNECTED
44
RX LANE1+
27
APS SENSE
43
GND
28
APS
42
RX LANE0-
29
APS
41
RX LANE0+
30
3.3V
40
GND
31
3.3V
39
NOT CONNECTED
32
5.0V
38
NOT CONNECTED
33
GND
37
GND
34
GND
36
GND
35
GND
Figure 4. Electrical Pin Out
10
Electrical Pin Out Definitions
Table 7 - Pin Function Definitions (Lower Row)
Pin No
Name
1
GND
Electrical ground
2
GND
Electrical ground
3
GND
Electrical ground
4
NOT CONNECTED
5.0 V power supply
5
3.3 V
I
3.3 V power supply
6
3.3 V
I
3.3 V power supply
7
APS
I
Adaptive power supply (1.8 V)
8
APS
I
Adaptive power supply (1.8 V)
9
LASI
O
Logic high: normal operation
Logic low: LASI asserted
10
RESET
I
Logic high: normal operatio
Logic low: reset
11
NOT CONNECTED
12
TX ON/OFF
I
Pulled up inside module via 10 kW
Logic high: transmitter on
Logic low: transmitter off
13
NOT CONNECTED
14
MOD DETECT
O
Pulled low inside module through 1 k to GND
15
NOT CONNECTED
16
NOT CONNECTED
17
MDIO
I/O
Management data IO
18
MDC
I
Management data clock
19
PRTAD4
I
Port address bit 4
20
PRTAD3
I
Port address bit 3
21
PRTAD2
I
Port address bit 2
22
PRTAD1
I
Port address bit 1
23
PRTAD0
I
Port address bit 0
24
NOT CONNECTED
25
APS SET
I
APS set connection
26
NOT CONNECTED
27
APS SENSE
I
APS sense connection
28
APS
I
Adaptive Power Supply (1.8 V)
29
APS
I
Adaptive Power Supply (1.8 V)
30
3.3 V
I
Power
31
3.3 V
I
Power
32
NOT CONNECTED
5.0 V Power Supply
33
GND
Electrical Ground
34
GND
Electrical Ground
35
GND
Electrical Ground
11
Direction
Function
Note
See Table 10
Table 8 - Pin Function Definitions (Upper Row)
Pin No
Name
36
GND
Electrical Ground
37
GND
Electrical Ground
38
NOT CONNECTED
39
NOT CONNECTED
40
GND
41
RX LANE 0+
O
Module XAUI Output Lane 0+
42
RX LANE 0-
O
Module XAUI Output Lane 0-
43
GND
44
RX LANE 1+
O
Module XAUI Output Lane 1+
45
RX LANE 1-
O
Module XAUI Output Lane 1-
46
GND
47
RX LANE 2+
O
Module XAUI Output Lane 2+
48
RX LANE 2-
O
Module XAUI Output Lane 2-
49
GND
50
RX LANE 3+
O
Module XAUI Output Lane 3+
51
RX LANE 3-
O
Module XAUI Output Lane 3-
52
GND
Electrical Ground
53
GND
Electrical Ground
54
GND
Electrical Ground
55
TX LANE 0+
I
Module XAUI Input Lane 0+
56
TX LANE 0-
I
Module XAUI Input Lane 0-
57
GND
58
TX LANE 1+
I
Module XAUI Input Lane 1+
59
TX LANE 1-
I
Module XAUI Input Lane 1-
60
GND
61
TX LANE 2+
I
Module XAUI Input Lane 2+
62
TX LANE 2-
I
Module XAUI Input Lane 2-
63
GND
64
TX LANE3+
I
Module XAUI Input Lane 3+
65
TX LANE3-
I
Module XAUI Input Lane 3-
66
GND
67
NOT CONNECTED
68
NOT CONNECTED
69
GND
Electrical Ground
70
GND
Electrical Ground
12
Direction
Function
Electrical Ground
Electrical Ground
Electrical Ground
Electrical Ground
Electrical Ground
Electrical Ground
Electrical Ground
Electrical Ground
Note
Mechanical Specifications
Package Dimensions
Figure 5.
Note:
It is recommended that the user refers to the XENPAK MSA at www.xenpak.org for full mechanical detail.
13
Dimensions Table (Figure 5)
Key
Values
Tolerance
Comments
mm
inch
mm
A1
51.3
2.020
±0.20
Width of Bezel overall
B1
22.4
0.882
±0.20
Height of Bezel overall
E1
20.75
0.817
Maximum
Extension of captive screw
F1
36.0
1.417
±0.20
Width of Transceiver body
K1
(121.0)
4.764
REF
Length of Transceiver overall minus protruding captive screw heads
L1
5.00
0.197
±0.20
Length of captive screw from Datum "D" to end of threaded end
N1
5.8
0.228
±0.20
Datum "D" to front of Transceiver Bezel
V1
7.92
0.312
±0.20
Datum "E" to Bottom of Transceiver Bezel
Y1
102.20
4.024
±0.20
Datum "D" to Datum "B"
AA1
3.0
0.118
±0.50
Datum "B" to end of 45° chamfer
BB1
(115.2)
4.535
REF
Length of Module from Datum "D" to rear Over-hanging Ledge
LL1
25.8
1.016
Maximum
Length of Thumbscrew
14
Figure 6.
15
Note:
Case Ground is separated from the common Rx and Tx signal ground
Figure 7.
16
Pin1
Figure 8. Host board layout for 70 pin connector
17
Functional Descriptions
System
Control
Transmitter Path Summary
Figure 10 shows a block diagram
of the transmit path, from the
four XAUI differential inputs to
the optical output. The
incoming 4 x 3.125 Gb/s XAUI
differential 8B/10B encoded
electrical inputs, are
reformatted and transmitted
onto the outgoing fiber optic
interface at 10.3125 Gb/s, using
64B/66B encoding.
Electrical Connector
Other Signals
HFCT-701XB
MDIO
8B/10B
3.125 x 4
SerDes
Opto
10G
SerDes
64B/66B
Figure 9. Block Diagram of HFCT-701XB
Optical Connectors
Block Diagram
Figure 9 shows a block diagram
of the HFCT-701XB. Figures 10
and 11 show greater detail of the
transmitter and receiver paths.
Opto
Tx
XTAL
XAUI LANE 2
XAUI LANE 3
Figure 10. Transmit Path High Level Overview
18
Mux
Rate Adjust & Frame
Rate adjust by add drop
off ¦R¦ character
39 +X 58
Scrambler 1+X
XAUI LANE 1
64B/66B 1:0 Block sync
64B/66B Encoder
PLL
8B/10B Decoder
CDR
Lane Alignment, with ¦A¦ character.
XAUI
LANE 0
SIPO and code word
alignment, with ¦K¦ char
PLL
Tx
Opto
Receiver Path Summary
Figure 11 shows a block diagram
of the receiver path, from the
incoming 10.3125 Gb/s, 64B/66B
encoded optical interface to the
four 3.125 Gb/s differential 8B/
10B encoded XAUI electrical
output interface. The XAUI
output drivers provide lowswing differential output with
100 W differential output
impedance and are ac coupled.
Management Data Input/Output
(MDIO) Interface
The MDIO interface provides a
simple, two wire, serial interface
to connect a station
management entity (STA) and a
managed PHY for the purpose of
controlling the PHY and
gathering status from the PHY.
The management interface
consists of the two wire physical
interface, a frame format, a
protocol specification for
exchanging the frames and a
register set that can be read and
written using these frames. The
two wires of the physical
interface are the Management
Data Clock (MDC) and the
Management Data I/O (MDIO).
Management Data Clock (MDC)
The MDC is sourced by the
Station Management entity
(STA) to the PHY as the timing
reference for transfer of
information on the MDIO signal.
MDC is an aperiodic signal that
has no maximum high or low
times.
Management Data I/O (MDIO)
MDIO is a bidirectional signal
between the PHY (HFCT-701XB)
and the STA. It is used to
transfer control and status
information. Data is always
driven and sampled
synchronously with respect to
MDC. Figure 13 shows that
MDIO open drain driver
configuration.
MDIO Timing relationship to MDC
MDIO is a bidirectional signal
that can be sourced by the STA
or the HFCT-701XB. When the
STA sources the MDIO signal,
the STA shall provide a
minimum of 10 ns of setup time
and a minimum of 10 ns of hold
time referenced to the rising
edge of MDC (see Figure 12).
When the MDIO signal is sourced
by the HFCT-701XB, it is
sampled by the STA
synchronously with respect to
the rising edge of MDC. The
clock output delay from the
HFCT-701XB shall be a
minimum of 0 ns and a
maximum of 300 ns.
MDC
tsu=10 ns min
MDIO
(STA Sourced)
Data Valid
thd=10 ns min
MDC
MDIO
(HFCT-701xB Sourced)
Data Valid
tpd=0 ns min, 300 ns max
XAUI LANE 2
Clock for Rx 10G path
XAUI LANE 3
Figure 11. Receive Path High Level Overview
19
CDR
De Mux
+X 58
39
Frame Recovery (block sync)
XAUI LANE 1
Descrambler 1+X
PLL
64B/66B Decoder
XTAL
8B/10B
Encoder
Driver
Mux
XAUI LANE 0
Rate adjust
Figure 12. MDIO/MDC Timing
Rx
Opto
Management Frame Format
The HFCT-701XB has an internal
address register which is used to
store the address for MDIO reads
and writes. This MDIO address
register can be set by using an
address frame that specifies the
register address to be accessed
within a particular port device.
The following write, read or a
post-read-increment-address
frame to the same port device
shall access the register whose
address is stored in the HFCT701XB MDIO address register.
An address frame should be
followed immediately by its
associated write, read or postread-increment-address frame.
Upon receiving a post-readincrement-address frame and
having completed the read
operation, the HFCT-701XB
shall increment and store the
address of the register accessed.
If no address cycle is received
before the next write, read or
post-read-increment-address
frame, then the HFCT-701XB
shall use the stored address for
that register access.
The Management Frame Format
for Indirect Access is specified
in Table 9.
PRE - Preamble
At the beginning of each
transaction the STA shall send a
preamble sequence of 32
contiguous logic one bits on
MDIO with 32 corresponding
cycles on MDC, to provide the
HFCT-701XB with a pattern that
it can use to establish
synchronization. The HFCT701XB must observe this
preamble sequence before it
responds to any transaction.
ST - Start
The Start of Frame is indicated
by a <00> pattern. This pattern
ensures transitions from the
default logic one line to zero and
back to one.
20
1.2 V
pullup, R>100 Ohms
receive buffer
external
capacitance loading
C< 700 pF
MDIO pin
Open drain
driver
COREGND
Figure 13. MDIO open Drain Driver Configuration
Table 9. Frame Format
Management Frame Fields
FRAME
PRE
ST OP
PRTAD
DEVAD
TA
ADDR/DATA
IDLE
ADDRESS
1...1
00
00
PRTAD[4:0]
DA[4:0]
10
D[15:0]
Z
WRITE
1...1
00
01
PRTAD[4:0]
DA[4:0]
10
D[15:0]
Z
READ
1...1
00
11
PRTAD[4:0]
DA[4:0]
Z0
D[15:0]
Z
READ INC
1...1
00
10
PRTAD[4:0]
DA[4:0]
Z0
D[15:0]
Z
OP - Operation Code
Table 10. OP Code Definitions
OP Code
Operation
00
Register Address
01
Write Data
11
Read Data
10
Post Read Data +
Increment
PRTAD
The Port Address is five bits,
allowing 32 unique port
addresses. HFCT-701XB’s port
address is set through pins
PRTAD<0:4>.
DEVAD
The Device Address is five bits,
allowing 32 unique devices per
port. The HFCT-701XB supports
device addresses 1 (PMA/PMD),
3 (PCS) and 4 (PHY XS).
TA
The Turnaround time is a two
bit time spacing between the
Register Address field and the
Data field of a management
frame to avoid contention during
a read transaction (see IEEE
802.3ae).
ADDR/DATA
The Data/Address field is 16
bits. The first bit transmitted/
received is bit 15 and the last bit
is bit 0.
IDLE
The idle condition is a highimpedance state. The MDIO line
will be pulled to a one.
EEPROM Interface
NVR
There are two main memory/
register types in the HFCT701XB which comply with the
IEEE 802.3ae and XENPAK
standard: volatile and
nonvolatile. These areas can be
further divided into user
readable and writeable areas.
At power up the module register
space is initialized and, where
appropriate, default values are
loaded from the non user
accessible nonvolatile memory.
The user accessible nonvolatile
memory is also uploaded
entirely into the user accessible
volatile memory.
DEVICE MANAGEMENT INTERFACE - ADDRESS FRAME STRUCTURE
MDC
MDIO Write
32 "1"s
0
Idle Preamble
0
ST
0
0
Op Code
A4
A3
A0
PHY Address
R4
R3
R0
1
0
A15 A14 A1
Register Address Turn Around
A0
Address
Idle
Write
DEVICE MANAGEMENT INTERFACE - WRITE FRAME STRUCTURE
MDC
MDIO Write
32 "1"s
0
Idle Preamble
0
ST
0
1
Op Code
A4
A3
A0
PHY Address
R4
R3
R0
1
0
D15 D14 D1
Register Address Turn Around
D0
Data
Idle
Write
DEVICE MANAGEMENT INTERFACE - READ INCREMENT FRAME STRUCTURE
MDC
MDIO READ
INCREMENT
32 "1"s
0
Idle Preamble
0
ST
1
0
Op Code
A4
A3
A0
PHY Address
R4
R3
R0
Register Address
Z
0 D15 D14
Turn Around
Write
D1
D0
Data
Idle
Read
DEVICE MANAGEMENT INTERFACE - READ FRAME STRUCTURE
MDC
MDIO READ
32 "1"s
Idle Preamble
0
0
ST
1
1
Op Code
A4
21
A0
PHY Address
Write
Figure 14. MDIO Frame Formats
A3
R4
R3
R0
Register Address
Z
0 D15 D14
Turn Around
D1
Data
Read
D0
Idle
It is important to note that
writes to the user accessible
volatile memory are not stored
to the corresponding user
nonvolatile area and will
therefore be lost upon a power
down or reset. For such writes
to be permanent the data must
be written first to the user
accessible nonvolatile area and
then a reload invoked via the
NVR Control/Status register, see
Register 1.32768.
Access
The XENPAK MSA related
Nonvolatile Control/Status
register is only needed for
performing writes to the
nonvolatile user accessible area
within the HFCT-701XB because
nonvolatile memory cannot be
written to by normal MDIO write
cycles. Other writes to volatile
memory and registers may be
performed directly via normal
MDIO write cycles. All volatile
and nonvolatile locations may be
read directly via MDIO read
cycles, it is not necessary to use
the NVR Control/Status register,
other than for status.
Read/Write Command (bit5)
The XENPAK MSA related
1.32768.5 register must be set to
1 to perform writes to the NVR
and zero (read) otherwise a zero
written to bit 5 initiates an NVR
read. A 1 written to bit 5
initiates an NVR write.
Table 11. LASI Control Registers
If the NVR register bit 5 is set to
zero and the extended command
bits set to 11 forces an upload of
all values in the NVR to the
volatile areas, including default
register values. Such an upload
is performed automatically after
a hard or soft reset.
EEPROM Checksum Checking
The HFCT-701XB will perform a
checksum calculation and
compare after every successful
256 byte read. The checksum for
comparison is in EEPROM
register 118 =MDIO register
1.32893.7:0. The checksum is
equal to the 8 LSB ‘s of the sum
of bytes 0 to 117 of the EEPROM.
The calculated checksum is
stored in MDIO register
1.49156.15:8. The result of the
calculated checksum compared
with the one read from EEPROM
is placed in MDIO register
1.49155.7.
EEPROM 256 Byte Read Cycle
An EEPROM 256 Byte Read
Cycle is initiated by setting
MDIO bits 1.32768.0,1 to 0 and
1.32768.5 to 0.
EEPROM Single Byte Read or Write
Cycle
An EEPROM Single Byte Read/
Write Cycle is initiated by setting
MDIO EEPROM control register
bits 1.32768.1:0 to 10. As for the
256 byte read/write commands,
MDIO register 1.32768.5
determines if a read or a write
cycle will be performed. The
single byte EEPROM address is
read from EEPROM control
register 1.32768 bit15:8. The
data is placed in/read from the
associated MDIO register.
Monitors and Diagnostic Features
The LASI pin is used to indicate
suboptimal performance in
either the receive or transmit
path. It can be used as an
interrupt. It is the OR of the
tx_alarm, rx_alarm and the
ls_alarm signals each gated with
their respective enables. The
enables are read from MDIO
register 1.36867, LASI control.
LASI ={OR of (reg 1.36869.n ‘bit
wise AND ‘ reg 1.36866.n) for
n=0 to 15}.
The information to be read from
the EEPROM stored in the 256
MDIO registers. A 256 byte read
is initiated on hot plug or reset.
Description
MDIO Status Registers
LS_ALARM
1.36869.0
RO/LH
1.36866.0
0
TX_ALARM
1.36869.1
RO/LH
1.36866.1
0
RX_ALARM
1.36869.2
RO/LH
1.36866.2
0
LASI test mode
1.36869.3
RW
1.36866.3
0
1.8 V supply too low
1.36869.4
RO/LH
1.36866.4
0
3.3 V supply too low
1.36869.5
RO/LH
1.36866.5
0
MON3P3V_IN voltage too low
1.36869.6
RO/LH
1.36866.6
0
22
Type
MDIO Enable Registers
Default Value
ls_alarm
LS Alarm is latched high each
time the link_status signal
changes state. LS_ALARM is the
output of this latch AND the
LS_ALARM enable register (see
Figure 15). link_status is an
indicator of the link health.
link_status = {PMD signal detect
(MDIO 1.10.0) AND PCS
block_lock (MDIO 3.32.0) AND
PHY_XS lane_alignment (MDIO
4.24.12)}
tx_alarm
tx_alarm is used to indicate a
problem with the transmit path.
tx_alarm is the OR of several
transmit path status registers in
MDIO registers 1.36868 bit wise
AND’d with the TX_ALARM
enable register. The ORing of
each term is enabled by a
companion MDIO register in
1.36865.
tx_alarm = {OR of (reg 1.36868
‘bit wise AND’ reg 1.36865) for
n=0 to 15} AND {TX_ALARM
enable (reg 1.36866)}
Table 12. Receive Alarm Registers
Description
MDIO Status
Registers (RO)
Mirrors
Type
MDIO Enable
Registers (R/W)
Default
PHY_XS receive local fault
1.36867.0
4.8.10
RO/LH
1.36864.0
1
PHY_XS receive rate error
1.36867.1
1.49154.3
RO/LH
1.36864.1
0
PCS receive code violation
1.36867.2
RO/LH
1.36864.2
0
PCS receive local fault
1.36867.3
3.8.11
RO/LH
1.36864.3
0
PMA receive local fault
1.36867.4
1.8.11
RO/LH
1.36864.4
1
Receive power error
1.36867.5
RO/LH
1.36864.5
0
Status 4
Status 5
(en 1.36865.0=1)
(en 1.36865.1=1)
(en 1.36865.2=1)
(en 1.36865.3=1)
(en 1.36865.4=1)
(en 1.36865.5=1)
(en 1.36865.6=1)
Status 6
4.8.11 = 1
1.36868.1 =
1.49154.5
=
1
3.8.11
=1
1
1.8.11 = 1
1.36868.5 =
1.36868.6
=
1
1
Status 4
Status 1,3
Status 1,2
1 * PHY XGXS Tx Local
2 * PHY XGXS Tx Code
Fault
3 * PHY XGXS Tx Rate
Error
4 * PCS Local Tx
Error
5 * PMA Local Tx
Fault
6 * Tx PLL Latched loss of
Fault
7 * Latched version of TX
lock
fault
XAUI LANE 2
XAUI LANE 3
Figure 15. Tx LASI Signals
23
Rate Adjust & Frame
58
39
Rate adjust by add drop
off ¦R¦ character
Scrambler 1+X +X
XAUI LANE 1
PLL
64B/66B 1:0 Block sync
64B/66B Encoder
PLL
8B/10B Decoder
CDR
Lane Alignment, with ¦A¦ character.
XAUI
LANE 0
SIPO and code
word
alignment, with ¦K¦ char
Tx PLL
OK
1.49153.0
Tx
XTAL
Mux
Tx
Opto
Rx_alarm
rx_alarm is used to indicate a
problem with the receive path.
rx_alarm is the OR of several
receive path status registers in
MDIO registers 1.36867.
The ORing of each term is
enabled by a companion MDIO
register in 1.36864 and the
overall output is enabled by the
RX_ALARM enable register
(1.36866.2h).
Table 13. Transmit Alarm Registers
rx_alarm ={OR of (reg 1.36867 ‘bit wise AND ‘ reg 1.36864..n) for n=0 to 15} AND {RX_ALARM enable (1.36866.2h})
Description
MDIO Status
Registers (RO)
Mirrors
Type
MDIO Enable
Registers (R/W)
Default
PHY_XS transmit local fault
1.36868.0
4.8.11
RO/LH
1.36865.0
1
PHY_XS code error
1.36868.1
-
RO/LH
1.36865.1
0
PHY_XS transmit rate error
1.36868.2
1.49154.5
RO/LH
1.36865.2
0
PCS transmit local fault
1.36868.3
3.8.11
RO/LH
1.36865.3
1
PMA transmit local fault
1.36868.4
1.8.11
RO/LH
1.36865.4
1
latched version of txlock
1.36868.5
1.49153.0
RO/LH
1.36865.5
0
latched version of TXFAULT
1.36868.6
RO/LH
1.36865.6
1
laser temperature error
1.36868.7
RO/LH
1.36865.7
0
laser bias error
1.36868.8
RO/LH
1.36865.8
0
Tx output power error
1.36868.9
RO/LH
1.36865.9
0
1 * PMD signal detect
1.10.0
(en 1.36864.0=1)
1 * PCS block_lock
3.32.0
(en 1.36864.0=1)
1 * PHY_XS lane alignment
4.24.12 (en 1.36864h.0=1)
LS_ALARM_enable
link_status
Latch High on change
of level
LS_ALARM
Latch
Reset Low
TX_ALARM_enable
1 * PHY XGXS Tx Local Fault
2 * PHY XGXS Tx Code Error
3 * PHY XGXS Tx Rate Error
4 * PCS Local Tx Fault
5 * PMA Local Tx Fault
6 * Tx PLL Latched loss of lock
7 * Latched version fo TX fault
4.8.11 = 1
1.36868.1 = 1
1.49154.5 = 1
3.8.11 = 1
1.8.11 = 1
1.36868.5 = 1
1.36868.6 = 1
AND
AND
AND
AND
AND
AND
AND
TX_ALARM
(en 1.36865.0=1)
(en 1.36865.1=1)
(en 1.36865.2=1)
(en 1.36865.3=1)
(en 1.36865.4=1)
(en 1.36865.5=1)
(en 1.36865.6=1)
Asserted
On leading
edge of read
RX_ALARM_enable
1 * PHY XGXS Rx Local Fault
2 * PHY XGXS Rx rate error
3 * 64B/66B Rx Code Violation
4 * PCS Local Rx Fault
5 * PMA/D Rx Fault
6 * RX power error
4.8.10 = 1
4.49154 = 1
1.36867 = 1
3.8.11 = 1
1.8.10
1.49155.5
AND
AND
AND
AND
AND
AND
(en 1.36864.0=1)
(en 1.36864.1=1)
(en 1.36864.2=1)
(en 1.36864.3=1)
(en 1.36864.4=1)
(en 1.36864.5=1)
RX_ALARM
LS_ALARM
TX_ALARM
RX_ALARM
LASI test mode
1.8V supply too low
3.3V supply too low
Figure 16. LASI functional diagram
24
1.36869.0
1.36869.1
1.36869.2
1.36869.3
1.36869.4
1.36867.5
(en 1.36866.0
(en 1.36866.1
(en 1.36866.2
(en 1.36866.3
(en 1.36866.4
(en 1.36866.5
0)
0)
0)
0)
0)
0)
LASI
Loopbacks
When in any system (PMA, PCS
or XGXS system) loopback mode
the HFCT-701XB shall accept
data from the transmit path and
return it on the receive path.
Reset Operation
Writing a ‘1’ to any of MDIO
registers 1.0.15, 3.0.15 or 4.0.15
causes all the HFCT-701XB
registers to be reset to their
default values. These bits are all
self-clearing after the reset
function is complete.
During PMA loopback the
XENPAK module will transmit
the data received at the XAUI i/
p’s. In XGXS system loopback,
the laser will default to mean
power but without any
modulation. In PCS loopback
mode a continuous pattern of
0x0F0F will be output. Transmit
data will be output instead if the
associated ‘loopback data out
enable bit ‘ is set high for the
enabled loopback mode.
Pulling the RESET pin low
causes a full chip reset.
Writes to any bits of the Control
register while the RESET is
asserted are ignored. All status
and control registers are reset to
their default states. The NVR
read sequence is started when
RESET goes high. MDIO register
bits 1.0.15, 3.0.15, and 4.0.15
will be held to 1 until the reset
sequence is complete.
When in PMA network loopback
mode, the recovered and
retimed 10.3125 GBd signal is
looped to the transmitter. The
receive path XAUI output data
will be received data. XAUI idle
codes will be output instead of
the received data if the ‘network
loopback data out enable bit ‘ is
set high.
In IEEE 802.3ae standard XGXS
network loopback the recovered
received data is looped back to
the transmit path in the XAUI
block.
Enabling of more than one
loopback path is invalid.
Table 14. Loopback Summary
loopback name
loopback
direction
loopback
control
register
bypassed path
default output
data output enable
register
bypassed path
output control' =1
PMA system loopback
Tx -> Rx
1.0.0
transmit data
NA
NA
PCS loopback
Tx -> Rx
3.0.14
0F0F
3.49152.5
transmit data
XGXS network loopback
(802.3ae standard)
Rx -> Tx
4.0.14
Receive data at Rx
Xaui
NA
NA
XGXS system loopback
Tx -> Rx 4
4.49152.14
Mean power, no
modulation
4.49152.15
transmit data
PMA network loopback
Rx -> Tx 1
1.49153.4
received data
1.49153.9
idle at RxXAUI
25
Force 1's on
PHY_XS
loopback
4.49152.15=0
Tx
XTAL
Mux
Rate Adjust & Frame
Tx
Opto
PMA Network Loopback
XAUI LANE 2
PCS SYSTEM LOOPBACK
64B/66B Encoder
8B/10B Decoder
Rate adjust by add drop
off ¦R¦ character
Scrambler 1+X39+X58
XAUI LANE 1
PMA Network
Loopback
1.49153.4=1
System
Loopback
1.0.0=1
PLL
64B/66B 1:0 Block sync
PHY XGXS SYSTEM LOOPBACK LANE 0
PLL
Lane Alignment, with ¦A¦ character.
CDR
PHY XS NETWORK LOOPBACK LANE 0
XAUI
LANE 0
SIPO and code word
alignment, with ¦K¦ char
XGXS
Network
Loopback
4.0.14=1
PMA System Loopback
XGXS
System
Loopback
4.49152.14
XAUI LANE 3
XAUI LANE 2
XAUI LANE 3
Figure 17. HFCT-701XB Loopback Modes
26
Enable
System
Loopback
4.49152.15=1
CDR
De Mux
PLL
Frame Recovery (block sync)
XAUI LANE 1
XTAL
Descrambler 1+X39+X58
Enable
Network
Loopback
4.0.14=1
64B/66B Decoder
Mux
Driver
8B/10B
Encoder
XAUI LANE 0
Rate adjust
Enable
System
Loopback
4.49152.14=1
Rx
Opto
Internal Clock Functionality
PLL
Rate Adjust & Frame
Mux
Frame Recovery (block sync)
De Mux
39 +X 58
Rate adjust by add drop
off ¦R¦ character
Scrambler 1+X
XAUI LANE 1
64B/66B Encoder
PLL
Tx
XTAL
64B/66B 1:0 Block sync
8B/10B Decoder
CDR
TX 10G Clock Domain
Derrived internally from
precision oscillator
Lane Alignment, with ¦A¦ character.
XAUI
LANE 0
SIPO and code word
alignment, with ¦K¦ char
TX XAUI Clock Domain
Recovered from incoming
XAUI link
Tx
Opto
XAUI LANE 2
XAUI LANE 3
Figure 18. Transmit Path
RX XAUI Clock Domain
Derived internally from
precision oscillator
RX 10G Clock Domain
Recovered from incoming
10G link
XAUI LANE 2
Clock for Rx 10G path
XAUI LANE 3
Figure 19. Receive Path
27
CDR
39 +X 58
Rate adjust
XAUI LANE 1
Descrambler 1+X
PLL
64B/66B Decoder
XTAL
8B/10B
Encoder
Driver
Mux
XAUI LANE 0
Rx
Opto
HFCT-701XB Registers
PLL OK
4.49152.3
XAUI LANE 2
CDR
XAUI LANE 1
PLL
In Service
PCS Bit Error
Counter
3.33.13:8
De Mux
8B/10B
Encoder
Mux
Status 5
Frame Recovery (block sync)
XTAL
Status 6
Bypass
Scrambler
3.49152.1
=1
Rate adjust
XAUI LANE 0
Driver
From
De-Scrambler
Frame
recovery
CDR
Status 4
(en 1.36864.0=1)
(en 1.36864.1=1)
(en 1.36864.2=1)
(en 1.36864.3=1)
(en 1.36864.4=1)
(en 1.36864.5=1)
Descrambler 1+X39+X58
Status 1,2
Reset all
X.15 = 1
4.8.10 = 1
4.49154.6:9 = 1
1.36867.2 = 1
3.8.11 = 1
1.8.10
1.36867.5
Status 3,4
1 * PHY XGXS Rx Local Fault
2 * PHY XGXS Rx rate error
3 * 64B/66B Rx Code Violation
4 * PCS Local Rx Fault
5 * PMA/D Rx Fault
6 * RX power error
64B/66B Decoder
PHY XS Link Up
4.1.2 = 1
Status 1
from
Tx
Rx
Opto
Signal
Detect
1.10.0=1
Clock for Rx 10G path
XAUI LANE 3
Reset Tx
XGXS
4.49152.0=1
In Service
Errored Block
Counter
3.33.7:0
PMA
Locked
1.1.2=1
Reset PCS
3.49152.4=1
Rx Clk
rate error
1.49153.1
=1
Figure 20. Summary of Key Receiver Path Registers
Status 4
Status 6
Status 5
(en 1.36865.0=1)
(en 1.36865.1=1)
(en 1.36865.2=1)
(en 1.36865.3=1)
(en 1.36865.4=1)
(en 1.36865.5=1)
(en 1.36865.6=1)
Status 4
Lock
4.49152.7:4
XAUI LANE 2
PHY XGXS Link Up
4.1.2 = 1
XAUI LANE 3
Rate adjust by add drop
off ¦R¦ character
Sync
4.24.3:0
from
Rx
Lanes
Aligned
4.24.12=1
Figure 21. Summary of Key Transmit Path Registers
28
Reset PCS
3.49152.3=0
Transmit
Disable
1.9.0
64B/66B
Encoder
error
3.49152.0
=1
Rate Adjust & Frame
XAUI LANE 1
64B/66B 1:0 Block sync
Scrambler 1+X39+X58
PLL OK
4.49152.3
PLL
Bypass
3.49152.2
=1
64B/66B Encoder
PLL
8B/10B Decoder
CDR
Lane Alignment, with ¦A¦ character.
XAUI
LANE 0
SIPO and code word
alignment, with ¦K¦ char
Tx PLL
OK
1.49153.0
Tx
XTAL
Tx
Opto
Mux
Status 1,2
Reset all
X.15 = 1
4.8.11 = 1
1.36868.1 = 1
1.36868.2 = 1
3.8.11 = 1
1.8.11 = 1
1.36868.5 = 1
1.36868.6 = 1
Status 1,3
1 * PHY XGXS Tx Local Fault
2 * PHY XGXS Tx Code Error
3 * PHY XGXS Tx Rate Error
4 * PCS Local Tx Fault
5 * PMA Local Tx Fault
6 * Tx PLL Latched loss of lock
7 * Latched version fo TX fault
Legend
* = LASI Signal
HFCT-701XB Device 1 PMA/PMD Registers
Device
From
Decimal
Hex
1
0
0
PMA/PMD Control 1
1
1
1
PMA/PMD Status 1
1
2
2
1
4
4
1
5
5
1
7
7
10G PMA/PMD Control 2
1
8
8
10G PMA/PMD Status 2
1
9
9
10G PMD transmit disable
1
10
A
10G PMD receive signal detect
1
14
E
1
32768
8000
NVR Control/Status
1
32775
8007
XENPAK MSA version supported
1
32776
8008
32777
8009
NVR size in bytes
1
32778
800A
32779
800B
Number of bytes used
1
32780
800C
Basic Field Address
1
32781
800D
Customer Field Address
1
32782
800E
Vendor Field Address
1
32783
800F
1
32785
8011
Reserved
1
32786
8012
Transceiver type
1
32787
8013
Optical connector type
1
32788
8014
Bit encoding
1
32789
8015
1
32791
8017
1
32792
8018
32801
8021
Standards Compliance Codes 10GbE Code Byte 0
1
32802
8022
32803
8023
Specifies transmission range in 10 m increments
1
32804
8024
32805
8025
Fibre Type Byte 0 and Byte1
1
32806
8026
32808
8028
Centre Optical Wavelength in 0.01nm steps - Channel 0
1
32818
8032
32821
8035
Package Identifier OUI
1
32822
8036
32825
8039
Transceiver Vendor OUI
29
To
Decimal
3
Register Name
Hex
3
Device identifier
PMA/PMD Speed Ability
6
15
32784
32790
6
F
8010
8016
Devices in package
Package identifier (OUI)
Extended Vendor Field Address
Nominal Bit Rate in multiples of 1Mb/s
Protocol Type
Device
From
Decimal
Hex
To
Decimal
Hex
1
32826
803A
32841
8049
Transceiver vendor name in ASCII
1
32842
804A
32857
8059
Part number provided by transceiver vendor in ASCII
1
32858
805A
32859
805B
Revision level for part number provided by vendor ASCII
1
32860
805C
32875
806B
Vendor serial number in ASCII
1
32876
806C
32885
8075
Vendor manufacturing date code in ASCII
1
32886
8076
5 V stressed environment reference
1
32887
8077
3.3 V stressed environment reference
1
32888
8078
APS stressed environment reference
1
32889
8079
Nominal APS voltage
1
32890
807A
DOM capability
1
32891
807B
Reserved
1
32893
807D
Basic Field Checksum
1
32894
807E
32941
80AD
Customer Writeable Area
1
32942
80AE
33030
8106
Vendor Specific
1
33031
8107
36863
8FFF
Extended Vendor Specific
1
36864
9000
RX_ALARM Control
1
36865
9001
TX_ALARM Control
1
36866
9002
LASI Control
1
36867
9003
RX_ALARM Status
1
36868
9004
TX_ALARM Status
1
36869
9005
LASI Status
1
49153
C001
Extended PMA features
1
49155
C003
PMA/PMD Vendor Specific
1
49156
C004
PMA/PMD Vendor Specific Checksum
1
49188
C024
PMA Vendor Specific
30
Register Name
Register 1.0 - PMA/PMD Control 1
Bit(s)
Name
Description
R/W1
1.0.15
Reset
RW
1.0.14
Reserved
1 = PMA/PMD reset
0 = Normal operation
Value always 0, writes ignored
1.0.13
Speed selection
RW
1.0.12
Reserved
1 = Operation at 10 Gb/s and above
0 = Unspecified
Value always 0, writes ignored
1.0.11
Low Power
RW
1.0.10:7
Reserved
1 = Low Power mode
0 = Normal operation
Value always 0, writes ignored
1.0.6
Speed selection
RW
1.0.5:2
Speed selection
1 = Operation at 10 Gb/s and above
0 = Unspecified
5432
1 x x x = Reserved
1.0.1
Reserved
1.0.0
PMA loopback
x 1 x x = Reserved
x x 1 x = Reserved
0 0 0 1 = Reserved
0 0 0 0 = 10 Gb/s
Values always 0, writes ignored
Default Value
RW
1
RW
0
RW
1
RW
RW
1 = Enable PMA loopback mode
0 = Disable PMA loopback mode
RW
0
Description
R/W1
Default Value
Register 1.1 - PMA/PMD Status 1
Bit(s)
Name
1.1.15:8
Reserved
N/A
RO
1.1.7
Fault
1 = Local fault condition detected in PMA/PMD
RO
N/A
0 = Local fault condition not detected in PMA/PMD
1.1.6:3
Reserved
(Set to a 1 when either 1.8.11 or 1.8.10 set to a one)
N/A
RO/LL
1.1.2
Receive link status
1 = PMA locked to receive signal
RO/LL
N/A
Power down ability
0 = PMA not locked to receive signal
1 = PMA/PMD supports low power mode
RO
1
Reserved
0 = PMA/PMD does not support low power mode
N/A
R/W1
Default Value
1.1.1
1.1.0
Register 1.2 to 1.3 - Device Identifier
Bit(s)
Name
Description
1.3.15:0
PMA Identifier
RO
1.2.15:0
PMA Identifier
RO
Register 1.4 PMA/PMD Speed Ability
Bit(s)
Name
1.4.15:1
Reserved for future
speeds
10 G capable
1.4.0
Description
1 = PMA/PMD is capable of operating at 10 Gb/s
0 = PMA/PMD is not capable of operating at 10Gb/s
Note:
1. RW = Read/Write, RO = Read Only, LL = Latching Low
31
R/W1
Default Value
RO
N/A
RO
1
Register 1.5 to 1.6 - PMA/PMD Devices in Package
Description
R/W1
Default Value
RO
1
Bit(s)
Name
1.6.15
1.6.14
Vendor Specific Device 1 = Vendor specific device 2 present in package
2 present
0 = Vendor specific device 2 not present in package
Vendor Specific
Reserved
RO
1.6.13:0
Reserved
N/A
RO
1.5.15:6
Reserved
N/A
RO
1.5.5
DTE XS present
RO
0
1.5.4
PHY XS present
RO
1
1.5.3
PCS present
RO
1
1.5.2
WIS present
RO
0
1.5.1
PMD/PMA present
1 = DTE XS present in package
0 = DTE XS not present in package
1 = PHY XS present in package
0 = PHY XS not present in package
1 = PCS present in package
0 = PCS not present in package
1 = WIS present in package
0 = WIS not present in package
1 = PMD/PMA present in package
RO
1
1.5.0
Clause 22 registers
present
0 = PMD/PMA not present in package
1 = Clause 22 registers present in package
0 = Clause 22 registers not present in package
RO
0
R/W1
Default Value
RW
110
Register 1.7 - 10 G PMA/PMD Control 2
Bit(s)
Name
Description
1.7.15:3
Reserved
N/A
1.7.2:0
PMA/PMD type
selection
210
1 1 1 = 10GBASE-SR PMA/PMD type
1 1 0 = 10GBASE-LR PMA/PMD type
1 0 1 = 10GBASE-ER PMA/PMD type
1 0 0 = 10GBASE-LX4 PMA/PMD type
0 1 1 = 10GBASE-SW PMA/PMD type
0 1 0 = 10GBASE-LW PMA/PMD type
0 0 1 = 10GBASE-EW PMA/PMD type
0 0 0 = Reserved
Note:
1. RW = Read/Write, RO = Read Only,
32
Register 1.8 - 10 G PMA/PMA Status 2
Bit(s)
Name
Description
R/W1
Default Value
1.8.15:14
Device present
15 14
RO
10
RO
1
RO
1
1 0 = Device responding at this address
1 1 = No device responding at this address
0 1 = No device responding at this address
1.8.13
Transmit local fault
0 0 = No device responding at this address
1 = PMA/PMD has the ability to detect a local fault
ability
condition on the transmit path
0 = PMA/PMD does not have the ability to detect a fault
1.8.12
Receive local fault
condition on the transmit path
1 = PMA/PMD has the ability to detect a local fault
ability
condition on the receive path
0 = PMA/PMD does not have the ability to detect a fault
Transmit local fault
condition on the receive path
1 = Local fault condition on transmit path
RO/LH
N/A
Receive local fault
0 = No local fault condition on transmit path
1 = Local fault condition on receive path
RO/LH
N/A
1.8.9
Reserved
0 = No local fault condition on receive path
N/A
RO
1.8.8
PMD transmit disable
1 = PMD has the ability to disable the transmit path
RO
1
ability
0 = PMD does not have the ability to disable the transmit
10GBASE-SR ability
path
1 = PMA/PMD is able to perform 10GBASE-SR
RO
0
10GBASE-LR ability
0 = PMA/PMD is not able to perform 10GBASE-SR
1 = PMA/PMD is able to perform 10GBASE-LR
RO
1
10GBASE-ER ability
0 = PMA/PMD is not able to perform 10GBASE-LR
1 = PMA/PMD is able to perform 10GBASE-ER
RO
0
10GBASE-LX4 ability
0 = PMA/PMD is not able to perform 10GBASE-ER
1 = PMA/PMD is able to perform 10GBASE-LX4
RO
0
10GBASE-SW ability
0 = PMA/PMA is not able to perform 10GBASE-LX4
1 = PMA/PMD is able to perform 10GBASE-SW
RO
0
10GBASE-LW ability
0 = PMA/PMD is not able to perform 10GBASE-SW
1 = PMA/PMD is able to perform 10GBASE-SW
RO
0
10GBASE-EW ability
0 = PMA/PMD is not able to perform 10GBASE-LW
1 = PMA/PMD is able to perform 10GBASE-EW
RO
0
PMA loopback ability
0 = PMA/PMD is not able to perform 10GBASE-EW
1 = PMA has the ability to perform a loopback function
RO
1
Default Value
1.8.11
1.8.10
1.8.7
1.8.6
1.8.5
1.8.4
1.8.3
1.8.2
1.8.1
1.8.0
0 = PMA does not have the ability to perform a loopback
function
Register 1.9 - 10 G PMD Transmit Disable
Bit(s)
Name
Description
R/W1
1.9.15:5
Reserved
N/A
RW
1.9.4:1
LX4 Signal Detect
Not used
RW
0
1.9.4:0
PMD Transmit Disable
1 = Transmit disable
0 = Transmit enable
RW
0
Note:
1. RW = Read/Write, RO = Read Only, LH = Latch High, clear on read (note that if the condition exitsts following register read, the bit will not be
cleared).
33
Register 1.10 - 10 G PMD Receive Signal OK
Description
R/W1
Reserved
Value always 0, writes ignored
RO
LX4 Signal Detect
Not used
RO
Global PMD Receive
signal detect
1 = Signal detected on receive
0 = Signal not detected on receive
RO
Bit(s)
Name
1.10.15:5
1.10.4:1
1.10.0
Default Value
Register 1.14 to 1.15 - Package Identifier (OUI)
Bit(s)
Name
Description
R/W1
Default Value
1.15.15
Reserved
Reserved
RO
248
1.15.14:11
Revision Number
Revision Number
RO
1.15.11:8
NVR Address
NVR DEV Address
RO
1.15.7:6
NVR Address
NVR DEV Address
RO
1.15.5:0
Package Identifier
XENPAK OUI
RO
1.14.15:8
Package Identifier
XENPAK OUI
RO
1.14.7:0
Package Identifier
XENPAK OUI
RO
34
Register 1.32768 - NVR Control/Status
Bit(s)
Name
1.32768.15:9
Vendor Specific
Description
R/W1
Default Value
RW
1.32768.7:6
Reserved
1.32768.5
RW2
1.32768.4
Read/Write Command 3 0 = Read NVR
1 = Write NVR
Reserved
N/A
N/A
1.32768.3:2
Command Status
RO/LH
1.32768.1:0
Extended Commands
00 = Idle
01 = Command completed successfully
10 = Command in progress
11 = Command failed
00 = Reserved
01 = Reserved
10 = Read/Write 1 byte
11 = Read all NVR contents
RO
RO
RW2
1.32775 to 1.32782 - NVR Information
Bit(s)
Name
Description
R/W1
Default Value (dec)
1.32775.7:0
Version
NVR Version number (MSB:LSB)
RO
30
1.32776.7:0
NVR_Size
NVR Size (upper byte) = 256 bytes
RO
1
1.32777.7:0
NVR_Size
NVR Size (lower byte) = 256 bytes
RO
0
1.32778.7:0
Mem_Used
Bytes used (upper byte) = 256 bytes
RO
1
1.32779.7:0
Mem_Used
Bytes used (lower byte) = 256 bytes
RO
0
1.32780.7:0
Basic Addr
Basic Field Address (MSB:LSB) Start
RO
11
1.32781.7:0
Cust Addr
Customer Field Address (MSB:LSB) Start
RO
119
1.32782.7:0
Vend Addr
Vendor Field Address (MSB:LSB) Start
RO
167
1.32783.7:0
Ext Vend Addr
Extended Vendor Field Address Start
RO
1
1.32784.7:0
Ext Vend Addr
Extended Vendor Field Address Start
RO
0
1.32785.7:0
Reserved
RO
0
34
Note:
1. RW = Read/Write, RO = Read Only, LH = latch high, clear on read (note that if the condition exists following register read, the bit will not be
cleared).
2. The values of the ‘Command’ and ‘Extended Command’ bits are held until a command has been executed.
3. Writes to register 1.32768 ignored during “command in progress”. Reads will not clear command status.
Register 1.32786 - Transceiver Type
Bit(s)
Name
Description
R/W1
Default Value (dec)
1.32786.7:0
RO
1
Transceiver type
XENPAK
Register 1.32787 - Optical Connector Type
Bit(s)
Name
Description
R/W1
Default Value (dec)
1.32787.7:0
Connector
SC Duplex Connector
RO
1
Register 1.32788 - Bit Encoding
Bit(s)
Name
Description
R/W1
Default Value (dec)
1.32788.7:0
Bit Encoding
NRZ
RO
1
Register 1.32789 to 1.32790 - Bit Rate
Bit(s)
Name
Description
R/W1
Default Value (dec)
1.32789.7:0
Bit rate
Bit 15 (MSB) to Bit 8
RO
40
1.32790.7:0
Bit rate
Bit 7 to Bit 0
RO
72
Register 1.32791 - Protocol Type
Bit(s)
1.32791.7:0
Name
Protocol
Description
R/W1
Default Value (dec)
Supports 10GbE
RO
1
Register 1.32792 to 1.32793 - 10GbE Compliance Code
Bit(s)
Name
Description
R/W1
Default Value (dec)
1.32792.7:0
Standards compliance
Supports 10GBASE-LR
RO
2
1.32793.15:0
code
Reserved
N/A
0
Register 1.32802 to 1.32803 - Transmission Range
R/W1
Default Value (dec)
Bit(s)
Name
Description
1.32802.7:0
Transmission Range
Bit 15 (MSB) to Bit 8
RO
3
1.32803.7:0
Transmission Range
Bit 7 to Bit 0
RO
232
Description
R/W1
Default Value (dec)
RO
Register 1.32804 to 1.32805 - Fiber Type Suitability
Bit(s)
Name
1.32804.5
Fiber Type
SM Generic
1.32805.0
Reserved
N/A
32
128
Register 1.32806 to 1.32808 - Center Wavelength
Bit(s)
Name
1.32806.7:0
Wavelength
1.32807.7:0
Wavelength
1.32808.7:0
Wavelength
Note:
1. RW = Read/Write, RO = Read Only.
35
R/W1
Default Value (dec)
Bits 23-16
RO
1
Bits 15-8
RO
255
Bits 7-0
RO
184
Description
Register 1.32818 to 1.32821 - Package Identifier (OUI) = Xenpak
Default Value (dec)
Bit(s)
Name
Description
R/W1
1.32818.7:0
Package Identifier
Package Identifier
RO
0
1.32819.7:0
Package Identifier
Package Identifier
RO
65
244
1.32820.7:2
Package Identifier
Package Identifier
RO
1.32820.1:0
NVR Address
NVR Device Address
RO
1.32821.7:5
NVR Address
NVR Device Address
RO
RO
1.32821.4:1
Revision Number
Revision Number
1.32821.0
Reserved
Reserved
32
Register 1.32822 to 1.32825 - Vendor (OUI) = Agilent
Bit(s)
Name
Description
R/W1
Default Value (dec)
1.32822.7:0
Vendor OUI
Vendor OUI
RO
0
1.32823.7:0
Vendor OUI
Vendor OUI
RO
0
48
1.32824.7:2
Vendor OUI
Vendor OUI
RO
1.32824.1:0
Model No
Model Number
RO
1.32825.7:4
Model No
Model Number
RO
1.32825.3:0
Rev No
Revision Number
RO
211
Register 1.32826 to 1.32841 - Vendor Name (ASCII)
Bit(s)
Name
Description
R/W1
Default Value
1.32826.7:0
Vendor Name
Vendor Name byte 15 (MSB:LSB)
RO
A (65)
1.32827.7:0
Vendor Name
Vendor Name byte 14 (MSB:LSB)
RO
G (71)
1.32828.7:0
Vendor Name
Vendor Name byte 13 (MSB:LSB)
RO
I (73)
1.32829.7:0
Vendor Name
Vendor Name byte 12 (MSB:LSB)
RO
L (76)
1.32830.7:0
Vendor Name
Vendor Name byte 11 (MSB:LSB)
RO
E (69)
1.32831.7:0
Vendor Name
Vendor Name byte 10 (MSB:LSB)
RO
N (78)
1.32832.7:0
Vendor Name
Vendor Name byte 9 (MSB:LSB)
RO
T (84)
1.32833.7:0
Vendor Name
Vendor Name byte 8 (MSB:LSB)
RO
SPACE (32)
1.32834.7:0
Vendor Name
Vendor Name byte 7 (MSB:LSB)
RO
SPACE (32)
1.32835.7:0
Vendor Name
Vendor Name byte 6 (MSB:LSB)
RO
SPACE (32)
1.32836.7:0
Vendor Name
Vendor Name byte 5 (MSB:LSB)
RO
SPACE (32)
1.32837.7:0
Vendor Name
Vendor Name byte 4 (MSB:LSB)
RO
SPACE (32)
1.32838.7:0
Vendor Name
Vendor Name byte 3 (MSB:LSB)
RO
SPACE (32)
1.32839.7:0
Vendor Name
Vendor Name byte 2 (MSB:LSB)
RO
SPACE (32)
1.32840.7:0
Vendor Name
Vendor Name byte 1 (MSB:LSB)
RO
SPACE (32)
1.32841.7:0
Vendor Name
Vendor Name byte 0 (MSB:LSB)
RO
SPACE (32)
Note:
1. RW = Read/Write, RO = Read Only.
36
Register 1.32842 to 1.32857 - Vendor Part Number (ASCII)
Bit(s)
Name
Description
R/W1
Default Value (dec)
1.32842.7:0
Vendor Part No
Vendor Part No. byte 15 (MSB:LSB)
RO
H (72)
1.32843.7:0
Vendor Part No
Vendor Part No. byte 14 (MSB:LSB)
RO
F (70)
1.32844.7:0
Vendor Part No
Vendor Part No. byte 13 (MSB:LSB)
RO
C (67)
1.32845.7:0
Vendor Part No
Vendor Part No. byte 12 (MSB:LSB)
RO
T (84)
1.32846.7:0
Vendor Part No
Vendor Part No. byte 11 (MSB:LSB)
RO
- (45)
1.32847.7:0
Vendor Part No
Vendor Part No. byte 10 (MSB:LSB)
RO
7 (55)
1.32848.7:0
Vendor Part No
Vendor Part No. byte 9 (MSB:LSB)
RO
0 (48)
1.32849.7:0
Vendor Part No
Vendor Part No. byte 8 (MSB:LSB)
RO
1 (49)
1.32850.7:0
Vendor Part No
Vendor Part No. byte 7 (MSB:LSB)
RO
X (88)
1.32851.7:0
Vendor Part No
Vendor Part No. byte 6 (MSB:LSB)
RO
B (66)
1.32852.7:0
Vendor Part No
Vendor Part No. byte 5 (MSB:LSB)
RO
SPACE (32)
1.32853.7:0
Vendor Part No
Vendor Part No. byte 4 (MSB:LSB)
RO
SPACE (32)
1.32854.7:0
Vendor Part No
Vendor Part No. byte 3 (MSB:LSB)
RO
SPACE (32)
1.32855.7:0
Vendor Part No
Vendor Part No. byte 2 (MSB:LSB)
RO
SPACE (32)
1.32856.7:0
Vendor Part No
Vendor Part No. byte 1 (MSB:LSB)
RO
SPACE (32)
1.32857.7:0
Vendor Part No
Vendor Part No. byte 0 (MSB:LSB)
RO
SPACE (32)
Register 1.32858 to 1.32859 - Vendor Revision (ASCII)
Bit(s)
Name
Description
R/W1
Default Value (dec)
1.32858.7:0
Vendor Rev
Revision Upper Byte (MSB:LSB)
RO
0
1.32859.7:0
Vendor Rev
Revision Lower Byte (MSB:LSB)
RO
0
R/W1
Default Value
Register 1.32860 to 1.32875 - Vendor Serial Number (ASCII)
Bit(s)
Name
Description
1.32860.7:0
Vendor Serial No
Vendor Serial No. byte 15 (MSB:LSB)
1.32861.7:0
Vendor Serial No
Vendor Serial No. byte 14 (MSB:LSB)
1.32862.7:0
Vendor Serial No
Vendor Serial No. byte 13 (MSB:LSB)
RO
-
1.32863.7:0
Vendor Serial No
Vendor Serial No. byte 12 (MSB:LSB)
RO
-
1.32864.7:0
Vendor Serial No
Vendor Serial No. byte 11 (MSB:LSB)
RO
-
1.32865.7:0
Vendor Serial No
Vendor Serial No. byte 10 (MSB:LSB)
RO
-
1.32866.7:0
Vendor Serial No
Vendor Serial No. byte 9 (MSB:LSB)
RO
-
1.32867.7:0
Vendor Serial No
Vendor Serial No. byte 8 (MSB:LSB)
RO
-
1.32868.7:0
Vendor Serial No
Vendor Serial No. byte 7 (MSB:LSB)
RO
-
1.32869.7:0
Vendor Serial No
Vendor Serial No. byte 6 (MSB:LSB)
RO
-
1.32870.7:0
Vendor Serial No
Vendor Serial No. byte 5 (MSB:LSB)
RO
-
1.32871.7:0
Vendor Serial No
Vendor Serial No. byte 4 (MSB:LSB)
RO
-
1.32872.7:0
Vendor Serial No
Vendor Serial No. byte 3 (MSB:LSB)
RO
-
1.32873.7:0
Vendor Serial No
Vendor Serial No. byte 2 (MSB:LSB)
RO
-
1.32874.7:0
Vendor Serial No
Vendor Serial No. byte 1 (MSB:LSB)
RO
-
1.32875.7:0
Vendor Serial No
Vendor Serial No. byte 0 (MSB:LSB)
RO
-
Note:
1. RW = Read/Write, RO = Read Only.
37
Register 1.32876 to 1.32885 - Date Code (ASCII)
Bit(s)
Name
Description
1.32876.7:0
Year (1000's)
R/W1
Default Value
RO
-
Year in 1000's (bit 7=MSB, bit 0=LSB)
1.32877.7:0
Year (100's)
Year in 100's (bit 7=MSB, bit 0=LSB)
1.32878.7:0
Year (10's)
Year in 10's (bit 7=MSB, bit 0=LSB)
1.32879.7:0
Year (1's)
Year Units (bit 7=MSB, bit 0=LSB)
RO
-
1.32880.7:0
Month (10's)
Month in 10's (bit 7=MSB, bit 0=LSB)
RO
-
1.32881.7:0
Month (1's)
Month in units (bit 7=MSB, bit 0=LSB)
RO
-
1.32882.7:0
Day (10's)
Day in 10's (bit 7=MSB, bit 0=LSB)
RO
-
1.32883.7:0
Day (1's)
Day in Units (bit 7=MSB, bit 0=LSB)
RO
-
1.32884.7:0
Lot Code (10's)
Lot code in 10's (bit 7=MSB, bit 0=LSB)
RO
-
1.32885.7:0
Lot Code (1's)
Lot code in units (bit 7=MSB, bit 0=LSB)
RO
-
Register 1.32886 - 5 V Stressed Environment
Bit(s)
Name
Description
R/W1
Default Value
1.32886.7:0
RO
0
5V Supply
5 V stressed environment reference
Register 1.32887 - 3.3 V Stressed Environment
Bit(s)
Name
Description
R/W1
Default Value
1.32887.7:0
RO
16
3.3V Supply
3.3 V stressed environment reference
Register 1.32888 - APS Stressed Environment
Bit(s)
Name
Description
R/W1
Default Value
1.32888.7:0
APS stressed environment reference
RO
1
Register 1.32889 - APS Voltage
Bit(s)
Name
Description
R/W1
Default Value
1.32889.7:0
Nominal APS voltage (1.8V)
RO
16
Register 1.32890 - DOM Capability
Bit(s)
Name
Description
R/W1
Default Value
1.32890.7
RO
0
APS Supply
APS Voltage
Status
DOM Control/Status Register:
0 = not implemented
1.32890.6
DOM set
1 = implemented
Set when DOM implemented
RO
0
1.32890.5
WDM capability
WDM lane by lane DOM capability: setting this bit
RO
0
RO
0
1 = 10 µA
Reserved
RO
0
Address of external DOM device
RO
0
Register 1.32891 - Reversed
Bit(s)
Name
Description
R/W1
Default Value
1.32891.7:0
DOM Control/Status
RO
indicates that registers A0CO-A0FF are valid. Setting this
bit will NOT override indications placed in register A06F
1.32890.4
Laser bias scale
(DOM capability)
Laser bias scale factor:
0 = 2 µA
1.32890.3
1.32890.2:0
External DOM
DOM Control/Status
Register 1.32894 - 1.32941 Customer Writeable Area
Bit(s)
Name
Description
R/W1
1.32894.7:0
Start of writeable area
Start of customer writeable Area
RO
1.32941.7:0
End of writeable area
End of customer writeable area
RO
38
Note:
1. RW = Read/Write, RO = Read Only.
Default Value
Register 1.32942 to 1.33030 - Vendor Specific
Bit(s)
Name
1.32942.7:0
Description
R/W1
Vendor Specific
RO
Default Value
to 1.33030.7:0
Register 1.33030 - Extended Vendor Specific
Bit(s)
Name
1.33031.7:0
Description
R/W1
Extended Vendor Specific
RO
Default Value
Register 1.36864 RX_ALARM Control (see also Table 1.36867 RX_ALARM Status)
Bit(s)
Name
Description
R/W1
Default Value
1.36864. 15:11
Reserved
Reserved
RO
0
1.36864. 6
PHY_XS receive buffer
1 = PHY_XS receive buffer over/underflow error enable
RW
0
1.36864. 5
error enable
Receive optical power
0 = disabled
1 = Receive Optical Power Fault Enable
1.36864. 4
fault
PMA/PMD local fault
1.36864. 3
PCS local fault
0 = Receive Optical Power Fault Disable
1 = PMA/PMD Receiver Local Fault Enable
0 = PMA/PMD Receiver Local Fault Disable
1 = PCS Receiver Local Fault Enable
1.36864.2
PCS Receive Code
0 = PCS Receiver Local Fault Disable
1 = Violation Enable
1.36864.1
RX Flag
0 = Violation Disable
1 = Enabled
RW
0
PHY XS Receive local
0 = Disabled
1 = PHY XS Receive Local Fault Enable
RW
1
fault
0 = PHY XS Receive Local Fault Disable
1.36864.0
1
RW
1
Register 1.36865 TX_ALARM Control (see also Table 1.36868 TX_ALARM Status)
Bit(s)
Name
Description
R/W1
Default Value
1.36865. 15:11
Reserved
Reserved
RO
0
1.36865. 10
PHY_XS code violation 1 = PHY_XS code violation error enabled
RW
Note 3
1.36865. 9
error
0 = PHY_XS code violation error disabled
Laser bias current fault 1 = Laser Bias Current Fault Enable
Note 2
0
Laser temp fault
0 = Laser Bias Current Fault Disable
1 = Laser Temperature Fault Enable
Note 2
Note 2
0
Laser output fault
0 = Laser Temperature Fault Disable
1 = Laser Output Power Fault Enable
Note 2
0
Transmitter Fault
0 = Laser Output Power Fault Disable
1 = Transmitter Fault Enable
RW
1
1.36865. 5
Transmitter Loss of
0 = Transmitter Fault Disable
1 = Transmitter Loss of Lock enabled
RW
Note 3
1.36865. 4
Lock
PMA/PMD transmit
0 = Transmitter Loss of Lock disabled
1 = PMA/PMD Transmitter Local Fault Enable
Note 2
1
1.36865.3
fault
PCS transmit fault
0 = PMA/PMD Transmitter Local Fault Disable
1 = PCS Transmit Local Fault Enable
RW
1
1.36865.2
PCS buffer
0 = PCS Transmit Local Fault Disable
1 = PCS buffer over/underflow enabled
RW
0
1.36865.1
over/underflow
TX Flag
0 = PCS buffer over/underflow disabled
1 = TX flag enabled
RW
0
PHY XS transmit fault
0 = TX flag disabled
1 = PHY XS Transmit Local Fault Enable
RW
1
1.36865. 8
1.36865. 7
1.36865. 6
1.36865.0
0 = PHY XS Transmit Local Fault Disable
Note:
1. RW = Read/Write, RO = Read Only.
2. Optional features that are not implemented shall have their enable bit forced to zero. When implemented, the default value for the control bit shall
be 1.
3. The default value for a vendor specific bit shall be vendor specific.
39
Register 1.36866 - LASI Control (see also Table 1.36869 LASI Status)
Bit(s)
Name
Description
R/W1
Default Value
1.36866.15:8
Reserved
Reserved
RO
0
1.36866. 6
MON3P3V_IN supply
1 = Enable detection of supply too low
RW
1.36866.5
too low
3.3V supply too low
0 = Disable detection of supply too low
1 = Enable detection of supply too low
RW
0
1.8V supply too low
0 = Disable detection of supply too low
1 = Enable detection of supply too low
RW
0
LASI test data
0 = Disable detection of supply too low
1 = Enable LASI test data
RW
0
RX alarm
0 = Disable LASI test data
1 = RX_ALARM enable
RW
0
TX alarm
0 = RX ALARM disable
1 = TX_ALARM enable
RW
0
LS alarm
0 = TX ALARM disable
1 = LS_ALARM enable
RW
0
1.36866.4
1.36866.3
1.36866. 2
1.36866. 1
1.36866. 0
0 = LS ALARM disable
Register 1.36867 - RX_ALARM Status (see also Table 1.36864 - RX_ALARM Control)
Bit(s)
Name
Description
R/W1
1.36867.15:11
Reserved
Reserved
RO/RW
1.36867.6
PHY_XS receive buffer
1 = PHY XS receive buffer over/underflow enabled
RO/LH
1.36867.5
error enable
Receive optical power
0 = PHY XS receive buffer over/underflow disabled
Local fault condition detected in optical power fault
RO/LH
1.36867.4
fault
PMA/PMD Receive
PMA/PMD receive local fault ( A mirror of 1.8.10)
RO/LH
1.36867.3
local fault
PCS Receive local fault PCS receive local fault (A mirror of 3.8.10)
1.36867.2
Local fault condition detected in code violation
1.36867.1
PCS receive code
violation
RX flag
1.36867.0
PHY-XS Receive local
PHY_XS receive local fault. (A mirror of 4.8.10)
Default Value
RO/LH
RO/LH
RO/LH
RO/LH
fault
Register 1.36868 - TX_ALARM Status (see also Table 1.36865 TX_ALARM Control)
Bit(s)
Name
Description
R/W1
1.36868. 15:11
Reserved
1.36868. 10
PHY_XS code violation PHY_XS code violation error enable
enable
Laser bias fault
ADC channel 2
1.36868. 9
Reserved
Laser Bias Current Fault
ADC channel 1
1.36868. 8
Laser temp fault
1.36868. 7
Laser power fault
1.36868. 6
Transmitter fault
1.36868. 5
Transmitter loss of lock
1.36868. 4
PMA/PMD transmit
1.36868.3
local fault
PCS transmit local fault PCS Transmit Local Fault (linked to 3.8.11)
1.36868.2
1.36868.1
1.36868.0
40
Laser Temperature Fault
ADC channel 0
Laser Output Power Fault
Transmitter Fault
Default Value
RO
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
PMA/PMD Transmitter Local Fault (linked to 1.8.11)
PCS buffer
over/underflow error
TX_flag
Linked to 4.49154.8:9
PHY XS transmit local
fault
PHY XS Transmit Local Fault (linked to 4.8.11)
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
Note:
1. RW = Read/Write, RO = Read Only, LH = Latch High, clear on read (note that if the condition exists following register read, the bit will not be
cleared).
Register 1.36869 - LASI Status (see also Table 1.36866 LASI Control)
Bit(s)
Name
Description
R/W1
1.36869.15:7
Reserved
Reserved
RO
1.36869.6
MON3P3V_IN supply
1 = 1.8V supply too low
RO/LH
1.36869.5
alarm
3.3V supply alarm
0 = no alarm
1 = 1.8V supply too low
RO/LH
1.8V supply alarm
0 = no alarm
1 = 1.8V supply too low
RO/LH
1.36869.3
LASI test data
0 = no alarm
Local fault condition detected in test data
RW
1.36869.2
RX_ALARM
1 = Local fault condition detected in RX_ALARM
RO2
1.36869.1
TX_ALARM
0 = No alarm
1 = Local fault condition detected in TX_ALARM
RO2
1.36869.0
LS_ALARM
0 = No alarm
1 = Local fault condition detected in status change
LH
1.36869.4
Default Value
0 = No status change
Register 1.49153 - Extended PMA Features
R/W1
Default Value
1 = RXLOSB_I override
RW
0
0 = no override
PMA Network loopback 1 = Transmit all idles at RxXAUI when in network
RW
Bit(s)
Name
Description
1.49153.15:11
Reserved
N/A
1.49153.10
RXLOSB_I override
1.49153.9
data out
loopback mode
0 = Receive data at RxXAUI when in network loopback
mode
N/A
1.49153.8:5
Reserved
1.49153.4
PMA Network loopback 1 = Enable network loopback
1.49153.3
mode
Reserved
1.49153.2
refmon
0 = REFCLK present
RO
1
1.49153.1
syn_err
1 = Recovered clock rate error
RO
1
1.49153.0
txlock
1 = Fiber transmit PLL in lock
RO
1
RW
0 = Disable network loopback
N/A
Notes:
1. RW = Read/Write, RO = Read Only, LH = Latch High, clear on read (note that if the condition exists following register read, the bit will not be
cleared.
2. The RX_ALARM and TX_ALARM indications are the logic OR of the contents of registers 0x9003 and 0x9004 respectively. Therefore, these alarms
will persist until the bit(s) reflecting the source of interrupt are cleared.
41
Register 1.49155 - PMA/PMD Vendor Specific
Bit(s)
Name
Description
R/W1
1.49155.15:14
EEPROM test mode
RW
1.49155.13
EEPROM detect
00 = 37kHz
01 = high frequency test mode
10 = debug mode - do not use
11 = debug mode - do not use
1 = Detected
RO
1.49155.12
EEPROM error
1 = EEPROM error
RO/LH
1.49155.11
EEPROM active
1 = EEPROM access in progress, MDIO writes to
EEPROM registers ignored
RO
1.49155.10:8
Reserved
RO
1.49155.7
EEPROM checksum OK 1 = OK
RO/LH
1.49155.6
Reserved
RO
1.49155.5:4
EEPROM 256 byte read Size Bit1 Bit0
cycle burst size
1
0
0
8
0 1
RW
16 1
256 1
Default Value
11
0
1
1.49155.3:2
Reserved
RO
1.49155.1:0
EEPROM 256 byte write Size Bit1 Bit0
cycle burst size
1
0
0
8
0 1
16 1 0
1
1
1
RW
01
R/W1
Default Value
Register 1.49156 - PMA/PMD Vendor Specific Checksum
Bit(s)
Name
1.49156.15:8
EEPROM calculated
RO
1.49156.7:4
checksum
Reserved
RO
1.49156.3:2
EEPROM 256 byte write Size Bit1 Bit0
1.49156.1:0
Description
cycle burst size
1
0
0
8
0
1
DOM write command
16 1 0
1
1
1
Bit1 Bit0 Command
0
0
RW
01
RW
Reserved
0
1
Reserved
1
0
Reserved
1
1
Write 256 bytes
Register 1.49188 - PMA Vendor Specific
Bit(s)
Name
Description
R/W1
1.49188.15:4
RO
Reserved
1.49188.3
TXPLLOUT frequency
1 = 10 GHz
0 = 156 MHz
1.49188.2
selection
Reserved
1.49188.1
TXPLLOUT enable
1 = enabled
RW
0
EEPROM_SCL tristate
0 = disabled
1 = tristate
RW
0
1.49188.0
RW
Default Value
0
RO
0 = not tristate
Notes:
1. RW = Read/Write, RO = Read Only, LH = Latch High, clear on read (note that if the condition exists following register read, the bit will not be
cleared.
42
HFCT-701XB Device 3 PCS Registers
Device
From
Decimal
Hex
To
Decimal
3
0
0
PCS Control 1
3
1
1
PCS Status 1
3
2
2
3
4
4
3
5
5
3
7
7
10G PCS Control 2
3
8
8
10G PCS Status 2
3
32
20
10GBASE-R PCS Status 1
3
33
21
10GBASE-R PCS Status 2
3
34
22
37
25
10GBASE-R PCS Test Pattern Seed A
3
38
26
41
29
10GBASE-R PCS Test Pattern Seed B
3
42
2A
10GBASE-R PCS Test Pattern Control
3
43
2B
10GBASE-R PCS Test Pattern Error Counter
3
49152
C000
PCS extended features
3
49153
C0001
49157
C005
3
49158
C006
49169
C011
3
Register Name
Hex
3
PCS Device identifier
PCS Speed Ability
6
6
PCS Devices in package
3
3
43
PCS Vendor Specific
Register 3.0 - PCS Control 1
Bit(s)
Name
Description
R/W1
3.0.15
PCS 64/66 Reset
RW/SC
3.0.14
PCSLoopback
3.0.13
Speed Selection
1 = PCS reset
0 = Normal operation
1 = Enable loopback mode
0 = Disable loopback mode
1 = Operation at 10 Gb/s and above
0 = Unspecified
3.0.12
Reserved
3.0.11
Low power
3.0.10:7
Reserved
3.0.6
Speed selection
3.0.5:2
Speed selection
3.0.1:0
Reserved
RW
Default Value
0
RW
RW
1 = Low power mode
0 = Normal operation
RW
1 = Operation at 10 Gb/s and above
0 = Unspecified
5432
0 0 0 0 = 10 Gb/s
RW
RW
RW
0000
RW
Register 3.1 - PCS Status 1
Bit(s)
Name
3.1.15:8
Reserved
3.1.7
Local fault
Description
R/W1
Default Value
RO
1 = Local fault condition detected
RO
0 = Local fault condition not detected
(Set to 1 when either 3.8.11 or 3.8.10 set to 1)
N/A
3.1.6:3
Reserved
3.1.2
PCS receive link status 1 = PCS receive link up
3.1.1
3.1.0
RO/LL
Low Power ability
0 = PCS receive link down
1 = PCS supports low power mode
RO
Reserved
0 = PCS does not support low power mode
N/A
RO
Register 3.2 to 3.3 - PCS Device Identifier
A mirror of Registers 1.2 to 1.3.
Register 3.4 - PCS Speed Ability
Bit(s)
Name
3.4.15:1
Reserved
3.4.0
10 G capable
Description
1 = PCS capable of operating at 10 Gb/s
0 = PCS is not capable of operating at 10 Gb/s
Register 3.5 to 3.6 - PCS Devices in Package
A mirror of Registers 1.5 to 1.6.
Note:
1. RW = Read/Write, SC = Self Clearing, RO = Read Only, LL = Latching Low.
44
R/W1
Default Value
RO
N/A
RO
1
Register 3.7 - 10 G PCS Control 2
Bit(s)
Name
Description
3.7.15:2
Reserved
N/A
3.7.1:0
PCS type selection
10
R/W1
Default Value
RW
00
Default Value
0 0 = Select 10GBASE-R PCS type
Register 3.8 - 10 G PCS Status 2
Bit(s)
Name
Description
R/W1
3.8.15:14
Device present
15 14
RO
1
0 = Device responding at this address
1
0
1 = No device responding at this address
1 = No device responding at this address
3.8.13:12
Reserved
0 0 = No device responding at this address
N/A
RO
3.8.11
Transmit local fault
1 = Local fault condition on transmit path
RO/LH
Receive local fault
0 = No local fault condition on transmit path
1 = Local fault condition on receive path
RO/LH
3.8.9:3
Reserved
0 = No local fault condition on receive path
N/A
RO
3.8.2
10GBASE-W capable
1 = PCS is able to support 10GBASE-W PCS type
RO
10GBASE-X capable
0 = PCS is not able to support 10GBASE-W PCS type
1 = PCS is able to support 10GBASE-X PCS type
RO
10GBASE-R capable
0 = PCS is not able to support 10GBASE-X PCS type
1 = PCS is able to support 10GBASE-R PCS type
RO
3.8.10
3.8.1
3.8.0
0 = PCS is not able to support 10GBASE-R PCS type
Register 3.32 - 10GBASE-R PCS Status 1
Description
R/W1
Bit(s)
Name
3.32.15:13
Reserved
3.32.12
10GBASE-R receive link 1 = 10GBASE-R PCS receive link up
RO
3.32.11:3
status
Reserved
RO
3.32.2
PRBS31 pattern testing 1 = PCS is able to support PRBS31 pattern testing
RO
3.32.1
ability
10GBASE-R PCS high
0 = PCS is not able to support PRBS31 pattern testing
1 = 10GBASE-R PCS reporting a high BER
RO
3.32.0
BER
10GBASE-R PCS block
0 = 10GBASE-R PCS not reporting a high BER
1 = 10GBASE-R PCS locked to received blocks
RO
lock
0 = 10GBASE-R PCS not locked to received blocks
Default Value
RO
0 = 10GBASE-R PCS receive link down
Notes:
1. RW = Read/Write, RO = Read Only, LH = Latch High, clear on read (note that if the condition exists following register read, the bit will not be
cleared.
45
Register 3.33 - 10GBASE-R PCS Status 2
Bit(s)
Name
Description
R/W1
3.33.15
Latched block lock
RO/LL
3.33.14
Latched high BER
3.33.13:8
BER
1 = PCS has reported block lock since last read
0 = PCS has not reported block lock since last read
1 = PCS has reported high BER since last read
0 = PCS has not reported high BER since last read
BER counter
RO/NR
3.33.7:0
Errored blocks
Jitter pattern checker
RO/NR
Default Value
RO/LH
Register 3.34 to 3.37 - 10GBASE-R PCS Test Pattern Seed A
Bit(s)
Name
Description
R/W1
3.37.15:10
Reserved
Value always 0, writes ignored
RW
3.37.9:0
Test pattern seed A 3
Test pattern seed A bits 48-57
RW
3.36.15:0
Test pattern seed A 2
Test pattern seed A bits 32-47
RW
3.35.15:0
Test pattern seed A 1
Test pattern seed A bits 16-31
RW
3.34.15:0
Test pattern seed A 0
Test pattern seed A bits 0-15
RW
Default Value
Register 3.38 to 3.41 - 10GBASE-R PCS Test Pattern Seed B
Bit(s)
Name
Description
R/W1
3.41.15:10
Reserved
Value always 0, writes ignored
RW
3.41.9:0
Test pattern seed B 3
Test pattern seed B bits 48-57
RW
3.40.15:0
Test pattern seed B 2
Test pattern seed B bits 32-47
RW
3.39.15:0
Test pattern seed B 1
Test pattern seed B bits 16-31
RW
3.38.15:0
Test pattern seed B 0
Test pattern seed B bits 0-15
RW
Default Value
Register 3.42 - 10GBASE-R PCS Test Pattern Control
Default Value
Bit(s)
Name
Description
R/W1
3.42.15:6
Reserved
Value always 0, writes ignored
RW
3.42.5
PRBS31 receive test
1 = Enable PRBS31 test pattern mode on the receive
RW
0
pattern
path
0 = Disable PRBS31 test pattern mode on the receive
RW
0
3.42.4
PRBS31 transmit test
pattern
3.42.3
3.42.2
3.42.1
3.42.0
path
1 = Enable PRBS31 test pattern mode on the transmit
path
0 = Disable PRBS31 test pattern mode on the transmit
Transmit test pattern
path
1 = Enable transmit test pattern testing
RW
Receive test pattern
0 = Disable transmit test pattern testing
1 = Enable receive test pattern testing
RW
Test pattern select
0 = Disable receive test pattern testing
1 = Square wave test pattern
RW
Data pattern select
0 = Pseudo random test pattern
1 = Zeros data pattern
RW
0 = LF data pattern
Notes:
1. RW = Read/Write, RO = Read Only, LL = Latching Low, LH = Latch High, clear on read (note that if the condition exists following register read, the
bit will not be cleared, NR = Non Roll-Over.
46
Register 3.43 - 10GBASE-R PCS Test Pattern Error Counter
Bit(s)
Name
Description
R/W1
3.43.15:0
RO/NR
Test pattern error
Error counter
counter
LSB = bit 0
MSB = bit 15
Default Value
Register 3.49152 - PCS Extended Features
Bit(s)
Name
Description
R/W1
3.49152.15:8
Diagnostic Register
Diagnostic register
RO
3.49152.7:6
Reserved
N/A
3.49152.5
PCS loopback data out 1 = Transmit data at TXOUT when in PCS loopback mode RW
0
3.49152.4
Reset transmit PCS
0 = Transmit a square wave when in PCS loopback mode
1 = Not reset
RW
1
Reset receive PCS
0 = ResetNote: not self clearing
1 = Not reset
RW
1
3.49152.2
TX scrambler bypass
0 = ResetNote: not self clearing
1 = Bypass
RW
0
3.49152.1
RX scrambler bypass
1 = Bypass
RW
0
3.49152.0
64/66 encoder error
1 = Error
RO/LH
0
R/W1
Default Value
Default Value
3.49152.3
Register 3.49152 - 3.49157 - PCS Vendor Specific
Bit(s)
Name
Description
3.49152.15:0
3.49153.15:0
3.49154.15:0
Default Value
Diagnostic registers
3.49155.15:0
3.49156.15:0
3.49157.15:0
Register 3.49158 - PCS Vendor Specific
Bit(s)
Name
Description
R/W1
3.49158.15:7
Vendor Specific
Reserved
RO
3.49158.6:0
Receive Frame Offset
RO
Register 3.49159 - PCS Vendor Specific Receive Path PACKET Checker
Bit(s)
Name
Description
R/W1
3.49159.15:0
RO/LH
First 16 bits of XGMII
1 = error at this bit location
Default Value
bus error flag
Register 3.49160 - PCS Vendor Specific Receive Path PACKET Checker
Bit(s)
Name
Description
R/W1
3.49160.15:0
Second 16 bits of
1 = error at this bit location
RO/LH
Default Value
XGMII bus error flag
Register 3.49161 - PCS Vendor Specific Receive Path PACKET Checker
Bit(s)
Name
Description
R/W1
3.49161.15:6
Vendor Specific
RO
3.49161.5
rx_idle_err_flag
Received a full packet but with start or idle errors
RO/LH
3.49161.4
rx_start_err_flag
Received a full packer but with preamble errors
RO/LH
3.49161.3
rx_data_err_flag
Received a full packet but long packet
RO/LH
3.49161.2
rx_long_pkt_flag
Received a full packet but long packet
RO/LH
3.49161.1
rx_short_pkt_flag
Received a full packet but short packet
RO/LH
3.49161.0
rx_term_err_flag
Set if terminate received but the next byte is not an idle
RO/LH
Reserved
Default Value
Notes:
1. RW = Read/Write, RO = Read Only, LH = Latch High, clear on read (note that if the condition exists following register read, the bit will not be
cleared, NR = Non Roll-Over.
47
Register 3.49162 - PCS Vendor Specific Transmit Path PACKET Checker
Bit(s)
Name
Description
R/W1
3.49162.15:0
First 16 bits of XGMII
1 = error at this bit location
RO/LH
Default Value
bus error flag
Register 3.49163 - PCS Vendor Specific Transmit Path PACKET Checker
Bit(s)
Name
Description
R/W1
3.49163.15:0
Second 16 bits of
1 = error at this bit location
RO/LH
Default Value
XGMII bus error flag
Register 3.49164 - PCS Vendor Specific PACKET Generator/Checker
Bit(s)
Name
3.49164.15:6
Packet generator idle
3.49164.5
size
tx_idle_err_flag
Description
R/W1
Default Value
RW
Received a full packet but with start or idle errors
RO/LH
3.49164.4
tx_start_err_flag
Received a full packet but with preamble errors
RO/LH
3.49164.3
tx_data_err_flag
Received a full packet but with long packet
RO/LH
3.49164.2
tx_long_pkt_flag
Received a full packet but with long packet
RO/LH
3.49164.1
tx_short_pkt_flag
Received a full packet but with short packet
RO/LH
3.49164.0
tx_term_err_flag
Set if terminate received but the next byte is not an idle
RO/LH
Register 3.49165 - PCS Vendor Specific PACKET Generator
Bit(s)
Name
Description
R/W1
3.49165.15:0
Fixed pattern
First 16 bits of XGMII
RW
Default Value
Register 3.49166 - PCS Vendor Specific PACKET Generator
Bit(s)
Name
Description
R/W1
3.49166.15:0
Fixed pattern
Second 16 bits of XGMII
RW
Default Value
Register 3.49167 - PCS Vendor Specific PACKET Generator
Name
Description
R/W1
3.49167.15:14
Vendor Specific
Reserved
RO
3.49167.13
3.49167.12
Tx path pattern checker 1 = enabled
0 = disabled
Tx path pattern
1 = enabled
3.49167.11
generator
0 = disabled
Rx path pattern checker 1 = enabled
3.49167.10
Rx path pattern
0 = disabled
1 = enabled
3.49167.9
generator
Packet type
0 = disabled
1 = increment pattern
RW
Bit(s)
Default Value
RW
0
RW
0
RW
0
RW
0
0 = fixed pattern
3.49167.8:0
Data packet size
RW
divided by 4
Notes:
1. RW = Read/Write, RO = Read Only, LH = Latch High, clear on read (note that if the condition exists following register read, the bit will not be
cleared.
48
Register 3.49169 - PCS Vendor Specific
R/W1
Bit(s)
Name
3.49169.15:2
Reserved
Description
3.49169.1
Gearbox FIFO error
Diagnostic register
RO
3.49169.0
Frame sync FIFO error
Diagnostic register
RO
RO
Note:
1. RW = Read/Write, RO = Read Only.
HFCT-701XB Device 4 PHYXS Registers
Device
From
Decimal
Hex
4
0
0
PHY XS Control 1
4
1
1
PHY XS Status 1
4
2
2
4
4
4
4
5
5
4
8
8
4
14
E
4
24
18
10G PHY XGXS Lane Status
4
25
19
10G PHY XGXS Test Control
4
49152
C000
PHY_XS Extended Features
4
49153
C001
PHY_XS Extended Features
4
49154
C002
49
To
Decimal
3
Register Name
Hex
3
PHY XS Device identifier
PHY XS Speed Ability
6
6
PHY XS Devices in package
PHY XS Status 2
15
49160
F
C008
PHY XS Package identifier
PHY_XS Vendor Specific
Default Value
Register 4.0 - PHY_XS Control 1
Bit(s)
Name
Description
R/W1
4.0.15
Global Reset
RW/SC
4.0.14
Loopback
4.0.13
Speed selection
1 = reset
0 = Normal operation
1 = Enable PHY XS loopback mode
0 = Disable PHY XS loopback mode
1 = Operation at 10 Gb/s and above
0 = Unspecified
4.0.12
Reserved
4.0.11
Low power
4.0.10:7
Reserved
4.0.6
Speed selection
4.0.5:2
Speed selection
4.0.1:0
Reserved
RW
Default Value
0
RW
RW
1 = Low power mode
0 = Normal operation
RW
1 = Operation at 10 Gb/s and above
0 = Unspecified
5432
0 0 0 0 = 10 Gb/s
Value always 0, writes ignored
RW
RW
RW
0000
RW
Register 4.1 - PHY_XS Status 1
Bit(s)
Name
Description
R/W1
4.1.15:8
Reserved
N/A
RO
4.1.7
Local fault
RO
4.1.6:3
Reserved
1 = Local fault condition detected on PHY XS
0 = Local fault condition not detected on PHY XS
N/A
RO
4.1.2
PHY XS transmit link
1 = The PHY XS transmit link is up
RO/LL
4.1.1
status
Low Power ability
0 = The PHY XS transmit link is down
1 = PHYXS supports low power mode
RO
Reserved
0 = PHYXS does not support low power mode
N/A
RO
4.1.0
Default Value
1
Register 4.2 to 4.3 - Device Identifier
A mirror of Registers 1.2 to 1.3.
Register 4.4 - PHY_XS Speed Ability
Bit(s)
Name
4.4.15:1
Reserved for future
speeds
10 G capable
4.4.0
Description
Default Value
RO
1 = PHYXS is capable of operating at 10 Gb/s
0 = PHYXS is not capable of operating at 10 Gb/s
Register 4.5 to 4.6 - Device in Package
A mirror of Registers 1.5 to 1.6.
Notes:
1. RW = Read/Write, SC = Self Clearing, RO = Read Only, LL = Latching Low.
50
R/W1
RO
1
Register 4.8 - PHY_XS Status 2
Bit(s)
Name
Description
R/W1
Default Value
4.8.15:14
Device present
15 14
RO
10
1 0 = Device responding at this address
1 1 = No device responding at this address
0 1 = No device responding at this address
4.8.13:12
Reserved
0 0 = No device responding at this address
N/A
4.8.11
Transmit local fault
1 = Local fault condition on transmit path of PHY XS
RO/LH
Receive local fault
0 = No local fault condition on transmit path of PHY XS
1 = Fault condition on receive path of PHY XS
RO/LH
Reserved
0 = No fault condition on receive path of PHY XS
N/A
RO
4.8.10
4.8.9:0
Register 4.14 to 4.15 - Package Identifier (OUI)
A mirror of Registers 1.32818 to 1.32821.
Register 4.24 - 10G PHY_XGXS Lane Status
Default Value
Bit(s)
Name
Description
R/W1
4.24.15:13
Reserved
N/A
RO
4.24.12
PHY XGXS lane
alignment status
Pattern testing ability
1 = PHY XGXS transmit lanes aligned
0 = PHY XGXS transmit lanes not aligned
1 = PHY XGXS is able to generate test patterns
0 = PHY XGXS is not able to generate test patterns
1 = PHY XGXS has the ability to perform a loopback
function
0 = PHY XGXS does not have the ability to perform a
loopback function
N/A
RO
1 = Lane 3 is synchronized
0 = Lane 3 is not synchronized
1 = Lane 2 is synchronized
0 = Lane 2 is not synchronized
1 = Lane 1 is synchronized
0 = Lane 1 is not synchronized
1 = Lane 0 is synchronized
0 = Lane 0 is not synchronized
RO
N/A
RO
N/A
RO
N/A
RO
N/A
Default Value
4.24.11
4.24.10
PHY XGXS loopback
ability
4.24.9:4
Reserved
4.24.3
Lane 3 sync
4.24.2
Lane 2 sync
4.24.1
Lane 1 sync
4.24.0
Lane 0 sync
RO
1
RO
1
RO
Register 4.25 - 10 G PHY_XGXS Test Control
Bit(s)
Name
Description
R/W1
4.25.15:3
Reserved
N/A
RW
4.25.2
Receive test pattern
enable
Test pattern select
1 = Receive test pattern enabled
0 = Receive test pattern not enabled
10
1 1 = Reserved
RW
4.25.1:0
0
RW
1 0 = Mixed frequency test pattern
0 1 = Low frequency test pattern
0 0 = High frequency test pattern
Notes:
1. RW = Read/Write, RO = Read Only, LH = Latch High, clear on read (note that if the condition exists following register read, the bit will not be
cleared.
51
Register 4.49152 - PHY_XS Extended Features
Bit(s)
Name
4.49152.15
XAUI system loopback 1 = Transmit data at TXOUT when in PHY_XS loopback
data out enable
Description
R/W1
Default Value
RW
0
mode
4.49152.14
0 = Transmit all 1's when in PHY_XS loopback mode
XAUI system loopback 1 = Enable XAUI loopback
RW
0
4.49152.13
(Tx - >Rx path) enable
XAUI PRBS enable
1 = Enable PRBS
RW
0
4.49152.12
XAUI analog monitor
1 = XAUI lane 3 recovered data
4.49152.11:8
point control
Reserved
0 = XAUI lane 3 recovered clock
N/A
4.49152.7
Lane 3 locked
1 = lane 3 in lock
RO
N/A
4.49152.6
Lane 2 locked
1 = lane 2 in lock
RO
N/A
4.49152.5
Lane 1 locked
1 = lane 1 in lock
RO
N/A
4.49152.4
Lane 0 locked
1 = lane 0 in lock
RO
N/A
4.49152.3
XAUI PLL locked
1 = XAUI PLL locked
RO
N/A
4.49152.2
XAUI external reference 1 = external clock
RW
0
4.49152.1
clock mode
Receive XGXS reset
RW
1
RW
1
Default Value
0 = internal reference clock
1 = Not reset
0 = Reset
4.49152.0
Transmit XGXS reset
Note: not self clearing
1 = Not reset
0 = Reset
Note: not self clearing
Register 4.49153 - PHY_XS Extended Features
Bit(s)
Name
Description
R/W1
4.49153.15:8
Reserved
N/A
RO
4.49153.7
XAUI lane 7 PRBS error 1 = error
RO/LH
4.49153.6
XAUI lane 6 PRBS error 1 = error
RO/LH
4.49153.5
XAUI lane 5 PRBS error 1 = error
RO/LH
4.49153.4
XAUI lane 4 PRBS error 1 = error
RO/LH
4.49153.3
XAUI lane 3 PRBS error 1 = error
RO/LH
-
4.49153.2
XAUI lane 2 PRBS error 1 = error
RO/LH
-
4.49153.1
XAUI lane 1 PRBS error 1 = error
RO/LH
-
4.49153.0
XAUI lane 0 PRBS error 1 = error
RO/LH
-
Notes:
1. RW = Read/Write, RO = Read Only.
52
Register 4.49154 - PHY_XS Vendor Specific
Default Value
Bit(s)
Name
Description
R/W1
4.49154.15:10
Vendor Specific
Reserved
RO
4.49154.9
1 = Overflow(linked to 1.36868.2)
RO/LH
Note 2
4.49154.8
XGXS Tx rate adjust
overflow
XGXS Tx rate adjust
1 = Underflow(linked to 1.36868.2)
RO/LH
Note 2
4.49154.7
underflow
XGXS Rx rate overflow 1 = Overflow(linked to 1.36867.6)
RO/LH
Note 2
4.49154.6
XGXS Rx rate adjust
1 = Underflow(linked to 1.36867.6)
RO/LH
Note 2
4.49154.5:0
underflow
Vendor Specific
Reserved
RO
-
R/W1
Default Value
Register 4.49155 - PHY_XS Vendor Specific
Bit(s)
Name
4.49155.15:12
Sync offset XAUI
channel 3
Sync offset XAUI
channel 2
Sync offset XAUI
4.49155.11:8
4.49155.7:4
4.49155.3:0
Description
RO
RO
RO
channel 1
Sync offset XAUI
channel 0
RO
Register 4.49156 - PHY_XS Vendor Specific
Bit(s)
Name
4.49156.15:12
Align offset XAUI
channel 3
Align offset XAUI
channel 2
Align offset XAUI
4.49156.11:8
4.49156.7:4
4.49156.3:0
Description
R/W1
Default Value
RO
RO
RO
channel 1
Align offset XAUI
channel 0
RO
Register 4.49157 - PHY_XS Vendor Specific
Bit(s)
Name
Description
R/W1
4.49157.15
PHY_XS phase_err3
XAUI lane 3 clock phase error, clear on read
RO
4.49157.14
PHY_XS phase_err2
XAUI lane 2 clock phase error, clear on read
RO
4.49157.13
PHY_XS phase_err1
XAUI lane 1 clock phase error, clear on read
RO
4.49157.12
PHY_XS phase_err0
XAUI lane 0 clock phase error, clear on read
RO
4.49157.11:0
Vendor Specific
Reserved
RO
Default Value
Notes:
1. RW = Read/Write, RO = Read Only, LH = Latch High, clear on read (note that if the condition exists following register read, the bit will not be
cleared.
2. This bit is linked to an MDIO latched high diagnostic alarm register bit. When either register is read, both bits will be cleared.
53
Register 4.49158 - PHY_XS Vendor Specific
Bit(s)
Name
Description
R/W1
4.49158.15:8
Vendor Specific
Reserved
RO
4.49158.7
Lane 3 upper byte
10B/8B decode error
RO/LH
4.49158.6
Lane 2 upper byte
10B/8B decode error
RO/LH
4.49158.5
Lane 1 upper byte
10B/8B decode error
RO/LH
4.49158.4
Lane 0 upper byte
10B/8B decode error
RO/LH
4.49158.3
Lane 3 lower byte
10B/8B decode error
RO/LH
4.49158.2
Lane 2 lower byte
10B/8B decode error
RO/LH
4.49158.1
Lane 1 lower byte
10B/8B decode error
RO/LH
4.49158.0
Lane 0 lower byte
10B/8B decode error
RO/LH
Default Value
Register 4.49160 - PHY_XS Vendor Specific
Bit(s)
Name
Description
R/W1
4.49160.15:0
PHY_XS receive code
violation counter
Clear on read
Bit0 = LSB
RO/NR
Default Value
Bit15 = MSB
Note: in Tx path
Notes:
1. RW = Read/Write, RO = Read Only, LH = Latch High, clear on read (note that if the condition exists following register read, the bit will not be
cleared, NR = Non Roll-Over.
54
Regulatory Compliance
The HFCT-701XB is intended to
enable commercial system
designers to develop equipment
that complies with the various
regulations governing
Certification of Information
Technology equipment (see Table
15).
Electrostatic Discharge (ESD)
There are two design cases in
which immunity to ESD damage
is important. The first case is
during handling of the
transceiver prior to plugging into
the circuit board. It is important
to use normal ESD handling
precautions for ESD sensitive
devices. These precautions
include using grounded wrist
straps, work benches and floor
mats in ESD controlled areas.
The second case to consider is
static charges to the exterior of
the equipment chassis containing
the transceiver parts. To the
extent that the SC duplex
connector is exposed to the
outside of the equipment chassis
it may be subject to whatever
ESD system level criteria that
the equipment is intended to
meet.
Electromagnetic Interference (EMI)
Most equipment design utilizing
these high speed transceivers
from Agilent will be required to
meet the requirements of FCC in
the United States, CENELEC
EN55022 (CISPR 22) in Europe
and VCCI in Japan. Performance
of the HFCT-701XB transceiver
is dependent upon customer
board and chassis design.
Immunity
Equipment utilizing these
transceivers will be subject to
radio frequency electromagnetic
fields in some environments.
These transceivers have been
characterized without the
benefit of the normal equipment
chassis enclosure and results are
reported below. Performance of
a system containing these
transceivers within a welldesigned chassis enclosure is
expected to be better than the
results of these tests without a
chassis enclosure.
Glossary
PHY = Module = Used
interchangeably with HFCT701XB in this document.
Network = Used to indicate
elements that are on the optical
side of the module.
Network loopback = A signal
path within the module from the
optical input of the module to
the optical output of the module.
System = Used to indicate
elements that are on the
electrical side of the module.
System loopback = A signal path
within the module from the
electrical input of the module to
the electrical output of the
module.
Table 15. Regulatory Compliance - Typical Performance
Feature
Test Method
Performance
General
Telcordia GR-468-CORE
Qualified in accordance with Remote terminal requirements
Electrostatic Discharge - Human Body
MIL STD 883 Method 3015
500 V
Model
Electrostatic Discharge - Charged Device
JEDEC JES D22-C101
500 V
Model
Electrostatic Discharge - Contact Discharge IEC 61000-4-2
8000 V
Electromagnetic Interference
FCC Class BCENELEC EN55022 Class B
Margins are dependant on customer board and chassis
Immunity
(CISPR 22B) VCCI Class 2
Variation of IEC 61000-4-3
design
A BER of better than 1E-12 was observed from a 10 V/m
Eye Safety
IEC 60825/CDRH Class 1
field swept from 27 MHz to 1 GHz.
CDRH: 9521220-51
TUV: 933/510230/01
55
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semiconductors
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Data subject to change.
Copyright © 2003 Agilent Technologies, Inc.
January 23, 2003
5988-8667EN