ETC HPLL-8001

PLL Frequency Synthesizer
Technical Data
HPLL-8001
Features
Description
Plastic SOP-14
• Low Operating Current
Consumption (4 mA, typ.)
HP
800 LL
YY 1
WW
• High Input Sensitivity, High
Input Frequencies (50 MHz)
• Synchronous Programming of
the Counters (n-, n/a-,
r-counters)
• Switchable Modulus Trigger
Edge
Pin Configuration
1
LD
VSS
EN
• Serial Control 3-wire Bus:
Data, Clock (<10 MHz), Enable
• Switchable Polarity and
Programmable Phase Detector
Current
14
REFI
HPLL
8001
YYWW
• Large Dividing Ratios for
Small Channel Spacing,
A counter 0 to 127, N counter
3 to 16,380, R counter 3 to
65,535
DATA
CLK
PO2
PO1
AVDD
PD
AVSS
VDD
The HPLL-8001 is a phase-locked
loop (PLL) frequency synthesizer
intended for use in a frequency
generation loop with an external
dual modulus prescaler and VCO.
The VCO frequency is divided by
the dual modulus prescaler, which
is then fed to the internal A and N
counters. The reference frequency
is fed to an internal R counter to
define the channel spacing. Both
frequencies are compared in the
phase detector which drives the
charge pump. A lock detect is
provided to monitor the lock state
of the loop. All blocks are
programmed by a serial 3-wire
bus interface.
VCOI
MOD
7
8
• 2 Programmable Outputs
• Digital Phase Detector
Output Signals (e.g. for
External Charge Pump)
• DRFI, DVFI Outputs (e.g. for
Prescaler Standby)
• Lock Detect Output with
Gated Anti-backlash Pulse
(quasi digital lock detect)
Applications
• GSM Handsets and Base
Stations
Functional Block Diagram
DATA
CLOCK
ENABLE
REFI
Serial
Control Logic
PD
16 bit R
counter
DRFI
PO1
7 bit A
counter
VCOI
14 bit N
counter
Detector
Modulus
Control
Analog
Control
Logic
• DECT
VDD VSS AVDD AVSS
Charge
Lock
Detect
LD
Pump
DVFI
• PCS/PCN
• Wireless LAN
Phase
MOD
PO2
2
HPLL-8001 Absolute Maximum Ratings[1]
Symbol
VCC
PT
Pin
Tj
TSTG
Parameter
Supply Voltage
Power Dissipation [2, 3]
RF Input Power
Junction Temperature
Storage Temperature
Units
Absolute
Maximum
V
mW
dBm
°C
°C
7
400
+15
150
-65 to 150
Thermal Resistance[2]:
θjc = 150°C/W
Notes:
1. Permanent damage may occur if
any of these limits are exceeded.
2. Tcase = 25°C.
3. Derate at 7 mW/°C for Tcase > 90°C.
Recommended operating range of Vcc = 2.7 to 5.5 V, Ta = - 40 to +85°C.
HPLL-8001 Summary Characterization Information
Standard test conditions apply unless otherwise noted.
Current Consumption
Symbol
Is
Parameters and Test Conditions
Current Consumption [1]
@ VDD = 4.5 – 5.5 V
@ VDD = 2.7 – 3.0 V
Standby
Units
Typ.
mA
mA
µA
6.8
3.1
0.06
Note:
1. FVF = 50 MHz, VVF = 150 mVrms, FRF = 50 MHz, VRF = 150 mVrms, IPD = 0.250 mA, IREF = 100 µA
VCO Input Frequency (pin 8), Reference Input Frequency (pin 1)
Symbol
Parameters and Test Conditions
FREFI
Reference Frequency Range
FVCOI
Oscillator Frequency Range[2]
Dual Mode
Units
Typ.
VREFI = 100 mVrms
VREFI = 100 mVrms
VDD = 4.5 V
VDD = 2.7 V
MHz
MHz
4 - 60
4 - 30
VVCOI = 200 mVrms
VVCOI = 200 mVrms
VDD = 4.5 V
VDD = 2.7 V
MHz
MHz
4 - 65
4 - 30
Single HF Mode
VVCOI = 200 mVrms
VVCOI = 200 mVrms
VDD = 4.5 V
VDD = 2.7 V
MHz
MHz
4 - 160
4 - 100
Single LF Mode
VVCOI = 100 mVrms
VVCOI = 100 mVrms
VDD = 4.5 V
VDD = 2.7 V
MHz
MHz
4 - 90
4 - 35
Note:
2. Minimum Slew Rate = 4 V/ms, Input Capacitance = 4 pF
Input Current low = 150 µA, Input Current high = 150 µA
3
Inputs EN (pin 3), Data (pin 4), CLK (pin 5)
Symbol
Parameters and Test Conditions
Units
VIL
Voltage Input Low at IIL = 10 µA
V
VIH
Voltage Input High at IIH = 100 µA
V
FCLK
Clock Frequency
TR , TF
Min
Typ
Max
0.3VDD
0.7VDD
MHz
10
Rise and Fall Time of CLK
µs
1
TCLW
CLK Pulse Width (high)
ns
60
TDS
Data Setup Time
ns
20
TCLES
CLK-Enable Setup Time
ns
20
TECLS
Enable-CLK Setup Time
ns
20
TENW
EN Pulse Width (high)
ns
60
Propagation Delay Time (Enable - Port 1)
µs
1
Note:
These values are valid under the following conditions: VDD = 2.7 to 5.5 V.
VIH
CLK
VIL
TDS
VOH
DATA
VOL
VOH
EN
VOL
TCLES
TECLS
4
Output MOD Modulus Control (pin 7)
Symbol
Parameters and Test Conditions
VOH
Voltage Output High
VOL
Voltage Output Low
TR, TF
Rise and Fall Time
Units
Min
IOH = 2 mA, VDD = 4.5 – 5.5 V
V
VDD – 0.4
IOH = 1.2 mA, VDD = 2.7 – 3.3 V
V
VDD – 0.4
IOL = 0.5 mA, VDD = 4.5 – 5.5 V
V
0.8
IOL = 0.3 mA, VDD = 2.7 – 3.3 V
V
0.8
VDD = 4.5 – 5.5 V, CL = 5 pF
ns
1
3
VDD = 2.7 – 3.3 V, CL = 5 pF
ns
3
6
ns
6
9
ns
15
17
TPHL , TPL H
Propagation Delay from high to low and low to high
(VCOI to MOD)
VDD = 4.5 – 5.5 V, CL = 5 pF
VDD = 2.7 – 3.3 V, CL = 5 pF
VIH
FI
50%
VIL
TPLH
TPLH
VOH
MOD
pos-edge
50%
50%
VOL
TPLH
TPLH
VOH
MOD
neg-edge
VOL
50%
Typ
Max
5
Output PD Phase Detector (pin 10)
Symbol
Parameters and Test Conditions
B14
B13
B12
Units
Typ.
0
0
0
mA
0.15
0
0
1
mA
0.21
0
1
0
mA
0.31
Icp
0
1
1
mA
0.44
(VDD = 4.5 – 5.5 V)
1
0
0
mA
0.63
1
0
1
mA
0.89
1
1
0
mA
1.26
1
1
1
mA
1.69
nA
0.1
Standby
Icp
(VDD = 2.7 – 3.3 V)
0
0
0
mA
0.14
0
0
1
mA
0.20
0
1
0
mA
0.29
0
1
1
mA
0.40
1
0
0
mA
0.58
1
0
1
mA
0.79
1
1
0
mA
1.06
1
1
1
mA
1.26
nA
0.1
Standby
REFI
VCOI
DRFI
pos.
edge
neg.
edge
DVFI
PD
pos.
+lprog
tri-st.
-lprog
PD
neg.
+lprog
tri-st.
-lprog
LD
high
resist.
LOW
(pos.)
PHIR
(neg.)
PHIV
(pos.)
(neg.)
fv < fr
fv > fr
fv = fr
6
Input-Output PO2 Programmable Input-Output (pin 13)
Symbol
VOH
VOL
TF
TR
VREF
Parameters and Test Conditions
Units
Min
IOH = 2 mA, VDD = 4.5 – 5.5 V
V
VDD – 0.8
IOH = 1.2 mA, VDD = 2.7 – 3.3 V
V
VDD – 0.8
IOL = 2 mA, VDD = 4.5 – 5.5 V
V
0.8
IOL = 1.2 mA, VDD = 2.7 – 3.3 V
V
0.8
VDD = 4.5 – 5.5 V, MF01, MF02, CL = 10 pF
ns
3
4
VDD = 2.7 – 3.3 V, MF01, MF02, CL = 10 pF
ns
5
6
VDD = 4.5 – 5.5 V, MF01, MF02, CL = 10 pF
ns
6
7
VDD = 2.7 – 3.3 V, MF01, MF02, CL = 10 pF
ns
12
14
Voltage Output High
Voltage Output Low
Fall Time
Rise Time
Reference Voltage, Iref = 100 µA
Typ
Max
V
0.8
1.1
1.3
Units
Min
Typ
Max
Output LD Lock Detect (pin 14)
Symbol
VOL
TF
Parameters and Test Conditions
Voltage Output Low
IOL = 0.5 mA, VDD = 5 V
V
0.8
IOL = 0.5 mA, VDD = 2.7 V
V
0.8
VDD = 4.5 – 5.5 V
ns
5
6
VDD = 2.7 – 3.3 V
ns
8
10
Fall Time
Tr
VIH
Tf
90%
90%
INPUT
10%
10%
VIL
TPLH
TPLH
VOH
OUTPUT
50%
50%
VOL
TW
7
HPLL-8001 Pin Description Table
No. Mnemonic
Description
Typical Signal
1
REFI
Reference Frequency
High sensitivity preamplifier input for the r-counter.
The input can be AC-coupled for small input signals or
DC-coupled for large input signals.
2
VSS
Ground for digital logic
0V
3
EN
3-wire interface: Enable
Enable line of the serial interface with internal pull-up
resistor. When EN=H, the input signal CLK and DATA are
internally disabled. When EN=L, the received data is
transferred to the latches on the positive edge of the EN
signal.
4
DATA
3-wire interface: Data
Serial DATA input with internal pull-up resistor. The last two
bits before the EN-signal define the destination address.
5
CLK
3-wire interface: Clock
Clock line with internal pull-up resistor. The serial DATA is
read into the internal shift register on the positive edge (see
pulse diagram for serial data control).
6
VDD
Positive supply voltage for
digital logic
7
MOD
Modulus Control
For an external dual modulus prescaler. The modulus output
is low at the beginning of the cycle. When the a-counter has
reached its set value, MOD switches to high. When the ncounter has reached its set value, MOD switches to low and
the cycle starts again. When the prescaler has the counter
factor P or P+1 (P for MOD=H, P+1 for MOD=L), the overall
scaling factor is NP+A. The value of the a-counter must be
smaller than that of the n-counter. The trigger edge of the
modulus signal to the input signal can be selected (see
programming tables and MOD A, B) according to the needs
of the prescaler.
In single modulus operation and for standby operation,
the output is low.
8
VCOI
VCO frequency
High sensitivity preamplifier input for the n-counter. The
input can be AC-coupled for small input signals or
DC-coupled for large input signals.
9
AVSS
Ground for analog logic
Pins VDD and AVDD and also pins VSS and AVSS must have
the same power supply voltage.
10
PD
Phase detector
Tristate charge pump output. The level of the charge pump
output current can be programmed using the digital interface.
frequency FV<FR or FV lagging: p source active
frequency FV>FR or FV leading: n source active
frequency FV=FR & PLL locked: PD tristate
standby mode:
PD tristate
The polarity of the output signals of the phase detector can be
programmed.
11
AVDD
Positive supply voltage for
analog logic
8
HPLL-8001 Pin Description Table, continued
No. Mnemonic
Description
Typical Signal
12
PO1
Programmable output
Multifunction Output for the signals FRN , φV , φVN and
PROBIT (FRN, φV are the inverted signals of FR, φVN).
13
PO2
Programmable I/O
For the output signals FVN, φRN and the input signal IREF
- The signals φR and φV are the digital output signals of the
phase and frequency detector for use with external active
current sources.
- The signals FRN and FVN are the scaled down signals of the
reference frequency and VCO-frequencies.
- The programmed bit PROBIT is assigned to PO1 output in
the internal charge pump mode. The standby mode does not
affect this function.
- In the internal charge pump mode the input signal IREF
determines the value of the PD-output current.
14
LD
Lock detect
Unipolar output of the phase detector in the form of a pulsewidth modulated signal. The LD-pulse width corresponds
to the phase difference. In the locked state the LD-signal is at
H-level. In standby mode the output is resistive.
Programmable Reference Divider (R Counter Register)
1
1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
A5
A6
A7
Note: R16 is the MSB of the R counter value. R16 is the first bit which is transferred to the HPLL-8001.
Programmable Dividers (N and A Counter Registers)
Dual Mode
0
1
N1
N2
N3
N1
N2
N3
..........
N12 N13 N14
A1
A2
A3
A4
N11
N12
N13
N14
Single Mode
0
1
N4
N5
N6
N7
N8
N10
Note: N14 is the MSB of the N counter value. A7 is the MSB of the A counter value. A7 is the first bit which is transferred
to the HPLL-8001.
9
Status Registers
1
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B1 is the first bit which is transferred to the HPLL-8001.
B1:
B1
0
1
Counter loading
asynchronous counter load
synchronous counter load
B2 and B3:
B2
B3
PO1
PO2
Modes
0
0
FRN
FVN
Test Modes
0
1
1
0
φV
φVN
φRN
φRN
1
1
PROBIT
IREF
External Charge Pump, Mode 1
External Charge Pump, Mode 2
Internal Charge Pump mode
B4:
B2
PD Polarity
0
negative
1
positive
positive means increasing VCO
frequency with increasing voltage
B5 and B6:
B5
Standby 2
0
0
1
B6
Standby 1
0
1
0
1
1
Modes
Standby mode 1: All functions
powered down
Standby mode 2: Counters, charge pump,
and outputs are off. Only preamplifiers
stay active
Normal operation: All functions are active
B7 and B8:
Anti Backlash Pulse Width
B8
B7
Typical
0
0
10
0
1
6
1
0
4
1
1
2
Unit
ns
ns
ns
ns
B5
B4
B3
B2
B1
10
B9 and B10:
B9
Single/Dual
Mode
0
0
1
1
B10
Preamplifier
Select
0
1
0
1
Modes
VCOI input: single HF mode
VCOI input: single LF mode
VCOI input: dual mode, VCOI trigger LH edge
VCOI input: dual mode, VCOI trigger HL edge
B11:
B11
0
1
Output bit PROBIT on PO1
0
1
B12, B13, and B14:
VDD = 4.5 – 5.5 V
VDD = 2.7 – 3.3 V
B14
B13
B12
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Standby
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Standby
0
1
0
1
0
1
0
1
Charge pump current
Typ.
Units
0.15
mA
0.21
mA
0.31
mA
0.44
mA
0.63
mA
0.89
mA
1.26
mA
1.69
mA
0.1
nA
0.14
0.20
0.29
0.40
0.58
0.79
1.06
1.26
0.1
Reduced Status Register
0
0
B14
B13
B12
B11
B11 is the first bit which is transferred to the HPLL-8001.
mA
mA
mA
mA
mA
mA
mA
mA
nA
11
Functional Description
Frequency Divider
The division ratio can be
calculated as follows:
FVCO = ( N x P + A) / R x
FREF where,
FVCO: Output frequency of the
external VCO
FREF: Reference oscillator
frequency
N: divide ratio of the N counter
3 ≤ N ≤ 16380
A: divide ratio of the A counter
0 ≤ A ≤ 127
R: divide ratio of the R counter
3 ≤ R ≤ 65535
P: divide ratio of the external dual
modulus prescaler
Phase Detector and
Charge Pump
The phase detector is a digital,
edge-sensitive comparator with
UP and DOWN outputs. Both
outputs can be monitored at the
outputs PO1 and PO2. The phase
detector drives a charge pump,
which is a switch with a tristate
state. The output current can be
programmed in 8 steps between
0.15 mA and 1.69 mA (VDD = 4.5
to 5.5 V) with a reference current
of 100 µA.
If VCOI < REFI, the charge pump
delivers a positive current to the
external loop filter. If VCOI >
REFI, the charge pump sinks a
negative current from the external
loop filter. The charge pump
output can be inverted by
software.
Anti-backlash pulses are generated to extend the very short
phase difference between VCOI
and REFI.
Programming
The HPLL-8001 can be
programmed through a 3-wire
interface. Four different words
can be sent over this interface to
program the internal registers. All
four words consists of a 2-bit
address and a variable data
portion. When EN= L, the data is
transferred. It is loaded into the
internal registers at the rising
edge of EN. The last two bits
which are transferred, form the
address bits. When EN = H, the
input signals, CLK and DATA, are
internally disabled.
2) programming of the R counter
The Status registers contains all
status information.
In standby mode 2, the serial
interface and the input amplifiers
are active. All other parts are
powered down.
The reduced Status register is a
reduced version of the status
register.
The N and A counter register and
the R counter register contain the
applicable counter values.
The programming of the device
must start with the loading of the
status register.
The N, A and R counters can be
loaded synchronously or asynchronously. If synchronous
loading is selected, all counters
are loaded when they reach the
value zero. As a result, the phase
difference between the divided
VCOI and REFI signal remains the
same.
For synchronous loading the
following order of programming
must be followed:
1) programming of synchronous
loading using the status
register
3) programming of the N, A
counters
The rising edge of EN enables the
synchronous loading of all
counters at their zero value.
Standby
The HPLL-8001 has two standby
modes.
In standby mode 1, the whole
device is powered down with the
exception of the serial interface.
Part Number Ordering Information
Part Number
No. of Devices
Container
HPLL-8001-BLK
56
Tube
HPLL-8001-TR1
1000
7" Reel
Package Dimensions
Device Orientation
JEDEC Standard SOP-14
REEL
14
HPLL
8001
YYWW
1
2
SYMBOL
A
A1
b
D
E
e
H
L
θ
E
H
DIMENSIONS
MIN.
MAX.
1.35 (0.053)
2.01 (0.079)
0.080 (0.003)
0.300 (0.012)
0.330 (0.013)
0.510 (0.020)
8.56 (0.337)
8.89 (0.350)
3.81 (0.150)
4.09 (0.161)
1.27 BSC (0.500)
5.79 (0.151)
6.40 (0.252)
0.300 (0.012)
1.27 (0.050)
0
10
CARRIER
TAPE
USER
FEED
DIRECTION
COVER TAPE
Meets JEDEC outline dimensions.
Dimensions are in millimeters (inches).
Tolerances: .XX = ±.01, .XXX = ±.002
3
D
θ
A
e
b
L
A1
Tape Dimensions and Product Orientation
4.0 ± 0.1
2.0 ± 0.1
0.30 ± 0.05
0.30 R MAX.
1
7
1.75 ± 0.1
7.5 ± 0.1
14
16.0 ± 0.3
HPLL
8001
YYWW
9.5 ± 0.1
2.1 ± 0.1
1.5 +0.1/-0.0 DIA.
8
8.0 ± 0.1
1.5 MIN
6.5 ± 0.1
0.5 RADIUS TYP
DIMENSIONS ARE SHOWN IN MILLIMETERS
www.hp.com/go/rf
For technical assistance or the location of
your nearest Hewlett-Packard sales office,
distributor or representative call:
Americas/Canada: 1-800-235-0312 or
408-654-8675
Far East/Australasia: Call your local HP
sales office.
Japan: (81 3) 3335-8152
Europe: Call your local HP sales office.
Data subject to change.
Copyright © 1998 Hewlett-Packard Co.
Printed in U.S.A.
5966-1495E (1/98)