INFINEON PMB2304

Wireless Components
PLL-Frequency Synthesizer
PMB 2304R Version 2.1
Specification June 2002
preliminary
Revision History: Current Version: 06.02
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Edition 03.02
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PMB 2304R
preliminary
Productinfo
Productinfo
General Description
Features
The PMB 2304R PLL is a high speed Package:
CMOS IC, especially designed for use
in battery powered radio equipment
and mobile telephones and serves as a
functional replacement of the PMB
2307R. The primary applications are in
digital cellular and cordless systems
e.g. GSM 900/1800/1900 and DECT
systems. The wide range of dividing
ratios also allows application in analog
systems.
Low operating current consumption Large dividing ratios for small
(typically 3.5 mA)
channel spacing
A counter 0 to 127
N counter 3 to 16.383
R counter 3 to 65.535
High input sensitivity, high input
frequencies (220 MHz)
Extremely fast phase detector
without dead zone
Serial control (3-wire bus: data,
clock, enable) for fast programming
(fmax ~ 10 MHz)
Linearization of the phase detector
output by current sources
Synchronous programming of the
counters (N-, N/A-, R-counters)
and system parameters
Switchable polarity and phase
detector current programmable
2 Multifunction outputs
frn, fvn outputs of the R- and
N/A- counters for test
Fast modulus switchover for
65-MHz operation
Switchable modulus trigger edge
Serial control (3-wire bus: data,
clock, enable) for fast programming
(fmax ~ 10 MHz)
Output port
(e.g. for standby of the prescaler)
External current setting for PD
output
Lock detect output with quasidigital
lock detect
Application
GSM 900 / 1800 / 1900
DECT
Analog systems
Ordering Information
Wireless Components
Type
Ordering Code
Package
PMB 2304R
Q67106-H9100
P-TSSOP-16
Product Info
Specification, June 2002
1
Table of Contents
1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2
2.1
2.2
2.3
2.4
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3
3.1
3.2
3.3
3.4
3.5
3.6
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Data acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
4
4.1
4.2
4.3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Application Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
5.3
5.4
5.5
5.6
5.7
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Absolute Maximum Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Operating Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Typical Supply Current IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Phase detector outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Serial Control Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Programming Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Pulse Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Serial Control Data Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Diagram Input Sensitivity FI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
2
Product Description
Contents of this Chapter
2.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
PMB 2304R
preliminary
Product Description
2.1 Overview
The PMB 2304R PLL is a high speed CMOS IC, especially designed for use in
battery powered radio equipment and mobile telephones and serves as a functional replacement of the PMB 2307R. The primary applications are in digital
cellular and cordless systems e.g. GSM 900/1800/1900 and DECT systems.
The wide range of dividing ratios also allows application in analog systems.
2.2 Features
Low operating current consumption (typically 3.5 mA)
High input sensitivity, high input frequencies (220 MHz)
Extremely fast phase detector without dead zone
Linearization of the phase detector output by current sources
Synchronous programming of the counters (N-, N/A-, R-counters) and
system parameters
Fast modulus switchover for 65-MHz operation
Switchable modulus trigger edge
Serial control (3-wire bus: data, clock, enable) for fast programming
(fmax ~ 10 MHz)
Large dividing ratios for small channel spacing
A counter 0 to 127
N counter 3 to 16.383
R counter 3 to 65.535
Serial control (3-wire bus: data, clock, enable) for fast programming
(fmax ~ 10 MHz)
Wireless Components
Switchable polarity and phase detector current programmable
2 Multifunction outputs frn, fvn outputs of the R- and N/A- counters for test
Output port (e.g. for standby of the prescaler)
External current setting for PD output
Lock detect output with quasidigital lock detect
2-2
Specification, June 2002
PMB 2304R
preliminary
Product Description
2.3 Application
GSM 900 / 1800 / 1900
DECT
Analog systems
2.4 Package Outlines
P-TSSOP-16
Wireless Components
2-3
Specification, June 2002
3
Functional Description
Contents of this Chapter
3.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.3
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.5
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.6
Data acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
PMB 2304R
preliminary
Functional Description
3.1 Pin Configuration
RI
1
16
LD
VSS
2
15
M FO2
EN
3
14
M FO1
13
VDD1
12
PD
DA
4
CLK
5
PM B 2304R
VDD
6
11
VSS1
MOD
7
10
FI
NC
8
9
NC
Pin_config.wmf
Figure 3-1
Pin Configuration
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function
Pin
No.
Symbol
1
RI
Equivalent I/O-Schematic
Function
STD BY
5 00K Ω
P in1
Reference Frequency
Input with highly sensitive
preamplifier for 16-bit R-counter. With
small input signals AC
coupling must be set up, where DC coupling can be used for large input signals.
5 60 Ω
RI
2 pF
ESD
STDBY
2
Ground for serial control logic.
VSS
Wireless Components
3-2
Specification, June 2002
PMB 2304R
preliminary
Functional Description
EN
P in 3
*2pF
EN
560Ω
75kΩ
3
3-Line Bus: Enable
Enable line of the serial control with internal pull-up resistor. When EN = H the
input signals CLK and DA are disabled
internally. When EN = L the serial control
is activated. The received data are transferred into the latches with the positive
edge of the EN-signal.
ESD
DA
P in 4
*2pF
DA
560Ω
75kΩ
4
3-Line Bus: Data
Serial data input with internal pull-up
resistor. The last two bits before the ENsignal define the destination address. In a
byte-oriented data structure the transmitted data have to end with the EN-signal,
i.e. bits to be filled in (don’t care) are
transmitted first.
ESD
CLK
P in 5
3-Line Bus: Clock
Clock line with internal pull-up resistor.
The serial data are read into the internal
shift register with the positive edge (see
pulse diagram for serial data control).
*2pF
CLK
560Ω
75kΩ
5
ESD
6
VDD
Positive supply voltage for serial control
logic.
7
MOD
Modulus Control Output for external
dual modulus prescaler. The modulus
output is low at the beginning of the cycle.
When the A-counter has reached its set
value, MOD switches to high. When the
N-counter has reached its set value,
MOD switches to low again, and the cycle
starts from the top. When the prescaler
has the counter factor P or P + 1 (P for
MOD = H, P + 1 for MOD = L), the overall
divider factor is NP + A. The value of the
A-counter must be smaller than that of
the N-counter. The trigger edge of the
modulus signal to the input signal can be
selected (see programming tables and
MODA, B) according to the needs of the
prescaler. In single modulus operation
and for standby operation in dual modulus operation, the output is low.
p in 7
2pF
MOD
ES D
Wireless Components
3-3
Specification, June 2002
PMB 2304R
preliminary
Functional Description
8
NC
not connected
9
NC
not connected
10
FI
STD BY
5 00K Ω
P in10
VCO-Frequency
Input with highly sensitive preamplifier for
14-bit N-counter and 7-bit A-counter. With
small input signals AC coupling must be
set up, where DC coupling can be used
for large input signals.
5 60 Ω
FI
2 pF
ESD
STDBY
11
Ground for the preamplifiers, counters,
phase detector and charge pump.
VSS1
(Note: The pins VDD and VDD1 respectively VSS and VSS1 have to have the
same supply voltage.)
12
PD
p in 1 2
*2 p F
PD
ES D
* O n ly th is p in h a s lim ite d b u ild -in E S D
p ro te ctio n
13
Positive supply voltage for the preamplifiers, counters, phase detector and charge
pump.
VDD1
Wireless Components
Phase Detector
Tristate charge pump output. The integrated, positive and negative current
sources can be programmed with respect
to their current density by means of the
serial control. Activation and deactivation
depend on the phase relationship of the
scaled-down input signals FI:N, RI:R.
(See phase detector output waveforms.)
frequencyfV < fR or fV lagging:p-channel
current source active
frequencyfV > fR or fR leading:n-channel
current source active
frequencyfV = fR and PLL locked:current
sources are switched off,
PD-output is tristate
In standby mode the PD-output is set to
tristate. The assignment of the current
sources to the output signals of the phase
detector can be swapped in it’s polarity,
i.e. the sign of the phase detector constant can be controlled.
3-4
Specification, June 2002
PMB 2304R
preliminary
Functional Description
14
MFO1
Multifunction Output for the signals fRN ,
ΦV,, ΦVN , and port1.
–The signal fRN is the divided signal of the
reference frequency.
The L-time corresponds to 1/fRI respectively
–In the port function the port 1 output signal is assigned to the information of the
programmed status. The output switches
with the rising edge of the EN-signal
The standby mode does not affect the
port function.
p in 1 4
2pF
M FO1
ES D
15
MFO2
5 60 Ω
IR E F
M F 02
V REF
Inte rn al C h arge
P um p M od e
& sta ndb y
16
2pF
V REF
ESD
LD
p in 1 6
2pF
LD
P in15
Multifunction I/O-Pin for the external reference current setting IREF and the signals
ΦRN and fVN ( in testmode).
–The signal fVN is the divided signal of FIinput. The L-time corresponds to 1/fFI
respectively.
Output levels are not specified, the signal
should only be used for test purpose.
–In the internal charge pump mode the
reference current IREF at MFO2 determines the value of the PD-output current.
Lock Detector Output (open drain). Unipolar output of the phase detector in the
form of a pulse-width modulated signal.
The LD-pulse width corresponds to the
phase difference. In the locked state the
LD-signal is at H-level. For standby mode
see Standby Table.
Only for ABL status 11 no gating of ABL
impulse is performed.
ES D
Wireless Components
3-5
Specification, June 2002
PMB 2304R
preliminary
Functional Description
3.3 Functional Block Diagram
RI
1 6-B it R -C o u n te r
ƒR
P h a se D e te cto r
R
L o ckD e te cto r
LD
D a ta R e g iste r
and
S ha d o w R e g iste r
PD
ƒV
S h ift R e g iste r
C h a rg e
Pum p
V
M FO1
IR E F
M FO2
M o d u lu s C o n tro l
FI
MOD
1 4 -B it
N -C o u n te r
7 -B it
A -C o u n te r
D a ta R e g iste r
D a ta R e g iste r
S ha d o w R e g iste r
S h a d o w R e g iste r
S h ift R e g iste r
S h ift R e g iste r
CLK
DA
EN
S e ria l C o n tro l L o g ic
V DD1
V SS1
V DD
V SS
Funct_block.wmf
Figure 3-2
Wireless Components
Functional Block Diagram
3-6
Specification, June 2002
PMB 2304R
preliminary
Functional Description
3.4 General Description
The circuit consists of a reference-, A- and N-counter, a dual modulus control
logic, a phase detector with charge pump output and a serial control logic. The
setting of the operating mode and the selection of the counter ratios is done
serially at the ports CLK, DA and EN.
The operating modes allow the selection of single or dual operation, asynchronous or synchronous data acquisition, 4 different antibacklash-impulse times, 8
different PD-output current modes, polarity setting of the PD-output signal,
adjustment of the trigger-edge of the MOD-output signal, 2 standby modes and
the control of the multifunction outputs MFO1 and MFO2.
The reference frequency is applied at the RI-input and divided by the R-counter.
It’s maximum value is 100 MHz. The VCO-frequency is applied at the FI-input
and divided by the N- or N/A-counter according to single or dual mode operation. The maximum value at FI is 220 MHz at single-, and 65 MHz at dual mode
operation.
The phase and frequency sensitive phase detector produces an output signal
with adjustable anti-backlash impulses in order to prevent a dead zone for very
small phase deviations. Phase differences of less than 100 ps can be resolved.
In general the shortest anti-backlash pulse gives the best system performance.
3.5 Programming
Programming of the IC is done by a serial data control. The contents of the message are assigned to the functional units according to the address. Single or
dual mode operation as well as asynchronous or synchronous data acquisition
is set by status 2 and should therefore precede the programming of the
counters.
3.6 Data acquisition
The PMB 2304R offers the possibility of synchronous data acquisition to avoid
error signals at the phase detector due to non-corresponding dividing factors in
the counters produced by asynchronous loading.
Synchronous programming guarantees control during changes of frequency or
channel. That means that the state of the phase detector or the phase
difference is kept maintained, and in case of “lock in”, the control process starts
with the phase difference “zero”.
Wireless Components
3-7
Specification, June 2002
PMB 2304R
preliminary
Functional Description
This is done as follows:
1. Setting of synchronous data acquisition by status 2.
2. Programming of the R-counter, status 1 (optional)-data is being loaded into
shadow registers.
3. Programming of the N- or N/A-counter-data is being loaded into shadow registers, the EN-signal starts the synchronous loading procedure.
4. Synchronous programming – which means data transfer of all data from the
shadow registers to the data registers – takes place at that point in time
when the respective counter reaches “zero + 1”, the maximum repetition rate
for channel change is therefore fFI:N.
5. Transfer of status 1 information into the corresponding data register is tied
to the N-counter loading, but follows the loading of the N-data register in the
distance of one N-counter dividing ratio, this guarantees that for example a
new PD-current value becomes valid at the same time when the counters
are loaded with the new data.
Synchronous avoids additional phase error caused by programming. Synchronous data acquisition is of especial advantage, when large steps in frequency
are to be made in a short time. For this purpose a high reference frequency can
be programmed in order to achieve rapid – “rough” – transient response. This
method increases the fundamental frequency nearly by the square route of the
reference frequency relation. When rough lock is achieved, another synchronous data transfer is needed to switch back to the original channel spacing. A
“fine” lock in will finish the total step response. It may not be necessary to
change reference frequency, but it make sense to perform synchronous data
acquisition in any case. Especially for GSM, PCN, PCS, DECT, DAMPS, PHP
systems the synchronous mode should be used to get best performance of the
PMB 2304R.
Standby Condition:
The PMB 2304R has two standby modes (standby 1, 2) to reduce the current
consumption.
Standby 1 switches off the whole circuit, the current consumption is reduced
below 1 µA.
Standby 2 switches off the counters, the charge pump and the outputs, only the
preamplifiers stay active.
For the influence on the output signals see standby table (5-10).
fRN, fVN, ΦRN, ΦVN are the inverted signals of fR, fV,ΦR, ΦV.
Wireless Components
3-8
Specification, June 2002
4
Applications
Contents of this Chapter
4.1
PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2
Application Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
PMB 2304R
preliminary
Applications
4.1 PCB Layout
oben.wmf
Figure 4-1
Top Side
unten.wmf
Figure 4-2
Wireless Components
Bottom Side
4-2
Specification, July 1999
PMB 2304R
preliminary
Applications
4.2 Application Board
stromlauf.wmf
Figure 4-3
Wireless Components
Application board
4-3
Specification, July 1999
PMB 2304R
preliminary
Applications
4.3 Bill of material
Table 4-1
Wireless Components
Nr
Reference
Symbol name
Technology
1
C1
CAP
10p
2
C2
CAPELK
4µ7
3
C3
CAP
10p
4
C4
CAP
10p
5
C5
CAP
10p
6
C6
CAP
220pF
7
C7
CAP
330pF
8
C8
CAP
30pF
9
C9
CAP
100p
10
C10
CAP
100n
11
C11
CAP
100p
12
C12
CAP
100n
13
C13
CAPELK
4µ7
14
C14
CAP
5.6nF
15
C15
CAP
150p
16
C16
CAP
10nF
17
C17
CAP
1nF
18
C18
CAPELK
4µ7
19
IC1
PMB2314T
PMB2314T
20
IC2
PMB2305
PMB2304R
21
J1
CON-5
5 Pin
22
J2
JUMP-2SMD0603
JUMPER_2SMD06031
23
J3
JUMP-2SMD0603
JUMPER_2SMD06031
24
N2
VCO2
1500MHz
25
R1
RES
10k
26
R2
RES
10k
27
R3
RES
10k
28
R4
RES
4k7
29
R5
RES
4k7
30
R6
RES
4k7
31
R7
RES
27k
32
R8
RES
124k
4-4
Specification, July 1999
PMB 2304R
preliminary
Applications
33
R9
RES
8.2k
34
R10
RES
18
35
R11
RES
56
36
R12
RES
18
37
R13
RES
18
38
R14
RES
47
39
R15
RES
10
40
R16
RES
10
41
R17
RES
22k
SMA
SMA_stehend
42
Wireless Components
43
-
SMA
SMA_stehend
44
X1
SMA
SMA_stehend
45
X2
SMA
SMA_stehend
4-5
Specification, July 1999
5
Reference
Contents of this Chapter
5.1
Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2
Phase detector outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.3
Serial Control Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.4
Programming Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.5
Pulse Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.6
Serial Control Data Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.7
Diagram Input Sensitivity FI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
PMB 2304R
preliminary
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Range
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Range
Parameter
Symbol
Limit Values
Unit
min
max
Supply Voltage
VDD
-0.3
6
V
Input Voltage
V1
-0.3
VDD + 0.3
V
Output Voltage
VQ
GND
VDD
V
Power dissipation per output
PQ
10
mW
Total power dissipation
Ptot
300
mW
Ambient temperature
TA
-40
85
°C
Storage temperature
Tstg
-50
125
°C
Thermal Resistance
RthJA
180
K/W
ESD Integrity except @Pin 12
(PD) (according to MIL833
Method 3015.7)
VESD
1
KV
ESD Integrity except @Pin 12
(PD) (according to MIL833
Method 3015.7)
VESD
400
Wireless Components
5-2
Remarks
in operation
V
Specification, June 2002
PMB 2304R
preliminary
Reference
5.1.2
Operating Ratings
Within the operating ratings the IC operates as described in the circuit description. The AC/DC characteristic limits are not guaranteed.
Table 5-2 Operating Ratings, Supply Voltage VVCC= 2.7 V .. 4.5 V, Ambient temp. TAMB= -30°C ... + 85°C
Symbol
Parameter
Limit Values
Unit
min
max
Test Conditions
Supply Voltage
VDD
2.7
5.5
V
Input frequency dual
ƒFI
0.1
65
MHz
VDD = 4.5...5.5V
Input frequency single HF-mode
ƒFI
0.1
220
MHz
VDD = 4.5...5.5V
Input frequency single LF-mode
ƒFI
0.1
90
MHz
VDD = 4.5...5.5V
Input reference frequency
ƒRI
100
MHz
VDD = 4.5...5.5V
Input frequency dual mode
ƒFI
0.1
30
MHz
VDD = 2.7V
Input frequency single HF-mode
ƒFI
0.1
90
MHz
VDD = 2.7V
Input frequency single LF-mode
ƒFI
0.1
35
MHz
VDD = 2.7V
Input reference frequency
ƒRI
20
MHz
VDD = 2.7V
PD-output current
/ IPD
4
mA
PD-output voltage
VPD
0.5
VDD - 0.5
V
VDD = 4.5- 5.5V
PD-output voltage
VPD
0.5
VDD - 0.5
c
VDD = 2.7V
Ambient temperature
TA
-40
85
5.1.3
L
Item
°C
Typical Supply Current IDD
All pins are protected against ESD. Unused inputs without pullup resistors must be connected to either VDD or VSS.
Table 5-3 Typical Supply Current IDD
Parameter
Symbol
Limit Values
min
Supply voltage
VDD
2.7
Unit
Test Conditions
L
Item
max
5
5.5
V
Supply current:
ƒFI = 50MHz
single mode HF
IDD
1.63
2.6
2.94
mA
VFI = 150mVrms
dual mode
IDD
1.76
2.80
3.17
mA
ƒRI = 10MHz
standby 2
IDD
0.11
0.62
0.75
mA
VRI = 150mVrms
standby 1
IDD
1
µA
IPD = 0.25mA
Iref = 100 µA
Wireless Components
5-3
Specification, June 2002
PMB 2304R
preliminary
Reference
5.1.4
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the
production.
Table 5-4 AC/DC Characteristics with Ambient temp. Tamb= -20 .. 85 °C, Supply Voltage VVCC = 2.7 .. 4.5V
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
Input Signals DA, CLK, EN (with internal pull-up resistors)
H-input voltage
VIH
L-input voltage
0.7- VDD
VDD
V
1.1
VIL
0.3- VDD
V
1.2
Input capacity
CI
5
pF
H-input current
IH
10
µA
VI = VDD = 5.5V
1.3
L-input current
IL
-60
µA
VI = GND
1.4
Input voltage
VI
100
mVrms
ƒ = 4...100MHz, VDD = 4.5V
2.1
Input voltage
VI
100
mVrms
ƒ = 4...30MHz, VDD = 2.7V
2.2
V/µs
VDD = 2.7...5.5V
2.3
Input Signal RI
Slew rate
4
Input capacity
CI
3
pF
H-input current
IH
30
µA
VI = VDD = 5.5V
2.4
L-input current
IL
-30
µA
VI = GND
2.5
Input voltage
VI
180
mVrms
ƒ = 4...65MHz, VDD = 4.5V
3.1
Input voltage
VI
50
mVrms
ƒ = 10...25MHz, VDD = 2.7V
3.2
V/µs
VDD = 2.7...5.5V
3.3
Input Signal FI (dual mode)
Slew rate
4
Input capacity
CI
3
pF
H-input current
IH
30
µA
VI = VDD = 5.5V
3.4
L-input current
IL
-30
µA
VI = GND
3.5
Input Signal FI (single HF-mode)
Input voltage
VI
200
mVrms
ƒ = 4...200MHz, VDD = 4.5V
4.1
Input voltage
VI
200
mVrms
ƒ = 4...90MHz, VDD = 2.7V
4.2
Input voltage
VI
50
mVrms
ƒ = 10...40MHz, VDD = 4.5V
4.3
4
V/µs
VDD = 2.7...5.5V
4.4
Slew rate
Input capacity
CI
3
pF
H-input current
IH
30
µA
VI = VDD = 5.5V
4.5
L-input current
IL
µA
VI = GND
4.6
Wireless Components
-30
5-4
Specification, June 2002
PMB 2304R
preliminary
Reference
Table 5-4 AC/DC Characteristics with Ambient temp. Tamb= -20 .. 85 °C, Supply Voltage VVCC = 2.7 .. 4.5V
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
Input Signal FI (single LF-mode)
Input voltage
VI
100
mVrms
ƒ = 4...90MHz, VDD = 4.5V
5.1
Input voltage
VI
100
mVrms
ƒ = 4...35MHz, VDD = 2.7V
5.2
4
V/µs
VDD = 2.7...5.5V
5.3
Slew rate
Input capacity
CI
3
pF
H-input current
IH
30
µA
VI = VDD = 5.5V
5.4
L-input current
IL
µA
VI = GND
5.5
-30
Output Current /IPD/
Current mode:
6.1
"0.175 mA"
IPROG
-20%
0.175
+20%
mA
"0.25 mA"
IPROG
-20%
0.25
+20%
mA
"0.35 mA"
IPROG
-20%
0.35
+20%
mA
"0.5 mA"
IPROG
-20%
0.5
+20%
mA
6.5
"0.7 mA"
IPROG
-20%
0.7
+20%
mA
6.6
"1.0 mA"
IPROG
-15%
1.0
+15%
mA
6.7
"1.4 mA"
IPROG
-15%
1.0
+15%
mA
"2.0 mA"
IPROG
-10%
Standby"
/IPD/
6.2
6.3
VDD = 4.5...5.5V
VPD = VDD/2
IREF = 100µΑ
6.4
6.8
VDD = 4.5V
2.0
+10%
mA
0.1
1
nA
-5%
+0%
6.9
6.10
Output Tolerance IPD
∆IPD / IPROG
-10%
∆IPD / IPROG
VPD = VDD/2, VDD = 2.7V
7.1
VPD = 0.5...2.2V, VDD = 2.7V
7.2
V
VDD = 2.7...5.5V
IREF = 100µA
8.1
V
VDD = 4.5...5.5V,IQH= -2mA
9.1
V
VDD = 4.5...5.5V,IQL= 2mA
9.2
V
VDD = 2.7V,IQH=-1.2mA
9.3
1
V
VDD = 2.7V,IQL=1.2mA
9.4
±2.5%
Input Voltage MFO2 (Internal charge pump mode)
Reference voltage
VREF
0.9
1.1
1.3
Output Signal MFO1 (push pull)
H-output voltage
VQH
L-output voltage
VQL
H-output voltage
VQH
L-output voltage
VQL
Rise time
tR
2.5
10
ns
VDD = 4.5...5.5V,CI= 10pF
9.5
Fall time
tF
2.0
10
ns
VDD = 4.5...5.5V,CI= 10p
9.6
Rise time
tR
5
12
ns
VDD = 2.7V,CI=10pF
9.7
Fall time
tF
4
12
ns
VDD = 2.7V,CI=10pF
9.8
Wireless Components
VDD - 1
1
VDD - 1
5-5
Specification, June 2002
PMB 2304R
preliminary
Reference
Table 5-4 AC/DC Characteristics with Ambient temp. Tamb= -20 .. 85 °C, Supply Voltage VVCC = 2.7 .. 4.5V
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
Output Signal MFO2 (push pull)
H-output voltage
VQH
L-output voltage
VQL
H-output voltage
VQH
L-output voltage
VQL
Rise time
tR
Fall time
VDD - 1
V
VDD = 4.5...5.5V,IQH= 2mA
10.1
V
VDD = 4.5...5.5V,IQL= 2mA
10.2
V
VDD = 2.7V,IQH= 1.2mA
10.3
1
V
VDD = 2.7V,IQL= 1.2mA
10.4
2
10
ns
VDD = 4.5...5.5V,CI= 10pF
10.5
tF
2
10
ns
VDD = 4.5...5.5V,CI= 10p
10.6
Rise time
tR
3
10
ns
VDD = 2.7V,CI=10pF
10.7
Fall time
tF
3
10
ns
VDD = 2.7V,CI=10pF
10.8
1
VDD - 1
Output Signal LD (n-channel open drain)
L-output voltage
VQL
0.4
V
VDD = 2.7...5.5V,
IQL = 0.3mA
11.1
H-output current
IQH
5
µA
VDD = 2.7...5.5V
11.2
Fall time
tF
3
10
ns
VDD = 4.5...5.5V,CI=10pF
11.3
Fall time
tF
5
12
ns
VDD = 2.7V,CI=10pF
11.4
V
VDD = 4.5...5.5V,
IQH = -0.5mA
12.1
V
VDD = 4.5...5.5V
IQL = 0.5mA
12.2
V
VDD = 2.7V, IQH = - 0.3mA
12.3
0.4
V
VDD = 2.7V, IQL= 0.3mA
12.4
Output Signal MOD (push pull)
H-output voltage
VQH
L-output voltage
VQL
H-output voltage
VQH
L-output voltage
VQL
Rise time
tR
1.5
3
ns
VDD = 4.5...5.5V, CI = 5pF
12.5
Fall time
tF
1.3
3
ns
VDD = 4.5...5.5V, CI = 5pF
12.6
Propagation delay
time H-L to FI
tDQHL
8
12
ns
VDD = 4.5...5.5V, CI = 5pF
12.7
Propagation delay
time L-H to FI
tDQHL
8
12
ns
VDD = 4.5...5.5V, CI = 5pF
12.8
Rise time
tR
3.2
5
ns
Fall time
tF
2
5
ns
Propagation delay
time H-L to FI
tDQHL
15
ns
Propagation delay
time L-H to FI
tDQHL
15
ns
VDD-0.4
0.4
VDD-0.4
VDD = 2.7V, CI = 5pF
VDD = 2.7V, CI = 5pF
VDD = 2.7V, CI = 5pF
VDD = 2.7V, CI = 5pF
12.9
12.10
12.11
12.12
This value is only guaranteed in lab.
Wireless Components
5-6
Specification, June 2002
PMB 2304R
preliminary
Reference
5.2 Phase detector outputs
RI
fR
(RI:R)
FI
MOD A
MOD B
fV
(FI:N)
P-Channel
PD
Tri-State.
Polarity
pos. N-Channel
P-Channel
PD
Polarity Tri-State.
neg.
N-Channel
LD
ΦR
Polarity pos.
(internal Signal)
ΦV
Polarity pos.
(internal Signal)
Frequency fV < fR
or fV lagging
Figure 5-1
Wireless Components
Frequency fV > fR
or fV leading
Frequency fV = fR
Phase detector output signals
5-7
Specification, June 2002
PMB 2304R
preliminary
Reference
5.3 Serial Control Data Format
Table 5-5 Serial Control Data Format (status 1,2)
Status 1
Status 2
1
asynchronous
synchronous
Data acquisition mode
1
Mode 1
2
see table
Mode 2
3
see table
PD-polarity
4
negative
positive
Standby 1
5
standby
active
Standby 2
6
standby
active
Anti-backlash pulse width 1
7
see table
Anti-backlash pulse width 2
8
see table
Preamplifier select
9
see table
Single / dual mode
10
single
dual
1
Port 1
11
low
high
2
PD-current 1
12
see table
3
PD-current 2
13
see table
4
PD-current 3
14
see table
5
6
0
Address
0
0
1
15
16
EN
EN
Wireless Components
0
5-8
Specification, June 2002
PMB 2304R
preliminary
Reference
Table 5-6 Serial Control Data Format
(N-, N/A-counter)
Table 5-7 Serial Control Data Format
(R-counter)
Dual
Mode
1
Single
Mode
MSB
1
2
2
3
3
4
4
ACounter
5
MSB
5
6
6
7
LSB
8
MSB
7
1
8
9
2
9
10
3
10
11
4
11
12
5
12
13
6
13
7
14
8
15
16
9
16
LSB
17
10
17
1
18
11
18
1
19
12
EN
20
13
14
NCounter
15
21
LSB
22
1
0
23
MSB
EN
Wireless Components
Address
LSB
14
1
0
15
RCounter
Address
16
EN
5-9
Specification, June 2002
PMB 2304R
preliminary
Reference
5.4 Programming Tables
Table 5-8
Status Bits
AntiBacklash
Pulse Width 2
AntiBacklash
Pulse Width 1
tW (typ.)
[ns]
0
0
1.3
0
1
5
1
0
10
not recommended
1
1
13*
any application where
continuous lock detect is required
VDD = 5V
* No ABL gating performed
* In general the shortest anti-backlash pulse gives the best system performance
.
Table 5-9
Status Bits
Single/Dual Mode
Preamplifier Function Mode
Preamplifier Select
0
0
FI-input frequency,single HF-mode
0
1
FI-input frequency,single LF-mode
1
0
FI-input frequency, dual-mode, FItrigger edge LH, MOD A
1
1
FI-input frequency, dual-mode, FItrigger edge HL, MOD B
Table 5-10 Standby Table
Output Pins
Status
Wireless Components
MFO1
MFO2
LD
PD
MOD
ΦV
ΦVN
Standby 1
low
high
high
resistive
tristate
low
Standby 2
low
high
high
resistive
tristate
low
5 - 10
Specification, June 2002
PMB 2304R
preliminary
Reference
Table 5-11
Status Bits
PD-Current Mode
PD-Current 3
PD-Current 2
PD-Current 1
Ipd/mA
0
0
0
0.175
0
0
1
0.25
0
1
0
0.35
0
1
1
0.5
1
0
0
0.7
1
0
1
1
1
1
0
1.4
1
1
1
2
Table 5-12
Status Bits
Multifunction Output
Mode 2
Mode 1
MFO 1
MFO 2
Remarks
0
0
fRN
fVN
test mode
0
1
ΦV
ΦRN
external charge pump mode 1
1
0
ΦVN
ΦRN
external charge pump mode 2
1
1
Port 1
Iref
internal charge pump mode
5.5 Pulse Diagram
50%
50%
≈
FI
tDQLH
tDQLH
tDQLH
≈
tDQLH
MOD A
MOD B
Figure 5-2
Wireless Components
VQH
VQL
50%
50%
tR
tF
VQH
VQL
50%
50%
tR
tF
Pulse diagram
5 - 11
Specification, June 2002
PMB 2304R
preliminary
Reference
5.6 Serial Control Data Input Timing
tF
tR
≈
tWHCL
VIH
CLK
VIL
≈
tDS
VIH
VIL
≈
DA
tCLE
tECL
VIH
VIL
≈
EN
≈ ≈
tWHEN
VIH
MFO1
MFO3 VIL
tDEP
Figure 5-3
Serial Control Data Input Timing
Table 5-13
Symbol
Parameter
Limit Values
min
Wireless Components
Unit
max
Clock frequency
ƒCL
H-pulsewidth (CL)
tWHCL
40
ns
Data setup
tDS
20
ns
Setup time-clock enable
tCLE
20
ns
Setup time enable-clock
tECL
20
ns
H-pulsewidth (enable)
tWHEN
40
ns
Rise, fall time
tR, tF
10
µs
Propagation delay time EN-PORT
tDEP
1
µs
5 - 12
12
MHz
Specification, June 2002
PMB 2304R
preliminary
Reference
5.7 Diagram Input Sensitivity FI
Figure 5-4
Wireless Components
Input sensitivity FI (single HF-mode)
5 - 13
Specification, June 2002