ICs for Communications PLL-Frequency Synthesizer PMB2306R/PMB2306T Version 2.2 Data Sheet 02.97 T2306-0V22-D1-7600 30%530%7 5HYLVLRQ+LVWRU\ &XUUHQW9HUVLRQ Previous Version: 01.94 Page Page (in previous (in new Version) Version) Subjects (major changes since last revision) 14-15 19-20 $&'&&KDUDFWHULVWLFV H-input current ,H: is changed from 10µA to 30µA and L-input current ,L: is changed from -10µA to -30µA 26 26 &ORFNIUHTXHQF\ ICL max. is changed from 10MHz to 12MHz; +SXOVHZLGWK&/ WWHCL min. is changed from 60ns to 40ns; +SXOVHZLGWKHQDEOH WWHENmin. is changed from 60ns to 40ns; 18 18 Input reference frequency ICRI is changed from 20MHz to 22MHz 19 19 ,QSXW6LJQDO5, Input voltage 9I: is changed from 20MHz to 22MHz (GLWLRQ This edition was realized using the software system FrameMaker. 3XEOLVKHGE\ 6LHPHQV$* +/,7 6LHPHQV$* $OO5LJKWV5HVHUYHG $WWHQWLRQSOHDVH As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. 3DFNLQJ Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. &RPSRQHQWVXVHGLQOLIHVXSSRUWGHYLFHVRUV\VWHPVPXVWEHH[SUHVVO\DXWKRUL]HGIRUVXFKSXUSRVH Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 30%530%7 7DEOHRI&RQWHQWV 3DJH 1.1 1.2 1.3 1.4 2YHUYLHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 &LUFXLW'HVFULSWLRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.1 3.2 3.3 (OHFWULFDO&KDUDFWHULVWLFV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Typical Supply Current ,DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.1 4.2 3DFNDJH2XWOLQHV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Plastic-Package, P-TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Plastic-Package, P-DSO-14-1(SMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Semiconductor Group 3 02.97 3//)UHTXHQF\6\QWKHVL]HU 30%530%7 9HUVLRQ 2YHUYLHZ )HDWXUHV %LSRODU,& 30%7 • Low operating current consumption (typically 3.5 mA) • High input sensitivity, high input frequencies (220 MHz) • Extremely fast phase detector without dead zone 3'62 • Linearization of the phase detector output by current sources 30%5 • Synchronous programming of the counters (n-, n/a-, r-counters) and system parameters • Fast modulus switchover for 65-MHz operation • Switchable modulus trigger edge • Large dividing ratios for small channel spacing A scaler 0 to 127 376623 N scaler 3 to 16.380 R scaler 3 to 65.535 • Serial control (3-wire bus: data, clock, enable) for fast programming (Imax ~ 10 MHz) • Switchable polarity and phase detector current programmable • 2 Multifunction outputs • Digital phase detector output signals (e.g. for external charge pump) • Irn, Ivn outputs of the R and N scalers • Port 1 output (e.g. for standby of the prescaler) • External current setting for PD output • Lock detect output with gated anti-backlash pulse (quasi digital lock detect) 7\SH 9HUVLRQ 2UGHULQJ&RGH 3DFNDJH PMB 2306T V2.2 Q67100-H6423 P-DSO-14 (SMD) PMB 2306T V2.2 Q67106-H6423 P-DSO-14 (SMD, Tape & Reel) PMB 2306R V2.2 Q-67106-H6514 (T&R) P-TSSOP-16 (SMD, T&R) The PMB 2306T PLL is a high speed CMOS IC, especially designed for use in battery powered radio equipment and mobile telephones. The primary applications will be in digital systems e.g. GSM, PCN, ADC, JDC and DECT systems. The wide range of dividing ratios also allows application in modern analog systems Semiconductor Group 4 02.97 30%530%7 2YHUYLHZ 3LQ&RQILJXUDWLRQ (top view) 3'62 RI LD VSS MFO2 EN MFO1 DA VDD1 CLK PD VDD VSS1 MOD FI NC NC 376623 Semiconductor Group 5 02.97 30%530%7 2YHUYLHZ 3LQ'HILQLWLRQVDQG)XQFWLRQV 7DEOH '62 76623 6\PERO )XQFWLRQ 6 6 9DD Positive supply voltage for serial control logic. 2 2 9SS Ground for serial control logic. 11 13 9DD1 Positive supply voltage for the preamplifiers, counters, phase detector and charge pump. 9 11 9SS1 Ground for the preamplifiers, counters, phase detector and charge pump. (1RWH7KHSLQV9''DQG9''UHVSHFWLYHO\966DQG966 KDYHWRKDYHWKHVDPHVXSSO\YROWDJH.) 3 3 EN /LQH%XV(QDEOH Enable line of the serial control with internal pull-up resistor. When EN = H the input signals CLK and DA are disabled internally. When EN = L the serial control is activated. The received data are transferred into the latches with the positive edge of the EN-signal. 4 4 DA /LQH%XV'DWD Serial data input with internal pull-up resistor. The last two bits before the EN-signal define the destination address. In a byteoriented data structure the transmitted data have to end with the EN-signal, i.e. bits to be filled in (don’t care) are transmitted first. 5 5 CLK /LQH%XV&ORFN Clock line with internal pull-up resistor. The serial data are read into the internal shift register with the positive edge (see pulse diagram for serial data control). 7 7 MOD 0RGXOXV&RQWURO2XWSXW for external dual modulus prescaler. The modulus output is low at the beginning of the cycle. When the a-counter has reached its set value, MOD switches to high. When the n-counter has reached its set value, MOD switches to low again, and the cycle starts from the top. When the prescaler has the counter factor P or P + 1 (P for MOD = H, P + 1 for MOD = L), the overall scaling factor is NP + A. The value of the acounter must be smaller than that of the n-counter. The trigger edge of the modulus signal to the input signal can be selected (see programming tables and MOD A, B) according to the needs of the prescaler. In single modulus operation and for standby operation in dual modulus operation, the output is low. Semiconductor Group 6 02.97 30%530%7 2YHUYLHZ 7DEOH '62 76623 6\PERO )XQFWLRQ 8 10 FI 9&2)UHTXHQF\ Input with highly sensitive preamplifier for 14-bit n-counter and 7-bit a-counter. With small input signals AC coupling must be set up, where DC coupling can be used for large input signals. 1 1 RI 5HIHUHQFH)UHTXHQF\ Input with highly sensitive preamplifier for 16-bit r-counter. With small input signals AC coupling must be set up, where DC coupling can be used for large input signals. 10 12 PD 3KDVH'HWHFWRU Tristate charge pump output. The integrated, positive and negative current sources can be programmed with respect to their current density by means of the serial control. Activation and deactivation depend on the phase relationship of the scaled-down input signals FI:N, RI:R. (See phase detector output waveforms.) frequency IV <IR orIV lagging: p-channel current source active frequency IV > IR orIR leading: n-channel current source active frequency IV = IR and PLL locked: current sources are switched off, PD-output is tristate In standby mode the PD-output is set to tristate. The assignment of the current sources to the output signals of the phase detector can be swapped in it’s polarity, i.e. the sign of the phase detector constant can be controlled. 14 16 LD /RFN'HWHFWRU2XWSXW (open drain). Unipolar output of the phase detector in the form of a pulse-width modulated signal. The L-pulse width corresponds to the phase difference. Phase differences < 20 ns are not indicated due to gating of the antibacklash impuls. In the locked state the LD-signal is at H-level. In standby mode the output is resistive. Only for ABL status 11 no gating of ABL impulse is performed. Semiconductor Group 7 02.97 30%530%7 2YHUYLHZ 7DEOH '62 76623 6\PERO )XQFWLRQ 12 14 MFO1 0XOWLIXQFWLRQ2XWSXW for the signalsIRN, ΦV, ΦVN and port 1. 13 15 MFO2 0XOWLIXQFWLRQ,23LQ for the output signals IVN, ΦRN and the input signal ,REF. – The signals ΦR and ΦV are the digital output signals of the phase and frequency detector for use in external active current sources (see phase detector output wave forms). – The signals IRN and IVN are the scaled down signals of the reference frequency and VCO-frequency. The L-time corresponds to 1/IRI and 1/IFI respectively. – In the port function the port 1 output signal is assigned to the information of the status program. The output switches with the rising edge of the EN-signal. The standby mode does not affect the port function. – In the internal charge pump mode the input signal ,REF determines the value of the PD-output current. Reference current for charge pump: ,REF = (9DD – 9REF)/R1 = 100µA (tolerance of ±20% or less is recommended) R1:see application circuit 9REF:see AC/DC characteristics Semiconductor Group 8 02.97 30%530%7 2YHUYLHZ )XQFWLRQDO%ORFN'LDJUDP Semiconductor Group 9 02.97 30%530%7 &LUFXLW'HVFULSWLRQ &LUFXLW'HVFULSWLRQ *HQHUDO'HVFULSWLRQ The circuit consists of a reference-, a- and n-counter, a dual modulus control logic, a phase detector with charge pump output and a serial control logic. The setting of the operating mode and the selection of the counter ratios is done serially at the ports CLK, DA and EN. The operating modes allow the selection of single or dual operation, asynchronous or synchronous data acquisition, 4 different antibacklash-impulse times, 8 different PDoutput current modes, polarity setting of the PD-output signal, adjustment of the triggeredge of the MOD-output signal, 2 standby modes and the control of the multifunction outputs MFO1 and MFO2. The reference frequency is applied at the RI-input and scaled down by the r-counter. It’s maximum value is 100 MHz. The VCO-frequency is applied at the FI-input and scaled down by the n- or n/a-counter according to single or dual mode operation. The maximum value at FI is 220 MHz at single-, and 65 MHz at dual mode operation. The phase and frequency sensitive phase detector produces an output signal with adjustable anti-backlash impulses in order to prevent a dead zone for very small phase deviations. Phase differences of less than 100 ps can be resolved. In general the shortest anti-backlash pulse gives the best system performance. 3URJUDPPLQJ Programming of the IC is done by a serial data control. The contents of the message are assigned to the functional units according to the address. 6LQJOH RU GXDO PRGH RSHUDWLRQ DV ZHOO DV DV\QFKURQRXV RU V\QFKURQRXV GDWD DFTXLVLWLRQ LV VHW E\ VWDWXVDQGVKRXOGWKHUHIRUHSUHFHGHWKHSURJUDPPLQJRIWKHFRXQWHUV 'DWDDFTXLVLWLRQ The PMB 2306T offers the possibility of synchronous data acquisition to avoid error signals at the phase detector due to non-corresponding dividing factors in the counters produced by asynchronous loading. Synchronous programming guarantees control during changes of frequency or channel. That means that the state of the phase detector or the phase difference is kept maintained, and in case of “lock in”, the control process starts with the phase difference “zero”. Semiconductor Group 10 02.97 30%530%7 &LUFXLW'HVFULSWLRQ This is done as follows: 1.Setting of synchronous data acquisition by status 2. 2.Programming of the r-counter, status 1 (optional)-data is being loaded into shadow registers. 3.Programming of the n- or n/a-counter-data is being loaded into shadow registers, the EN-signal starts the synchronous loading procedure. 4.Synchronous programming – which means data transfer of all data from the shadow registers to the data registers – takes place at that point in time when the respective counter reaches “zero + 1”, the maximum repetition rate for channel change is therefore IFI:N. 5.Transfer of status 1 information into the corresponding data register is tied to the ncounter loading, but follows the loading of the n-data register in the distance of one ncounter dividing ratio, this guarantees that for example a new PD-current value becomes valid at the same time when the counters are loaded with the new data. Synchronous avoids additional phase error caused by programming. Synchronous data acquisition is of especial advantage, when large steps in frequency are to be made in a short time. For this purpose a high reference frequency can be programmed in order to achieve rapid – “rough” – transient response. This method increases the fundamental frequency nearly by the square route of the reference frequency relation. When rough lock is achieved, another synchronous data transfer is needed to switch back to the original channel spacing. A “fine” lock in will finish the total step response. It may not be necessary to change reference frequency, but it make sense to perform synchronous data acquisition in any case. Especially for GSM, PCN, DECT, DAMPS, JDC, PHP systems the synchronous mode should be used to get best performance of the PMB 2306T. 6WDQGE\&RQGLWLRQ The PMB 2306T has two standby modes (standby 1, 2) to reduce the current consumption. Standby 1 switches off the whole circuit, the current consumption is reduced below 1 µA. Standby 2 switches off the counters, the charge pump and the outputs, only the preamplifiers stay active. The standby modes do not affect the port output signal. For the influence on the other output signals VHHVWDQGE\WDEOH 1RWH I51I91 Φ51 DQGΦ91DUHWKHLQYHUWHGVLJQDOVRII5I9Φ5DQGΦ9 Semiconductor Group 11 02.97 30%530%7 &LUFXLW'HVFULSWLRQ 3URJUDPPLQJ7DEOHV 6WDWXV%LWV 0XOWLIXQFWLRQ2XWSXWV 0RGH 0RGH 0)2 0)2 5HPDUNV 0 0 IRN IVN test mode 0 1 ΦV ΦRN external charge pump mode 1 1 0 ΦVN ΦRN external charge pump mode 2 1 1 Port 1 ,REF internal charge pump mode 6WDWXV%LWV 3'&XUUHQW0RGH 3'&XUUHQW 3'&XUUHQW 3'&XUUHQW 0 0 0 0.175 0 0 1 0.25 0 1 0 0.35 0 1 1 0.5 1 0 0 0.7 1 0 1 1 1 1 0 1.4 1 1 1 2 3URJUDPPLQJ7DEOHV(cont’d) 6WDWXV%LWV $QWL%DFNODVK 3XOVH:LGWK $QWL%DFNODVK 3XOVH:LGWK WZW\S >QV@ $SSOLFDWLRQ 0 0 1.3* 9DD = 5 V 0 1 5 1 0 10 not recommended 1 1 13** any application where continuous lock detect required * In general the shortest anti-backlash pulse gives the best system performance. ** No ABL (Anti-Backlash-Pulse) gating performed. This means, that at the LD output the anti-backlash pulse will appear. In the other cases the anti-backlash pulse will be surpressed at the LD output. Semiconductor Group 12 02.97 30%530%7 &LUFXLW'HVFULSWLRQ 6WDWXV%LWV 3UHDPSOLILHU)XQFWLRQ0RGH 6LQJOH'XDO 0RGH 3UHDPSOLILHU 6HOHFW 0 0 FI-input frequency, single HF-mode 0 1 FI-input frequency, single LF-mode 1 0 FI-input frequency, dual mode, FI-trigger edge LH, MOD A 1 1 FI-input frequency, dual mode, FI-trigger edge HL, MOD B 6WDQGE\7DEOH 2XWSXW3LQV 6WDWXV 0)2 0)2 /' 3' 02' Φ9 Φ91 Standby 1 low high high resistive tristate low Standby 2 low high high resistive tristate low Semiconductor Group 13 02.97 30%530%7 &LUFXLW'HVFULSWLRQ 6HULDO&RQWURO'DWD)RUPDWVWDWXV 6WDWXV 6WDWXV 0 1 Data acquisition mode 1 asynchronous synchronous Mode 1 2 see table Mode 2 3 PD-polarity 4 negative positive Standby 1 5 standby active Standby 2 6 standby active Anti-backlash pulse width 1 7 see table Anti-backlash pulse width 2 8 see table Preamplifier select 9 see table Single / dual mode 10 single dual 1 Port 1 11 low high 2 PD-current 1 12 see table 3 PD-current 2 13 see table 4 PD-current 3 14 see table 5 0 6 0 Address 0 15 1 16 EN see table EN 6LQJOHRUGXDOPRGHRSHUDWLRQDVZHOODVDV\QFKURQRXVRUV\QFKURQRXVGDWD DFTXLVLWLRQLVVHWE\VWDWXVDQGVKRXOGWKHUHIRUHSUHFHGHWKHSURJUDPPLQJRI WKHFRXQWHUVVHHDOVRSDJH Semiconductor Group 14 02.97 30%530%7 &LUFXLW'HVFULSWLRQ 6HULDO&RQWURO'DWD)RUPDWQQDFRXQWHU 'XDO0RGH 6LQJOH0RGH MSB 1 2 3 a-Counter 4 5 6 7 LSB 8 MSB MSB 1 9 2 10 3 11 4 12 5 13 6 14 7 n-Counter 15 8 16 9 17 10 18 11 19 12 20 13 LSB 21 22 1 23 0 LSB Address EN Semiconductor Group 14 1 15 0 16 EN 15 02.97 30%530%7 &LUFXLW'HVFULSWLRQ 6HULDO&RQWURO'DWD)RUPDWUFRXQWHU 1 MSB 2 3 4 5 6 7 8 r-Counter 9 10 11 12 13 14 15 LSB 16 17 1 18 1 Address EN Semiconductor Group 16 02.97 30%530%7 &LUFXLW'HVFULSWLRQ 3KDVH'HWHFWRUQ2XWSXW:DYHIRUPV Semiconductor Group 17 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV (OHFWULFDO&KDUDFWHULVWLFV $EVROXWH0D[LPXP5DWLQJV 7A = – 40 to 85 °C 3DUDPHWHU 6\PERO /LPLW9DOXHV PLQ PD[ 8QLW 5HPDUNV Supply voltage 9DD – 0.3 6 V Input voltage 9I – 0.3 9DD + 0.3 V Output voltage 9Q GND 9DD V Power dissipation per output 3Q 10 mW Total power dissipation 3tot 300 mW Ambient temperature 7A – 40 85 °C Storage temperature 7stg – 50 125 °C Supply voltage 9DD 3.0 5.5 V Input frequency dual mode Input frequency single HF-mode Input frequency single LF-mode Input reference frequency Input frequency dual mode Input frequency single HF-mode Input frequency single LF-mode Input reference frequency IFI IFI IFI IRI IFI IFI IFI IRI 0.1 0.1 0.1 65 220 90 100 30 120 35 22 MHz MHz MHz MHz MHz MHz MHz MHz 9DD = 4.5 … 5.5 V 9DD = 4.5 … 5.5 V 9DD = 4.5 … 5.5 V 9DD = 4.5 … 5.5 V 9DD = 3.3 V 9DD = 3.3 V 9DD = 3.3 V 9DD = 3.3 V PD-output current PD-output voltage PD-output voltage / ,PD / 9PD 9PD 4 0.5 0.5 9DD – 0.5 9DD – 0.5 mA V V 9DD = 4.5 – 5.5 V 9DD = 3.3 V Ambient temperature 7A – 40 85 °C in operation 2SHUDWLQJ5DQJH 0.1 0.1 0.1 All pins are protected against ESD. Unused inputs without pullup resistors must be connected to either 9DD or 9SS. 7\SLFDO6XSSO\&XUUHQW,'' Supply voltage 9DD 3.3 5 5.5 V Supply current singlemode HF dual mode standby 2 standby 1 ,DD ,DD ,DD ,DD 1.63 1.76 0.11 2.6 2.80 0.62 2.94 3.17 0.75 1 mA mA mA µA Semiconductor Group 18 Test conditions: IFI = 50 MHz, 9FI = 150 mVrms IRI = 10 MHz, 9RI = 150 mVrms ,PD = 0.25 mA, ,ref = 100 µA 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV $&'&&KDUDFWHULVWLFV 3DUDPHWHU 6\PERO /LPLW9DOXHV PLQ 8QLW 7HVW&RQGLWLRQ W\S PD[ ,QSXW6LJQDOV'$&/.(1ZLWKLQWHUQDOSXOOXSUHVLVWRUV H-input voltage L-input voltage Input capacity H-input current L-input current 9IH 9IL &I ,H ,L 0.7 9DD 0 9DD 0.3 9DD 5 10 – 300 V V pF µA µA 9I = 9DD = 5.5 V 9I = GND Further information about timing see at page 25 and 26 ,QSXW6LJQDO5, Input voltage 9I 100 Input voltage Slew rate Input capacity H-input current L-input current 9I 100 2.5 &I ,H ,L 3 30 – 30 mVrms I = 4 … 100 MHz, 9DD =4.5 V mVrms I = 4 … 22 MHz, 9DD = 3.3 V 9DD = 3.3 … 5.5 V V/µs pF µA 9I = 9DD = 5.5 V µA 9I = GND ,QSXW6LJQDO),GXDOPRGH Input voltage Input voltage Input voltage Slew rate Input capacity H-input current L-input current 9I 9I 9I &I ,H ,L 180 180 50 4 3 30 – 30 mVrms mVrms mVrms V/µs pF µA µA I = 4 … 65 MHz, 9DD = 4.5 V I = 4 … 30 MHz, 9DD = 3.3 V I = 10 … 30 MHz, 9DD = 3.3 V 9DD = 3.3 … 5.5 V mVrms mVrms mVrms V/µs pF µA µA I = 4 … 220 MHz, 9DD = 4.5 V I = 4 … 120 MHz, 9DD = 3.3 V I = 10 … 50 MHz, 9DD = 4.5 V 9DD = 3.3 … 5.5 V 9I = 9DD = 5.5 V 9I = GND ,QSXW6LJQDO),VLQJOH+)PRGH Input voltage Input voltage Input voltage Slew rate Input capacity H-input current L-input current 9I 9I 9I &I ,H ,L Semiconductor Group 200 20 50 2.5 3 30 – 30 19 9I = 9DD = 5.5 V 9I = GND 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV 3DUDPHWHU 6\PERO /LPLW9DOXHV PLQ 8QLW 7HVW&RQGLWLRQ mVrms mVrms V/µs pF µA µA I = 4 … 90 MHz, 9DD = 4.5 V I = 4 … 35 MHz, 9DD = 3.3 V 9DD = 3.3 … 5.5 V W\S PD[ ,QSXW6LJQDO),VLQJOH/)PRGH Input voltage Input voltage Slew rate Input capacity H-input current L-input current 9I 9I &I ,H ,L 100 100 2.5 3 30 – 30 9I = 9DD = 5.5 V 9I = GND 2XWSXW&XUUHQW,3' Current mode “0.175 mA” “0.25 mA” “0.35 mA” “0.5 mA” “0.7 mA” “1.0 mA” “1.4 mA” “2.0 mA” “Standby” * guaranteed by design ,PROG ,PROG ,PROG ,PROG ,PROG ,PROG ,PROG ,PROG / ,PD / – 20 % – 20 % – 20 % – 20 % – 20 % – 10 % – 10 % – 10 % 0.1* + 20 % + 20 % + 20 % + 20 % + 20 % + 10 % + 10 % + 10 % 50 mA mA mA mA mA mA mA mA nA 9DD = 4.5 … 5.5 V 9PD = 9DD/2 ,REF = 100 µA 9DD = 5.5 V 2XWSXW7ROHUDQFHV,3' ∆ ,PD / ,PROG – 20 % ∆ ,PD / ,PROG 9PD = 9DD/2, 9DD = 3.3 V +3% 9PD = 1 … 4 V, 9DD = 5 V ±4% ,QSXW9ROWDJH0)2LQWHUQDOFKDUJHSXPSPRGH Reference voltage 9REF Semiconductor Group 0.9 1.1 1.3 20 V 9DD = 4.5 … 5.5 V, ,REF = 100 µA 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV 3DUDPHWHU 6\PERO /LPLW9DOXHV PLQ 8QLW 7HVW&RQGLWLRQ V 9DD = 4.5 … 5.5 V, ,QH = 2 mA 9DD = 4.5 … 5.5 V, ,QL = 2 mA 9DD = 3.3 V, ,QH = 1.2 mA 9DD = 3.3 V, ,QL = 1.2 mA 9DD = 4.5 … 5.5 V, &I = 10 pF 9DD = 4.5 … 5.5 V, &I = 10 pF 9DD = 3.3 V, &I = 10 pF 9DD = 3.3 V, &I = 10 pF W\S PD[ 2XWSXW6LJQDO0)2SXVKSXOO H-output voltage 9QH L-output voltage H-output voltage L-output voltage Rise time Fall time Rise time Fall time 9QL 9QH 9QL WR WF WR WF 9DD – 1 1 9DD – 1 2.5 2.0 4.0 2.5 1 10 10 10 10 V V V ns ns ns ns 2XWSXW6LJQDO0)2SXVKSXOO H-output voltage 9QH L-output voltage H-output voltage L-output voltage Rise time Fall time Rise time Fall time 9QL 9QH 9QL WR WF WR WF 9DD – 1 V 1 9DD – 1 2 2 3 3 1 10 10 10 10 V V V ns ns ns ns 0.4 V 0.4 10 10 V ns ns 9DD = 4.5 … 5.5 V, ,QH = 2 mA 9DD = 4.5 … 5.5 V, ,QL = 2 mA 9DD = 3.3 V, ,QH = 1.2 mA 9DD = 3.3 V, ,QL = 1.2 mA 9DD = 4.5 … 5.5 V, &I = 10 pF 9DD = 4.5 … 5.5 V, &I = 10 pF 9DD = 3.3 V, &I = 10 pF 9DD = 3.3 V, &I = 10 pF 2XWSXW6LJQDO/'QFKDQQHORSHQGUDLQ L-output voltage 9QL L-output voltage Fall time Fall time 9QL WF WF Semiconductor Group 3 4.5 21 9DD = 4.5 … 5.5 V, ,QL = 0.5 mA 9DD = 3.3 V, ,QL = 0.5 mA 9DD = 4.5 … 5.5 V, &I = 10 pF 9DD = 3.3 V, &I = 10 pF 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV 3DUDPHWHU 6\PERO /LPLW9DOXHV PLQ 8QLW 7HVW&RQGLWLRQ V V 9DD = 4.5 … 5.5 V, ,QH = 0.5 mA 9DD = 4.5 … 5.5 V, ,QL = 0.5 mA 9DD = 3.3 V, ,QH = 0.3 mA V ns ns ns 9DD = 3.3 V, ,QL = 0.3 mA 9DD = 4.5 … 5.5 V, &I = 5 pF 9DD = 4.5 … 5.5 V, &I = 5 pF 9DD = 4.5 … 5.5 V, &I = 5 pF W\S PD[ 2XWSXW6LJQDO02'SXVKSXOO H-output voltage 9QH L-output voltage 9QL H-output voltage 9QH 9DD – 0.4 0.4 9DD V – 0.4 L-output voltage Rise time Fall time Propagation delay time H-L to FI Propagation delay time L-H to FI Rise time Fall time Propagation delay time H-L to FI Propagation delay time L-H to FI 9QL WR WF WDQHL 1.5 1.3 8 0.4 3 3 12 WDQLH 8 12 ns 9DD = 4.5 … 5.5 V, &I = 5 pF WR WF WDQHL 2.8 1.6 12 4 4 ns ns ns 9DD = 3.3 V, &I = 5 pF 9DD = 3.3 V, &I = 5 pF 9DD = 3.3 V, &I = 5 pF WDQLH 12 ns 9DD = 3.3 V, &I = 5 pF Semiconductor Group 22 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV (TXLYDOHQW,26FKHPDWLFV Semiconductor Group 23 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV (TXLYDOHQW,26FKHPDWLFV (cont’d) 500kΩ Semiconductor Group 24 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV 3XOVH'LDJUDP Semiconductor Group 25 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV 6HULDO&RQWURO'DWD,QSXW7LPLQJ 3DUDPHWHU 6\PERO /LPLW9DOXHV PLQ 8QLW 7HVW&RQGLWLRQ MHz 9DD=3.3V PD[ Clock frequency ICL H-pulsewidth (CL) WWHCL 40 ns Data setup WDS 20 ns Setup time clock-enable WCLE 20 ns Setup time enable-clock WECL 20 ns H-pulsewidth (enable) WWHEN 40 ns Rise, fall time WRWF 10 µs Propagation delay time EN-PORT WDEP 1 µs Semiconductor Group 12 26 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV ,QSXW6HQVLWLYLW\6LJQDO),VLQJOH+)PRGH Semiconductor Group 27 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV T 4 *60$SSOLFDWLRQ&LUFXLW Semiconductor Group 28 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV /LVWRI&RPSRQHQWV ,WHP 4XDQWLW\5HIHUHQFH 1 2 3 4 5 6 7 8 9 10 1 2 1 1 1 1 4 1 1 1 11 12 13 14 15 1 1 1 6 57 513, 514 56 58 510 512 59, 53, 55, 511 54 52 52 3DUW 100 Ω 150 Ω 220 Ω 330 Ω 3.3 kΩ 6.8 kΩ 8.2 kΩ 18 kΩ 22 kΩ 39 kΩ SMD/0805 B54102-A1101-K60 SMD/0805 B54102-A1151-J60 SMD/0805 B54102-A1221-J60 SMD/0805 B54102-A1331-J60 SMD/0805 B54102-A1332-J60 SMD/0805 B54102-A1682-J60 SMD/0805 B54102-A1822-J60 SMD/0805 B54102-A1183-J60 SMD/0805 B54102-A1223-J60 SMD/0805 B54102-A1393-J60 S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M 1 /1 22 nH SIMID 01 B82412-A3220-M S+M 1.2 pF 2.2 pF 10 pF COG/0805 B37940-K5010-C262 COG/0805 B37940-K5020-C262 COG/0805 B37940-K5100-J62 S+M S+M S+M 16 17 18 19 20 21 22 &11 &13 &8 &20, &10, &12, &14, &15, &16 3 &17, &1, &2 1 &9 1 &3 1 &5 1 &7 1 &6 1 &19 22 pF 33 pF 100 pF 330 pF 560 pF 5.6 nF 100 nF 22 µF COG/0805 B37940-K5220-J62 COG/0805 B37940-K5330-J62 COG/0805 B37940-K5101-J62 COG/0805 B37940-K5331-J62 COG/0805 B37940-K5561-J62 COG/1210 B37949-K5562-J62 X7R/1210 B37950-K5104-K62 B45196-E3226-+409 S+M S+M S+M S+M S+M S+M S+M S+M 23 24 25 1 D1 2 T3, T2 1 T1 BBY 51 BFR 280 BFT 92 26 27 28 29 1 2 1 1 30 1 IC2 &4 X2, X1 RX IC1 Semiconductor Group Q62702-B631 Q62702-F1298 Q62702-F1062 1,0 nF COG/1210 B37949-K5102-J62 SMA Connector 1.3 GHz B69610-G1307-A412 PMB 2306T P-DSO-14 Q67100-H6423 PMB 2306T P-DSO-14 Q67106-H6423(T+R) PMB 2314 P-DSO-8 Q67000-A6121 PMB 2314 P-DSO-8 Q67006-A6121(T+R) 29 SIEMENS SIEMENS SIEMENS S+M S+M SIEMENS SIEMENS SIEMENS SIEMENS 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV 3KDVH1RLVH&ORVHWRWKH&DUULHU Semiconductor Group 30 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV 6SHFWUXPDW/RZHU(QGRI*607;%RDUG0RELOH Semiconductor Group 31 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV /RFN,Q7LPHIRU*60$SSOLFDWLRQ Semiconductor Group 32 02.97 30%530%7 (OHFWULFDO&KDUDFWHULVWLFV 0HDVXUHPHQW6HW8SIRU/RFN,Q7LPH Semiconductor Group 33 02.97 30%530%7 3DFNDJH2XWOLQHV 3DFNDJH2XWOLQHV 3ODVWLF3DFNDJH376623 Semiconductor Group 34 02.97 30%530%7 3DFNDJH2XWOLQHV 3ODVWLF3DFNDJH3'6260' GPM05247 6RUWVRI3DFNLQJ Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 35 Dimensions in mm 02.97