IMI145152 FREQUENCY SYNTHESIZER CMOS LSI PARALLEL TUNING PLL FREQUENCY SYNTHESIZER February 1996 PRODUCT DESCRIPTION PRODUCT FEATURES The IMI145152 is a member of a family of phase lock loop synthesizer Ics from International Microcicruicts. This part is pin-for-pin compatible with the Motorola MC145152 series of parts. The IMI145152 is an improved version of this device, and designing to take advantage of these improvements will provide a synthesizer with noticeably improved performance. The IMI145152 is programmed with parallel input data lines. Since it does not require a microcontroller as serial and bus programming units do, the IMI145152 is an excellent choice for synthesizers requiring independence from digital controllers. Such applications particularly include fixed local oscillator signals, who tuning never changes, and signal sources, which have few operating frequencies. Blocks in the IMI145152 include a dual modulus feedback divider for use with an external dual modulus prescaler. Prescaler ratios can very from 3/4 through 64/65. The reference divider is set by three select lines to one of eight ROM encloded values. Both counter inputs are biased for high sensitivity to sinewave input signals, and the reference divider input is also configured to operate as an oscillator if desired. The phase detector is a Type IV phase-frequency design, which has inherently eliminated the dead zone and indeed any crossover distortion, as is often noticed on other PLL devices. Performance improvements are in the operating and phase detector noise floor. With its extremely noise floor and wider input bandwidth, prescaler be minimized to allow wide loop bandwidths settlign and lower phase noise. æ > 150 Mhz typical input frequency æ -163 dBc/Hz total phaswe noise floor æ No dead zone, by design æ Unambiguous PLL acquisition æ Parrallel programming, dual modulus PLL æ 8 user-selectable reference divider ratios: 8, 64, 128, 256, 512, 1024, 1160, and 2048 æ Lock detect signal æ Compatible with dual-modulus prescalers from ÷3/4 to ÷64/65 æ 10-bit N counter, 6-bit A counter æ On- or off-chip reference oscillator operation æ 3-volt and 5-volt characterizations bandwidth low phase ratios can for faster BLOCK DIAGRAM RA2 6 RA1 5 RA0 4 OSCin OSCout LOCK DETECT 28 PHASE DETECTOR 8 PHIV 7 PHIR LD 12 x 8 ROM REFERENCE DECODER 27 12 BIT /R COUNTER 26 CONTROL LOGIC FIN 1 9 6 BIT /A COUNTER 10 A5 10 BIT /N COUNTER 25 24 22 21 23 11 12 13 14 15 16 A4 A3 A2 A1 A0 N0 N1 N2 N3 N4 N5 17 MODULUS CONTROL 18 19 N6 N7 N8 20 VDD = PIN 3 VSS = PIN 2 N9 Note: N0 through N9 have pullup resistors not shown. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571 Page 1 of 12 IMI145152 FREQUENCY SYNTHESIZER CMOS LSI PARALLEL TUNING PLL FREQUENCY SYNTHESIZER February 1996 MAXIMUM RATINGS Voltage Relative to VSS: Voltage Relative to VDD: Storage Temperature: Ambient Temperature: This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum reated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: -0.3V to 7V 0.3V -65°C to 150°C -55°C to 125°C VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). PIN DESCRIPTIONS PinNo. Name Description 1 Fin Feedback divider input signal. Applied to both the N and A positive edge triggered counters, this signal is intended to be AC coupled. For CMOS logic level input signals, DC coupling can be used. 2 Vss Circuit ground. 3 Vdd Circuit positive power supply. 4 5 6 RA0 RA1 RA2 The three reference divisor ratio select pins. Pull-up resistors RA1 are included on each of these pins to insure that, if left RA2 unconnected, they will raimain at a logic ONE. The reference divider ratio is set accourding to the following table RA2 RA1 RA0 Reference Divider Ratio 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 64 128 256 512 1024 1160 2048 7 PHIR Phase detector output. This signal goes LOW when the feedback frequency is too low. 8 PHIV Phase detector output. This signal goes LOW when the feedback frequency is too high. 9 MC Prescaler modulus control output signal. MC is HIGH when the prescaler is to devide by its base modulus (P). MC is LOW when the prescaler is to divide by P+1. 10 A5 MSB of the A counter programming input bits. Pull-up resistor included. 11 N0 LSB of the N counter programming input bits. Pull-up resistor included. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571 Page 2 of 12 IMI145152 February 1996 FREQUENCY SYNTHESIZER CMOS LSI PARALLEL TUNING PLL FREQUENCY SYNTHESIZER PIN DESCRIPTIONS (Cont.) PinNo. Name Description 12 N1 LSB + 1 of the N counter programming input bits. Pull-up resistor included. 13 N2 LSB + 2 of the N counter programming input bits. Pull-up resistor included. 14 N3 LSB + 3 of the N counter programming input bits. Pull-up resistor included 15 N4 LSB + 4 of the N counter programming input bits. Pull-up resistor included 16 N5 LSB + 5 of the N counter programming input bits. Pull-up resistor included 17 N6 LSB + 6 of the N counter programming input bits. Pull-up resistor included 18 N7 LSB + 7 of the N counter programming input bits. Pull-up resistor included 19 N8 LSB + 8 of the N counter programming input bits. Pull-up resistor included 20 N9 MSB of the N counter programming input bits. Pull-up resistor included 21 A1 LSB + 1 of the A counter programming input bits. Pull-up resistor included 22 A2 LSB + 2 of the A counter programming input bits. Pull-up resistor included 23 A0 LSB of the A counter programming input bits. Pull-up resistor included 24 A3 LSB + 3 of the A counter programming input bits. Pull-up resistor included 25 A4 LSB + 4 of the A counter programming input bits. Pull-up resistor included 26 OSCout Reference signal output or output of the oscilator inverter. 27 OSCin AC-coupled reference signal input or input to the oscillator inverter. 28 LD Lock detect output. When the PLL is locked, this signal will be essentially HIGH, with very narrow negative spikes at the phase detection frequency. If the PLL is out of lock, this signal will pulse LOW. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571 Page 3 of 12 IMI145152 FREQUENCY SYNTHESIZER CMOS LSI PARALLEL TUNING PLL FREQUENCY SYNTHESIZER February 1996 PLL OPERATING CHARACTERISTICS VDD = 5 VOLTS -40ºC Characteristics Dynamic 70ºC 85ºC Min Max Min Max Min Typ Max Min Max Min Max Unit Sine 180 - 170 - 160 180 - 150 - 140 - Mhz Square 180 - 170 - 160 200 - 150 - 140 - Mhz - 6.5 - 7 - 6.8 7.5 - 8 - 8 ns Operating Modulus Control Prop. Dealy 25ºC Symbol fin, Frequency 0ºC fosc Conditions Mhz Mcpd Synthesizer Phase Noise Floor -160 PDNF Pin Cin - 10 - 6 10 - 10 pF Capacitance Cout - 10 - 6 10 - 10 pF Input VIL 1 1.5 - 1.5 - 2.75 1.5 - 1.5 - 1.5 Vdc Voltages VIH 3.5 - 3.5 - 3.5 2.75 - 3.5 - 3.5 - Output VOL - 0.05 - 0.05 - 0.0 0.05 - .05 - 0.05 Voltages VOH 4.95 - 4.95 - 4.95 5.0 - 4.95 - 4.95 - Logic 2.4 - 2.0 2.8 - 1.6 - OSCout 1.2 - 2.0 1.4 - 0.8 - Logic -2.4 - -2.0 -2.8 - -1.6 - mA VOH = 4.0 OSCout -1.2 - -1.0 -1.4 - -0.8 - mA VOH = 4.0 mA fosc=fin=10 MHz uA fosc=fin=0 uA VIL = 0 IOL Static Output Current Supply Currents IOH dBc/ Hz IDD ISB IPU - 150 - 40 50 150 - 150 Vdc mA VOL = 0.40 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571 Page 4 of 12 IMI145152 FREQUENCY SYNTHESIZER CMOS LSI PARALLEL TUNING PLL FREQUENCY SYNTHESIZER February 1996 PLL OPERATING CHARACTERISTICS VDD = 3 VOLTS -40ºC Characteristics 25ºC 70ºC 85ºC Symbol Min Max Min Max Min Typ Max Min Max Min Max Unit Sine 140 - 130 - 130 140 - 120 - 110 - Mhz Square 140 - 130 - 130 150 - 120 - 110 - Mhz fin, Operating Dynamic 0ºC Frequency fosc Modulus Control Prop. Dealy Mcpd Synthesizer Phase Noise Floor PDNF Pin Cin Conditions Mhz - 10 - 10.5 - 10.5 11 - 12 - 12.5 -155 - 10 - 6 ns dBc/ Hz 10 - 10 pF Capacitance Cout - 10 - 6 10 - 10 pF Input VIL - 0.9 - 1.35 0.9 - 0.9 Vdc Voltages VIH 2.1 - 2.1 1.65 - 2.1 - Output VOL - 0.05 - 0.05 - 0.0 0.05 - 0.05 - 0.05 Voltages VOH 2.95 - 2.95 - 2.95 3.0 - 2.95 - 2.95 - Logic 1.6 - 1.4 2.0 - 0.8 - OSCout 0.8 - 0.7 1.0 - 0.4 - Logic -1.6 - -1.4 -2.0 - -0.8 - mA VOH=2.4 OSCout -0.8 - -0.7 -1.0 - -0.4 - mA VOH = 2.4 mA fosc=fin=10 MHz uA fosc=fin=0 uA VIL = 0 IOL Static Output Current Supply Currents IOH IDD ISB - 150 IPU - 40 30 150 - 150 Vdc mA VOL = 0.30 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571 Page 5 of 12 IMI145152 FREQUENCY SYNTHESIZER CMOS LSI PARALLEL TUNING PLL FREQUENCY SYNTHESIZER February 1996 IDDvs VDD Fin = OSCin = 10MHz Power Consumption vs. Frequency 2.5 6 2 5 4 IDD (mA) IDD (mA) 1.5 1 0.5 5 VDC 3 3 VDC 2 1 -40c 25c 0 3¸ 4 5 6 7 0 0 10 20 30 40 85c Operating Frequency (MHz) VDD 3 VDC Input Sensitivity vs. Temp 5 VDC Input Sensitivity vs. Temp 0 -10 +85C -20 +25C -30 -40C 190 160 130 100 70 40 10 -40 MHz PD LINEARITY 5 VOLTS dBm (50 ohms) dBm (50 ohms) 10 10 5 0 -5 -10 -15 -20 -25 -30 -35 +85C +25C -40C 0 50 100 150 200 MHz PD LINEARITY 3 VOLTS INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571 Page 6 of 12 IMI145152 FREQUENCY SYNTHESIZER CMOS LSI PARALLEL TUNING PLL FREQUENCY SYNTHESIZER February 1996 PHASE NOISE FLOOR 152/HP 10811A Ref vs 8662 Loop/Residual Noise @ 145 MHZ (hp) 3018R Carrier: 145.E+6 Hz 8 Nov 1994 13:07:47 - 13:16:37 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -120 -130 -140 -150 -160 -160 -170 10 100 1K 10K 100K 1M 10M INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571 Page 7 of 12 IMI145152 FREQUENCY SYNTHESIZER CMOS LSI PARALLEL TUNING PLL FREQUENCY SYNTHESIZER February 1996 DUAL MODULUS PRESCALING Dual modulus prescaling is a widespread method used to effectively extend the operating frequency of a digital counter without sacrificing any frequency resolution. The key to understanding ths method is to remember the basics of division: When any two integers are divided, a quotient and a remainder will result. Two particular things should be noticed about this process. First, the remainder counts are spread among an equal number of quotient counts by the use of the prescaler modulus P+1. When the remainder has been counted, any remaining quotient counts are handled normally by prescaling with modulus P. This counter is thus performing When used here in a PLL, the numerator of this division is the required PLL total feedback divider ratio, called Ntot. The denominator is the base modulus of the dual modulus prescaler, P. The quotient is applied idrectly to the N counter, and the remainder is applied directly to the A counter. Both counters count down together toward zero. While the A counter counts, the MC (modulus control) output signal is LOW, setting the prescaler to divide by P+1. When the A counter reaches zero, the MC output is set HIGH while the N counter reaches zero, both counters are reset to theprogrammed inputs and the cycle is repeated. Ntot = A(P+1) + (N-A)P Some algebra on this relation yields Ntot = AP + A + NP - AP Ntot = NP + A which is just the definition of integer division. Second, for this to work, there must be more quotient ocunts than remainder counts for all possible values of Ntot in the synthesizer desing. If this wer enot true, then the N counter will reach zero and the cause the entire divider to be reset before the A counter is finished. there is a minimum value for Ntot for 2 which this requirement will always hold: Ntot> P -2. PROGRAMMING GUIDELINES APPLICABLE TO THE IMI145152 The system total divide value (Ntotal) will be dictated by the application: Ntotal = frequency into the prescaler frequency into the phase detector a. Propagation delay through the dual modulus prescaler. b. Prescaler setup or release time relative to its modulus control signal. c. Propagation time for Fin to the modulus control output for the IMI145152. = N*P + A N is the number programmed in the ÷ N counter; A is the number programmed into ÷ A counter. P and P + ! are two selectable divide ratios available in the two modulus prescaler. To have a range of Ntotal values in sequence, the ÷ A counter is programmed from zero through P-1 for a particular value N in the N counter. N is then incremented to N + !, and the ÷ A is sequenced from zero through P-1 again. To maximize system frequency capability, the dual modulus prescaler’s output must go from low to high after each group of P or P + !. input cycles. The prescaler should divide by P when its modulus control line is high, and by P + 1 when its modulus control is low. A. Fvco max divided by P may not exceed the frequency capability of Pin 1 of the IMI145152. B. The period of Fvco divided by P must be greater than the sum of the times: A usefull simplication in the IMI145152 programming code can be achieved by choosing the values for P of 8, 16, 32, or 64. For these cases, the desired value for N total will result when Ntotal in binary is used as the program code to the ÷ N and ÷ A counters in the following manner. b Assume the A counter contains “b” bits when 2 = P. Always program all higher order ÷ A counter bits above “b” to zero. C. Assume the ÷ N counter and ÷ A counter (with all the higher order bits above “b” ignored) combined into a single binary counter of 10+b bits in length. The MSB of this hypothetical counter is to correspond to the LSB of ÷ A. The system divide value, Ntotal, now results when the value of Ntotal in binary is used to program the “new” 10+b bit counter. A. B. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571 Page 8 of 12 IMI145152 FREQUENCY SYNTHESIZER CMOS LSI PARALLEL TUNING PLL FREQUENCY SYNTHESIZER February 1996 CONNECTIONS DIAGRAMS A4 A3 A0 A2 A1 N9 N8 24 23 22 21 20 19 15 N4 Vss 2 14 N3 VDD 3 13 N2 RA0 4 12 N1 11 1 N0 N5 Fin 10 16 A5 28 9 N6 LD Mod Control N7 17 8 18 27 PHIV 26 OSCin 7 OSCout PHIR Pin No. 1 Index 25 LD OSCin OSCout A4 A3 A0 A2 A1 N9 N8 N7 N6 N5 N4 6 28 27 26 25 24 23 22 21 20 19 18 17 16 15 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RA2 fin Vss VDD RA0 RA1 RA2 PHIR PHIV Mod Control A5 N0 N1 N2 N3 PLCC PACKAGE RA1 SSOP, SOIC AND PDIP PACKAGES TYPICAL APPLICATION CIRCUIT 2400 - 2483 1 MHz Steps - VCO + 8 MHz X0 Fosc RA0 RA1 RA2 Fin IMI MC 145152 SP8714 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571 Page 9 of 12 IMI145152 FREQUENCY SYNTHESIZER CMOS LSI PARALLEL TUNING PLL FREQUENCY SYNTHESIZER February 1996 PACKAGE DRAWING AND DIMENSIONS C 28 PIN PLASTIC DIP DIMENSIONS E2 INCHES a SYMBOL E E1 D B2 Q2 Q A1 B1 e1 S A L MIN NOM MAX MIN NOM MAX A - - .180 - - 4.57 A1 0.020 - - 0.51 - - B 0.015 0.0.8 0.020 0.38 0.46 0.51 B1 0.045 0.050 0.055 1.14 1.27 1.40 B2 0.035 0.040 0.045 0.89 1.02 1.14 C 0.008 0.010 0.012 0.20 0.25 0.30 D 1.360 1.365 1.370 34.54 34.67 34.80 E 0.300 - 0.325 7.62 - 8.255 E1 0.280 0.282 0.284 7.11 7.16 7.2` E2 0.282 0.284 0.286 7.16 7.21 7.25 e1 B L 0.100 BSC 0.128 a P-DIP MILLIMETERS 2.54 BSC 0.130 0.135 7° 15° 0° 3.18 3.30 0° 7° 3.43 15° Q1 0.055 0.060 0.065 1.40 1.52 1.65 Q2 - 130 - - 3.30 - S 0.028 0.033 0.038 0.71 0.84 0.97 28 PIN SSOP OUTLINE DIMENSIONS MILLIMETERS C L H E D a A2 A SYMBOL INCHES MIN NOM MAX MIN NOM MAX A 0.08 0.073 0.078 1.73 1.8 1.99 A1 0.002 0.005 0.008 0.05 0.13 0.21 A2 0.066 0.068 0.070 1.68 1.73 1.78 B 0.010 0.012 0.015 0.25 0.30 0.38 C 0.005 0.006 0.009 0.13 0.15 0.22 D 0.397 0.402 0.407 10.07 10.20 10.33 E 0.205 0.209 0.212 5.20 5.30 5.38 A1 B e SSOP e 0.0256 BSC 0.65 BSC H 0.301` 0.307 0.311 7.65 7.80 7.90 a 0° 4° 8° 0° 4° 8° L 0.022 0.030 0.037 0.55 0.75 0.95 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571 Page 10 of 12 IMI145152 FREQUENCY SYNTHESIZER CMOS LSI PARALLEL TUNING PLL FREQUENCY SYNTHESIZER February 1996 PACKAGE DRAWING AND DIMENSIONS (Cont.) D 28 PIN PLCC PACKAGE DIMENSIONS E e B .0 4 5 X 4 5 D E G CHAMFER PIN 1 IDENT. .070 DIA X .023 DP E D .045 X 45 DEGREE CORNER CHAMFER INCHES SYMBOL MIN NOM MILLIMETERS MAX MIN NOM MAX A 0.147 0.152 0.157 3.73 3.86 3.99 A1 .0085 .0100 .0115 0.215 0.254 0.292 B 0.026 0.029 0.032 0.660 0.736 0.813 b 0.013 0.017 0.021 0.330 0.432 0.533 D 0.485 0.490 0.495 12.32 12.44 12.57 E 0.443 0.448 0.453 11.25 11.38 11.51 E1 0.410 0.420 0.430 10.41 10.67 10.92 e 0.048 0.050 0.052 1.22 1.27 1.32 H 0.448 0.453 0.458 11.38 11.51 11.63 H b H 7 + 2 DEG A A1 E1 PLCC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571 Page 11 of 12 IMI145152 FREQUENCY SYNTHESIZER CMOS LSI PARALLEL TUNING PLL FREQUENCY SYNTHESIZER February 1996 PACKAGE DRAWING AND DIMENSIONS (Cont.) 28 PIN SOIC OUTLINE DIMENSIONS C INCHES L SYMBOL H E D a A2 A MIN NOM MAX A 0.097 0.101 0.104 2.46 2.56 2.64 A1 0.005 0.009 0.0115 0.127 0.22 0.29 A2 0.090 0.092 0.094 2.29 2.34 2.39 MAX MIN 0.48 B 0.014 0.016 0.019 0.35 0.41 C 0.0091 0.010 0.0125 0.23 0.25 0.32 D 0.701 0.706 0.711 17.81 17.93 18.06 E 0.292 0.296 0.299 7.42 7.52 7.59 e A1 NOM MILLIMETERS H .050 BSC 0.400 0.406 1.27 BSC 0.410 10.16 10.31 10.41 e a 0° 5° 8° 0° 5° 8° SOIC L 0.024 0.032 0.40 0.61 0.81 1.02 B ORDERING INFORMATION Part Number Package Type Production Flow IMI145152xPB 28 PIN Plastic Dip Industrial, -40°C to + 85°C Industrial, -40°C to + 85°C IMI145152xXB 28 PIN SOIC IMI145152xQB 28 PIN PLCC Industrial, -40°C to + 85°C IMI145152xYB 28 PIN SSOP Industrial, -40°C to + 85°C Note: The “x” following the IMI Device Number denotes the device revision. The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: IMI IMI145152xXB Date Code, Lot # IMISC498xXB Flow B = Industrial, -40°C to + 85°C Package P = Plastic Dip X = SOIC Q = PLCC Y = SOIC Revision IMI Device Number INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571 Page 12 of 12