ETC HY5116400CT-60

HY5117400C,HY5116400C
4Mx4, Fast Page mode
DESCRIPTION
This family is a 16M bit dynamic RAM organized 4,194,304 x 4-bit configuration with Fast Page mode CMOS DRAMs.
Fast Page mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this
device to achieve high performance and low power dissipation. Optional features are access time(50, 60 or 70ns) and
refresh cycle(2K ref. or 4K ref.) and power consumption (Normal or Low power with self refresh). Hyundai’s advanced
circuit design and process technology allow this device to achieve high bandwidth, low power consumption and
high reliability.
FEATURES
Ÿ Fast Page mode operation
Ÿ Read-modify-write Capability
Ÿ TTL compatible inputs and outputs
Ÿ /CAS-before-/RAS, /RAS-only, Hidden and
Self refresh capability
Ÿ JEDEC standard pinout
Ÿ 24/26-pin Plastic SOJ (300mil)
24/26-pin plastic TSOP-II (300mil)
Ÿ Single power supply of 5.0V ± 10%
Ÿ Early write or output enable controlled write
Ÿ Max. Active power dissipation
Ÿ Fast access time and cycle time
Speed
2K refresh
4K refresh
Speed
tRAC
tCAC
tPC
50
798mW
605mW
50
50ns
13ns
35ns
60
660mW
495mW
60
60ns
15ns
40ns
70
550mW
440mW
70
70ns
18ns
45ns
Ÿ Refresh cycle
Part number
Refresh
Normal
HY5117400C
2K
32ms
HY5116400C
4K
64ms
SL-part
256ms
ORDERING INFORMATION
Part Name
Refresh
HY5117400CJ
2K
HY5117400CSLJ
2K
HY5117400CT
2K
HY5117400CSLT
2K
HY5116400CJ
4K
HY5116400CSLJ
4K
HY5116400CT
4K
HY5116400CSLT
4K
Power
Package
24/26Pin SOJ
SL-part
24/26Pin SOJ
24/26Pin TSOP-II
SL-part
24/26Pin TSOP-II
24/26Pin SOJ
SL-part
24/26Pin SOJ
24/26Pin TSOP-II
SL-part
24/26Pin TSOP-II
*SL : Low power with self refresh
This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of
circuits described. No patent licences are implied
Hyundai Semiconductor
Rev.00 / Sep.97
1
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HY5117400C,HY5116400C
FUNCTIONAL BLOCK DIAGRAM
DQ0 DQ1 DQ2 DQ3
4
4
Data Input Buffer
Data Output Buffer
DQ0~3
DQ0~3
WE
CAS
4
OE
4
CAS Clock
Generator
RAS
Address Buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
*(A11)
(11/10)*
Cloumn Predecoder
(11/10)*
Column Decoder
Sense Amp
I/O Gate
Refresh Controller
Refresh Counter
Row
Decoder
Row Predecoder
(11/12)*
Memory Array
4,194,304 x 4
(11/12)*
RAS Clock
Generator
Substrate Bias
Generator
X16 Parallel
Test
*(A11) for 4K refresh part
(2K Refresh / 4K Refresh)*
4Mx4,Fast Page DRAM
Rev.00 / Sep.97
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VCC
VSS
HY5117400C,HY5116400C
PIN CONFIGURATION (Marking Side)
VCC
DQ0
DQ1
WE
RAS
*(N.C) A11
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
•
8
9
10
11
12
13
26
25
24
23
22
21
VSS
DQ3
DQ2
CAS
OE
A9
VCC
DQ0
DQ1
WE
RAS
*(N.C) A11
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
A10
A0
A1
A2
A3
VCC
24/26Pin Plastic SOJ (300mil)
PIN DESCRIPTION
Parameter
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
/OE
Output Enable
A0~A11
Address Input (4K Refresh Product)
A0~A10
Address Input (2K Refresh Product)
DQ0~DQ3
Data In/Out
Vcc
Power (3.3V)
Vss
Ground
NC
No Connection
•
8
9
10
11
12
13
26
25
24
23
22
21
VSS
DQ3
DQ2
CAS
OE
A9
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
24/26Pin Plastic TSOP-II (300mil)
(N.C)* : For 2K refresh product
Pin Name
1
2
3
4
5
6
4Mx4,Fast Page DRAM
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HY5117400C,HY5116400C
ABSOLUTE MAXIMUM RATING
Symbol
Parameter
Rating
Unit
TA
Ambient Temperature
0 to 70
°C
TSTG
Storage Temperature
-55 to 150
°C
VIN, VOUT
Voltage on Any Pin relative to VSS
-1.0 to 7.0
V
VCC
Voltage on VCC relative to VSS
-1.0 to 7.0
V
IOS
Short Circuit Output Current
50
mA
PD
Power Dissipation
1
W
TSOLDER
Soldering Temperature Ÿ Time
260 Ÿ 10
°C Ÿ sec
Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0°C to 70°C )
Symbol
Parameter
Min
Typ
Max
UNIT
VCC
Power Supply Voltage
4.5
5.0
5.5
V
VIH
Input High Voltage
2.4
-
Vcc+1.0
V
VIL
Input Low Voltage
-1.0
-
0.8
V
Note : All voltages are referenced to VSS.
DC OPERATING CHARACTERISTIC
Symbol
Parameter
Test condition
Min
Max
Unit
ILI
Input Leakage Current
(Any input)
VSS ≤ VIN ≤ VCC + 1.0
All other pins not under test = VSS
-10
10
µA
ILO
Output Leakage Current
(Any input)
VSS ≤ VOUT ≤ VCC
/RAS & /CAS at VIH
-10
10
µA
VOL
Output Low Voltage
IOL = 4.2mA
-
0.4
V
VOH
Output High Voltage
IOH = -5.0mA
2.4
-
V
4Mx4,Fast Page DRAM
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HY5117400C,HY5116400C
DC CHARACTERISTICS
(TA = 0°C to 70°C , VCC = 5.0V ± 10%, VSS = 0V, unless otherwise noted.)
Symbol
Parameter
Test condition
Speed
Max. Current
Unit
2K Ref
4K Ref
50
60
70
145
120
100
110
90
80
mA
SL-part
2
1
2
1
mA
ICC1
Operating Current
/RAS, /CAS Cycling
tRC = tRC(min.)
ICC2
TTL Standby
Current
/RAS, /CAS ≥ VIH
Other inputs ≥ VSS
ICC3
/RAS-only Refresh
Current
/RAS Cycling,/CAS = VIH
tRC = tRC(min.)
50
60
70
145
120
100
110
90
80
mA
ICC4
Fast Page Mode
Current
/CAS Cycling, /RAS = VIL
tPC = tPC(min.)
50
60
70
90
80
70
80
70
60
mA
ICC5
CMOS Standby
Current
/RAS = /CAS ≥ VCC - 0.2V
SL-part
1
300
1
300
mA
µA
ICC6
/CAS-before-/RAS
Refresh Current
/RAS & /CAS = 0.2V
tRC = tRC(min.)
50
60
70
145
120
100
110
90
80
mA
ICC7
Battery Back-up
Current (SL-part)
tRC=125µs (2K Ref), 62.5µs (4K Ref)
/CAS = CBR cycling or 0.2V
/OE & /WE = VCC - 0.2V
Address = Vcc-0.2V or 0.2V
DQ0~DQ3 = Vcc-0.2, 0.2V or Open
tRAS ≤
300ns
300
300
ICC8
Self Refresh Current
(SL-part)
tRAS ≤
1µs
/RAS & /CAS = 0.2V
Other pins are same as ICC7
µA
500
500
300
300
µA
Note
1. ICC1, ICC3, ICC4 and ICC6 depend on output loading and cycle rates(tRC and tPC).
2. Specified values are obtained with output unloaded.
3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4,
address can be changed maximum once while /CAS=VIH within one Fast Page mode cycle time tPC.
4. Only /RAS(max.)=1µs is applied to refresh of battery backup but tRAS(max.) = 10 µs is to applied to normal functional
operation.
5. Icc5(max.) = 300 µA, Icc7 and Icc8 are applied to SL-part only.
4Mx4,Fast Page DRAM
Rev.00 / Sep.97
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HY5117400C,HY5116400C
AC CHARACTERISTICS
(TA = 0 °C to 70 °C, VCC = 5.0V ± 10%, VSS = 0V, unless otherwise noted.)
50ns
Symbol
60ns
70ns
Parameter
Unit
Min
Max
Min
Max
Min
Max
Note
tRC
Random read or write cycle time
90
-
110
-
130
-
ns
tRWC
Read-modify-write cycle time
140
-
160
-
180
-
ns
tPC
Fast Page mode cycle time
35
-
40
-
45
-
ns
tPRWC
Fast Page mode read-modify-write cycle time
80
-
85
-
90
-
ns
tRAC
Access time from /RAS
-
50
-
60
-
70
ns
4,5,6
tCAC
Access time from /CAS
-
13
-
15
-
18
ns
4,5
tAA
Access time from column address
-
25
-
30
-
35
ns
4,6
tCPA
Access time from column precharge
-
30
-
35
-
40
ns
4
tCLZ
/CAS to output low impedance
0
-
0
-
0
-
ns
4
tOFF
Output buffer turn-off delay from /CAS
0
10
0
13
0
15
ns
7
tT
Transition time(rise and fall)
3
50
3
50
3
50
ns
2
tRP
/RAS precharge time
30
-
40
-
50
-
ns
tRAS
/RAS pulse width
50
10K
60
10K
70
10K
ns
tRASP
/RAS pulse width(Fast Page cycle)
50
200K
60
200K
70
200K
ns
tRSH
/RAS hold time
13
-
15
-
18
-
ns
tCSH
/CAS hold time
50
-
60
-
70
-
ns
tCAS
/CAS pulse width
13
10K
15
10K
18
10K
ns
tRCD
/RAS to /CAS delay time
18
37
20
45
20
52
ns
5
tRAD
/RAS to column address delay time
10
25
15
30
15
35
ns
6
tCRP
/CAS to /RAS precharge time
5
-
5
-
5
-
ns
10
tCP
/CAS precharge time
8
-
10
-
10
-
ns
tASR
Row address set-up time
0
-
0
-
0
-
ns
tRAH
Row address hold time
8
-
10
-
10
-
ns
tASC
Column address set-up time
0
-
0
-
0
-
ns
tCAH
Column address hold time
10
-
10
-
10
-
ns
tRAL
Column address to /RAS lead time
25
-
30
-
35
-
ns
tRCS
Read command set-up time
0
-
0
-
0
-
ns
tRCH
Read command hold time referenced to /CAS
0
-
0
-
0
-
ns
8
tRRH
Read command hold time referenced to /RAS
0
-
0
-
0
-
ns
8
tWCH
Write command hold time
8
-
10
-
10
-
ns
tWP
Write command pulse width
8
-
10
-
10
-
ns
tRWL
Write command to /RAS lead time
13
-
15
-
18
-
ns
tCWL
Write command to /CAS lead time
13
-
15
-
18
-
ns
4Mx4,Fast Page DRAM
Rev.00 / Sep.97
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HY5117400C,HY5116400C
AC CHARACTERISTICS
Continued
50ns
Symbol
60ns
70ns
Parameter
Min
Max
Min
Max
Min
Max
Unit
Note
tDS
Data-in set-up time
0
-
0
-
0
-
ns
9
tDH
Data-in hold time
10
-
10
-
10
-
ns
9
Refresh period(2048 cycles)
-
32
-
32
-
32
ms
Refresh period(4096 cycles)
-
64
-
64
-
64
ms
Refresh period(SL-part)
-
256
-
256
-
256
ms
tWCS
Write command set-up time
0
-
0
-
0
-
ns
9,10
tCWD
/CAS to /WE delay time
33
-
38
-
43
-
ns
10
tRWD
/RAS to /WE delay time
70
-
83
-
95
-
ns
10
tAWD
Column address to /WE delay time
45
-
53
-
60
-
ns
10
tCSR
/CAS set-up time(CBR cycle)
5
-
5
-
5
-
ns
9
tCHR
/CAS hold time(CBR cycle)
10
-
10
-
10
-
ns
9
tRPC
/RAS to /CAS precharge time
5
-
5
-
5
-
ns
9
tCPT
/CAS precharge time(CBR counter test)
15
-
20
-
25
-
ns
tROH
/RAS hold time referenced to /OE
10
-
10
-
10
-
ns
tOEA
/OE access time
-
13
-
15
-
18
ns
tOED
/OE to data delay Time
13
-
15
-
15
-
ns
tOEZ
Output buffer turn-off delay time from /OE
0
10
0
13
0
15
ns
tOEH
/OE command hold time
10
-
10
-
10
-
ns
tCPWD
/WE delay time from /CAS precharge
30
-
35
-
40
-
ns
tRHCP
/RAS hold time from /CAS precharge
30
-
35
-
40
-
ns
tWRP
/WE to /RAS precharge time(CBR cycle)
10
-
10
-
10
-
ns
tWRH
/WE to /RAS hold time(CBR cycle)
10
-
10
-
10
-
ns
tRASS
/RAS pulse width(self refresh)
100K
-
100K
-
100K
-
ns
tRPS
/RAS Precharge Time (Self refresh)
90
-
110
-
130
-
ns
tCHS
/CAS Hold Time (Self refresh)
-50
-
-50
-
-50
-
ns
tREF
4Mx4,Fast Page DRAM
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HY5117400C,HY5116400C
TEST MODE
50ns
Symbol
60ns
70ns
Parameter
Unit
Min
Max
Min
Max
Min
Max
Note
tRC
Random read or write cycle time
95
-
115
-
135
-
ns
tRWC
Read-modify-write cycle time
145
-
165
-
185
-
ns
tPC
Fast Page mode cycle time
40
-
45
-
50
-
ns
tPRWC
Fast Page mode read-modify-write cycle time
85
-
90
-
95
-
ns
tRAC
Access time from /RAS
-
55
-
65
-
75
ns
4,5,6
tCAC
Access time from /CAS
-
18
-
20
-
23
ns
4,5
tAA
Access time from column address
-
30
-
35
-
40
ns
4,6
tCPA
Access time from /CAS precharge
-
35
-
40
-
45
ns
4
tRAS
/RAS pulse width
55
10K
65
10K
75
10K
ns
tRASP
/RAS pulse width(Fast Page cycle)
55
200K
65
200K
75
200K
ns
tRSH
/RAS hold time
18
-
20
-
23
-
ns
tCSH
/CAS hold time
55
-
65
-
75
-
ns
tCAS
/CAS pulse width
18
10K
20
10K
23
10K
ns
tRAL
Column address to /RAS lead time
30
-
35
-
40
-
ns
tCWD
/CAS to /WE delay time
38
-
43
-
48
-
ns
10
tRWD
/RAS to /WE delay time
75
-
88
-
100
-
ns
10
tAWD
Column address to /WE delay time
50
-
58
-
65
-
ns
10
tOEA
/OE access time
-
18
-
20
-
23
ns
tOED
/OE to data delay Time
18
-
20
-
20
-
ns
tOEH
/OE command hold time
15
-
15
-
15
-
ns
tCPWD
/WE delay time from /CAS precharge
35
-
40
-
45
-
ns
10
In test mode, data are written into 16 sectors (each is composed of 1M bits) in parallel and retrieved the same way.
Column address A0 and A1 are not used. If, upon reading, 4-bit data from 4sectors connected to one DQ pin are equal
(all `1`s or `0`s), the DQ pin indicates a `1`. If they are not equal, the DQ indicates a `0`. The 4Mx4 DRAM can be tested
in the same way as a 1Mx4 DRAM is tested.
/WE (when in /CAS-before-/RAS cycle) puts the 4Mx4 DRAM into Test Mode and a /CAS-before-/RAS or a /RAS-only
refresh cycle put it back into Normal Mode. /WE (when in /CAS-before-/RAS cycle) shall be used for the refresh operation
in the test mode. The test mode function reduces test time(1/4 in case of N test pattern).
4Mx4,Fast Page DRAM
Rev.00 / Sep.97
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HY5117400C,HY5116400C
NOTE
1. An initial pause of 200µs is required after power-up followed by 8 /RAS only refresh cycles before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of
8 /RAS-only refresh cycles are required.
2. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH(min.) and VIL(max.)
3. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
range (TA=0 to 70¡ ÆC) is assured.
4. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 2TTL loads and 100pF.
5. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC.
6. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA.
7. t OFF and t OEZ define the time at which the output achieves the open circuit condition and is not referenced
to output voltage levels.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in
read-modify-write cycles .
10.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open
circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min), and tCPWD ≥
tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither
of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
CAPACITANCE
(TA = 25°C, VCC = 5.0V ± 10%, VSS = 0V and f=1MHz, unless otherwise noted.)
Symbol
Parameter
Typ.
Max
Unit
CIN1
Input Capacitance (A0~A11)
-
5
pF
CIN2
Input Capacitance (/RAS, /CAS, /WE, /OE)
-
7
pF
CDQ
Data Input / Output Capacitance (DQ0~DQ3)
-
7
pF
4Mx4,Fast Page DRAM
Rev.00 / Sep.97
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