Data Sheet PT7C4511 PLL Clock Multiplier ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Features from a lower frequency crystal or clock input. It is designed to replace crystal oscillators in most electronic • Zero ppm multiplication error systems, clock multiplier and frequency translation. • Input crystal frequency of 5 - 30 MHz • Input clock frequency of 4 - 50 MHz Using Phase-Locked-Loop (PLL) techniques, the • Output clock frequencies up to 200 MHz device uses a standard fundamental mode, • Peak to Peak Jitter less than 200ps over 200ns interval inexpensive crystal to produce output clocks up to (100~200MHz) 200 MHz. • Period jitter less than 100ps(70~200MHz) The complex Logic divider is the ability to generate • Duty cycle of 45/55% up to 120 MHz at +3.3V and nine different popular multiplication factors, allowing 150MHz at +5V one chip to output many common frequencies. • 9 selectable frequencies controlled by S0, S1 pins • Operating voltages of 3.0 to 5.5V The device also has an Output Enable pin that tri- • Tri-state output for board level testing states the clock output when the OE pin is taken low. This product is intended for clock generation and General frequency translation with low output jitter (variation The PT7C4511 is a high performance frequency in the output period) multiplier, which integrates Analog Phase Lock Loop Ordering Information techniques. The PT7C4511 is the most cost effective way to Part Number Package PT7C4511W 8 - Pin SOIC generate a high quality, high frequency clock output Block Diagram OE S0 S1 PLL Clock Synthesis and Control Circuit Output Buffer CLK X1/ICLK X2 Crystal Oscillator Output Buffer V CC PT0138(12/03) GND 1 Ver:0 Data Sheet PT7C4511 PLL Clock Multiplier ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Assignment 1 X1/ICLK X2 8 2 Vcc OE 7 3 GND S0 6 4 S1 CLK 5 SOIC-8 package Pin Description Pin Name Type Description 1 X1/ICLK XI Crystal connection or clock input. 2 Vcc P Supply voltage: +3.0V to +5.5V. 3 GND P Connect to ground. 4 S1 TI Multiplier select pin 1. Connect to GND or Vcc or float (no connection). 5 CLK O Clock output per Table below. 6 S0 TI Multiplier select pin 0. Connect to GND or Vcc or float (no connection). 7 OE I 8 X2 XO Output Enable. Tri-states CLK output when low. Internal pull-up. Crystal connection. Leave unconnected for clock input. Clock Output Table S1 0 0 0 M M M 1 1 1 1) 2) S0 0 M 2) 1 0 M 1 0 M 1 CLK ×4 1) ×(16/3) ×5 ×2.5 ×2 ×(10/3) ×6 ×3 ×8 Note: CLK output frequency = ICLK × 4. Note: M = leave unconnected (self-biases to Vcc/2). PT0138(12/03) 2 Ver:0 Data Sheet PT7C4511 PLL Clock Multiplier ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested) Note: Stresses greater than those listed under MAXIStorage temperature ................................................................. -65 to 150OC MUM RATINGS may cause permanent damage to Ambient Operating Temperature ..................................................0 to 70OC the device. This is a stress rating only and funcSupply Voltage to Ground Potential (VCC) ............................. -0.3 to +7.0V tional operation of the device at these or any other Inputs (Referenced to GND) ............................................ -0.5 to Vcc+0.5V conditions above those indicated in the operational Clock Output (Referenced to GND) ................................ -0.5 to Vcc+0.5V sections of this specification is not implied. ExpoSoldering Temperature (Max of 10 seconds) ................................... 260OC sure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operation Conditions Sym. VCC VIH VIL TA Description Supply Voltage H-Level Input Voltage L-Level Input Voltage Operating Temperature Test condition Min 3 2 Typ Max 5.5 Unit V V V °C 0.8 70 0 DC Electrical Characteristics O (VCC = 3.3V± 0.3V, TA= 0~70 C, unless noted) Sym. Parameter Test Condition Pin Min. Vcc 3 Vcc Supply Voltage Icc Supply Current VIH Input Logic High VIL Input Logic Low VIH Input Logic High S0, S1 VIM Input mid-level S0, S1 VIL Input Logic Low S0, S1 VOH High-level output voltage IOH = -12mA CLK VOL Low-level output voltage IOL = 12mA CLK no load, 20MHz crystal Vcc Typ. 12 ICLK (Vcc/2)+1 OE 2 ICLK 3 Unit 5.5 V 20 mA Vcc/2 V V Vcc/2 OE PT0138(12/03) Max. (Vcc/2)-1 V 0.8 V Vcc-0.5 V Vcc/2 V 0.5 2.4 V V 0.4 V Ver:0 Data Sheet PT7C4511 PLL Clock Multiplier ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| AC Electrical Characteristics (VCC = 3.3V± 0.3V, TA= 0~70 C, unless noted) O Sym. Parameter Test Condition Pin Min. fIN Input Frequency crystal ICLK fOUT Output frequency VCC: 4.5 to 5.5V Typ. Max. Unit 5 30 MHz CLK 20 200 MHz VCC: 3.0 to 3.6V CLK 20 180 MHz tr Output clock rise time 0.8 to 2.0V CLK 1 ns tf Output clock fall time 2.0 to 0.8V CLK 1 ns Duty Output clock duty cycle At VCC/2,VCC: 3V, CLK 45 50 55 % up to 120MHz At VCC/2,VCC: 5V, up to 150MHz PLL bandwidth 10 kHz Output enable time OE high to output on 50 ns Output disable time OE low to tri-state 50 ns Period Jitter 70MHz~200MHz CLK 100 ps Jitter over 200ns interval 100MH~200MHz CLK 200 ps Output jitter refer to ICLK 40~150MHz CLK PT0138(12/03) 4 50 100~250 ps Ver:0 Data Sheet PT7C4511 PLL Clock Multiplier ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC pub. no. 95.) 8 Pin SOIC Inches Symbol A A1 B C D E E H H L PT0138(12/03) Min 0.0532 0.0040 0.0130 0.0075 0.1890 0.1497 Millimeters Max 0.0688 0.0098 0.0200 0.0098 0.1968 0.1574 Min 1.35 0.10 0.33 0.19 4.80 3.80 0.2440 0.0195 0.0500 5.80 0.25 0.41 0.50BSC 0.2284 0.0099 0.0160 Max 1.75 0.24 0.51 0.24 5.00 4.00 1.27BSC 5 6.20 0.50 1.27 Ver:0 Data Sheet PT7C4511 PLL Clock Multiplier ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Notes Pericom Technology Inc. Email: [email protected] Web Site: www.pti.com.cn, www.pti-ic.com China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 U.S.A.: 2380 Bering Drive, San Jose, California 95131, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100 Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0138(12/03) 6 Ver:0