PT7C4511 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| PLL Clock Multiplier Features Description Zero ppm multiplication error The PT7C4511 is a high performance frequency Input crystal frequency of 5 - 30 MHz multiplier, which integrates Analog Phase Lock Loop Input clock frequency of 1 - 50 MHz techniques. Output clock frequencies up to 200 MHz The PT7C4511 is the most cost effective way to Peak to Peak Jitter less than 200ps over 200ns generate a high quality, high frequency clock output interval (100~200MHz) from a lower frequency crystal or clock input. It is Low period jitter 50ps (100~200MHz) designed to replace crystal oscillators in most electronic 9 selectable frequencies controlled by S0, S1 pins systems, clock multiplier and frequency translation. Operating voltages of 3.0 to 5.5V Tri-state output for board level testing Lead free SOIC-8 package Using Phase-Locked-Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 200 MHz. The complex Logic divider is the ability to generate nine different popular multiplication factors, allowing one Pin Configuration chip to output many common frequencies. The device also has an Output Enable pin that tri-states 1 X1/ICLK X2 8 the clock output when the OE pin is taken low. This 2 Vcc OE 7 product is intended for clock generation and frequency 3 GND S0 6 4 S1 CLK 5 translation with low output jitter (variation in the output period). SOIC-8 package Pin Description Name X1/ICLK Vcc Pin No. 1 2 Type X1 P Description Crystal connection or clock input. Connect to +3.3V or +5V. GND 3 P S1 4 T1 CLK 5 O S0 6 T1 OE 7 I X2 8 XO Connect to ground. Multiplier select pin, connect to GND or Vcc or floating (no connection). Clock output per Table below. Multiplier select pin 0, connect to GND or Vcc or floating (no connection). Output enable, tri-state CLK output when low. Internal pull-up. Crystal connection. Leave unconnected for clock input. 2014-08-0004 Clock Output Table S1 S0 CLK 0 0 ×4 0 M ×(16/3) 0 1 ×5 M 0 ×2.5 M M ×2 M 1 ×(10/3) 1 0 ×6 1 M ×3 1 1 ×8 1) Note: CLK output frequency=ICLK×4. 2) Note: M=Leave unconnected (self-biases to Vcc/2). PT0138-5 1 08/14/14 PT7C4511 PLL Clock Multiplier ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Block Diagram OE S0 PLL Clock Synthesis and Control Circuit S1 Output Buffer CLK X1/ICLK X2 Crystal Oscillator VCC GND External Components pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors, if needed, must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal CL*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 15 pF load capacitance, each crystal capacitor would be 30pF. Decoupling Capacitor As with any high-performance mixed-signal IC, the PT7C4511 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01μF or 0.1uF must be connected between VCC and the GND. It must be connected close to the PT7C4511 to minimize lead inductance. No external power supply filtering is required for the PT7C4511. Series Termination Resistor A 33Ω terminating resistor can be used next to the CLK pin for trace lengths over one inch. Crystal Load Capacitors There is no on-chip capacitance build-in chip. A parallel resonant, fundamental mode crystal should be used. The device crystal connections should include Maximum Ratings Storage Temperature..................................................................................... - 65oC to +150oC Ambient Operating Temperature...................................................................-40oC to +85oC Supply Voltage to Ground Potential (VCC)................................................... - 0.3V to +7.0V Inputs(Referenced to GND) ............................................. -0.5V to VCC +0.5V Clock Output(Referenced to GND)................................ -0.5V to VCC +0.5V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Sym Parameter Conditions Min Typ Max Unit VCC Supply voltage - 3.0 - 5.5 V TA Operating temperature - -40 - +85 °C 2014-08-0004 PT0138-5 2 08/14/14 PT7C4511 PLL Clock Multiplier ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| DC Electrical Characteristics (VCC = 3.3V±0.3V, TA = -40 ~ 85ºC, unless otherwise noted) Sym. Parameter Test Condition Pin Min. Typ. Max. Unit Vcc Supply Voltage - Vcc 3 3.3 3.6 V Icc Supply Current no load, 20MHz crystal,100MHz output Vcc - 12 20 mA ICLK (Vcc/2)+1 Vcc/2 - V VIH Input Logic High OE 2 - - V ICLK - Vcc/2 (Vcc/2)1 V OE - - 0.8 V VIL Input Logic Low - VIH Input Logic High - S0, S1 Vcc-0.5 - - V VIM Input mid-level - S0, S1 - Vcc/2 - V VIL Input Logic Low - S0, S1 - - 0.5 V VOH High-level output voltage IOH = -12mA CLK 2.4 - - V VOL Low-level output voltage IOL = 12mA CLK - - 0.4 V R Internal pull up resistance - OE - 270 - k IS Short Circuit Current - CLK - 30 - mA Pin Min. Typ. Max. Unit (VCC = 5.0V±0.5V, TA = -40 ~ 85ºC, unless otherwise noted) Sym. Parameter Test Condition Vcc Supply Voltage - Vcc 4.5 5.0 5.5 V Icc Supply Current no load, 20MHz crystal,100MHz output Vcc - 20 30 mA ICLK (Vcc/2)+1 Vcc/2 - V VIH Input Logic High OE 0.65*Vcc - - V V VIL Input Logic Low ICLK - Vcc/2 (Vcc/2)1 OE - - 0.8 V - VIH Input Logic High - S0, S1 Vcc-0.4 - - V VIM Input mid-level - S0, S1 - Vcc/2 - V VIL Input Logic Low - S0, S1 - - 0.4 V VOH High-level output voltage IOH = -12mA CLK Vcc-0.5 - - V VOL Low-level output voltage IOL = 12mA CLK - - 0.4 V R Internal pull up resistance - OE - 270 - k IS Short Circuit Current - CLK - 70 - mA 2014-08-0004 PT0138-5 3 08/14/14 PT7C4511 PLL Clock Multiplier ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| AC Electrical Characteristics (VCC = 3.3V±0.3V, TA = -40 ~ 85ºC, unless otherwise noted) Sym. fIN Parameter Test Condition Pin Min. Typ. Max. Unit Input Frequency - ICLK 1 - 50 MHz Output Frequency VCC: 3.0 to 3.6V CLK 20 - 180 MHz tR Output clock rise time 0.8 to 2.0V, 15pF load CLK - 1 - ns tF Output clock fall time 2.0 to 0.8V, 15pF load CLK - 1 - ns At VCC /2, below 160MHz CLK 45 50 55 % At VCC /2, 160MHz to 180MHz CLK 40 - 60 % fOUT Duty Output clock duty cycle PLL bandwidth - - 10 - - kHz Output enable time OE high to output on - - - 50 ns Output disable time OE low to tri-rise - - - 50 ns Period Jitter 70MHz~180MHz CLK - 50 100 ps Jitter over 200ns interval 100MHz~180MHz CLK - - 200 ps Pin Min. Typ. Max. Unit (VCC = 5.0V±0.5V, TA = -40 ~ 85ºC, unless otherwise noted) Sym. fIN fOUT Parameter Input Frequency - ICLK 1 - 50 MHz Output Frequency VCC: 4.5 to 5.5V CLK 20 - 200 MHz CLK - 1.2 - ns CLK - 1.2 - ns At VCC /2, below 160MHz CLK 45 50 55 % At VCC /2, 160MHz to 200MHz CLK 40 60 % tR Output clock rise time tF Output clock fall time Duty Test Condition Output clock duty cycle 20%Vcc to 80%Vcc, 15pF load 80%Vcc to 20%Vcc, 15pF load PLL bandwidth - - 10 - - kHz Output enable time OE high to output on - - - 50 ns Output disable time OE low to tri-rise - - - 50 ns Period Jitter 70MHz~200MHz CLK - 50 100 ps Jitter over 200ns interval 100MHz~200MHz CLK - - 200 ps Test circuits 1>Load circuit for output clock duty cycle, rise and fall time Measurement 33om From Output Under Test 15pF 2>Timing Definitions for output clock rise and fall time Measurement 2014-08-0004 PT0138-5 4 08/14/14 PT7C4511 PLL Clock Multiplier ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Mechanical Information SOIC-8 Symbol A A1 A2 b c D E E1 e L θ Note: 1) Controlling dimensions in millimeters. 2) Ref : JEDEC MS-012E/AA Dimensions In Millimeters Min Max 1.350 1.750 0.100 0.250 1.350 1.550 0.330 0.510 0.170 0.250 4.700 5.100 3.800 4.000 5.800 6.200 1.27 BSC 0.400 1.270 0° 8° Ordering Information Part No. Package Code Package PT7C4511WE W Lead free and Green 8-pin SOIC Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom. 2014-08-0004 PT0138-5 5 08/14/14