R1W V3216R Series REJ03C0215-0100Z Rev.1.00 2004.4.13 32Mb superSRAM (2M wordx16bit) Description The R1WV3216R Series is a family of low voltage 32-Mbit static RAMs organized as 2097152-words by 16-bit, fabricated by Renesas's high-performance 0.15um CMOS and TFT technologies. The R1WV3216R Series is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. The R1WV3216R Series is made by stacked-micro-package technology and two chips of 16Mbit superSRAMs are assembled in one package. The R1WV3216R Series is packaged in a 52pin micro thin small outline mount device[µTSOP / 10.79mm x 10.49mm with the pin-pitch of 0.4mm] or a 48balls fine pitch ball grid array [f-BGA / 7.5mmx8.5mm with the ball-pitch of 0.75mm and 6x8 array] . It gives the best solution for a compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards. Features • Single 2.7-3.6V power supply • Small stand-by current:4µA (3.0V, typ.) • Data retention supply voltage =2.0V • No clocks, No refresh • All inputs and outputs are TTL compatible. • Easy memory expansion by CS1#, CS2, LB# and UB# • Common Data I/O • Three-state outputs: OR-tie capability • OE# prevents data contention on the I/O bus • Process technology: 0.15um CMOS Rev.1.00 2004.4.13 page 1 of 16 R1W V3216R Series Ordering Information Type No. Access time Package R1WV3216RSD-7S% 70 ns R1WV3216RSD-8S% 85 ns 350-mil 52-pin plastic µ - TSOP(II) (normal-bend type) (52PTG) R1WV3216RBG-7S% 70 ns R1WV3216RBG-8S% 85 ns 7.5mmx8.5mm f-BGA 0.75mm pitch 48ball % - Temperature version; see table below Rev.1.00 2004.4.13 % Temperature Range R 0 ~ +70 ºC W -20 ~ +85 ºC I -40 ~ +85 ºC page 2 of 16 R1W V3216R Series Pin Arrangement 52-pin µTSOP 48-pin fBGA A15 1 52 A16 A14 2 51 BYTE# A13 3 50 UB# A12 4 49 A11 5 48 Vss LB# A10 6 47 DQ15 A9 7 46 DQ7 A8 8 45 DQ14 A19 9 44 DQ6 CS1# 10 43 DQ13 WE# 11 42 DQ5 NC 12 41 DQ12 NC 13 40 DQ4 Vcc 14 39 NC CS2 15 38 DQ11 NC 16 37 DQ3 A20 17 36 DQ10 A18 18 35 DQ2 A17 19 34 A7 20 33 DQ9 DQ1 A6 21 32 DQ8 A5 22 31 DQ0 A4 23 30 OE# A3 24 29 A2 25 28 Vss NC 26 27 A0 A1 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CS2 B DQ15 UB# A3 A4 CS1# DQ0 C DQ13 DQ14 A5 A6 DQ1 DQ2 D Vss DQ12 A17 A7 DQ3 Vcc E Vcc DQ11 Vss or NC A16 DQ4 Vss F DQ10 DQ9 A14 A15 DQ6 DQ5 G DQ8 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 Pin Description Pin name Function A0 to A20 Address input DQ 0 to DQ15 Data input/output CS1# &CS2 Chip select WE# Write enable OE# Output enable LB# Lower byte select UB# Upper byte select Vcc Power supply Vss Ground BYTE# Byte (x8 mode) enable input NC Non connection Rev.1.00 2004.4.13 page 3 of 16 R1W V3216R Series LB# x8/x16 SWITCHING CIRCUIT UB# OUTPUT BUFFER DATA SELECTOR OUTPUT BUFFER DQ8 BYTE# WE# OE# 16Mb superSRAM #1 16Mb superSRAM #2 Note: BYTE# pin supported by only TSOP type. Rev.1.00 2004.4.13 page 4 of 16 DATA INPUT BUFFER CS1# DQ7 DATA INPUT BUFFER CLOCK GENERATOR DQ0 DATA SELECTOR CS2 1048576 Words x 16BITS OR 2097152 Words x 8BITS SENSE Amp. A20 Memory Array DECODER ADDRESS BUFFER A0 SENSE Amp. Block Diagram DQ15 / A-1 Vcc Vss R1W V3216R Series Operating Table CS1# CS2 BYTE# LB# UB# WE# OE# DQ0-7 DQ8-14 DQ15 Operation H X X X X X X High-Z High-Z High-Z Stand by X L X X X X X High-Z High-Z High-Z Stand by X X H H H X X High-Z High-Z High-Z Stand by L H H L H L X Din High-Z High-Z Write in lower byte L H H L H H L Dout High-Z High-Z Read from lower byte L H X X X H H High-Z High-Z High-Z Output disable L H H H L L X High-Z Din Din Write in upper byte L H H H L H L High-Z Dout Dout Read from upper byte L H H L L L X Din Din Din Write L H H L L H L Dout Dout Dout Read L H L L L L X Din High-Z A-1 Write L H L L L H L Dout High-Z A-1 Read Note 1. H:VIH L:VIL X: VIH or VIL 2. BYTE# pin supported by only TSOP type. When apply BYTE# =“L” , please assign LB#=UB#=“L”. Absolute Maximum Ratings Parameter Symbol Value Unit Power supply voltage relative to Vss Vcc -0.5 to +4.6 V Terminal voltage on any pin relation toVss VT -0.5*1 to Vcc+0.3*2 V Power dissipation PT 0.7 W Operation temperature Storage temperature Note 1: -2.0V in case of AC (Pulse width ≤ 30ns) 2:Maximum voltage is +4.6V 2004.4.13 0 to +70 ºC W ver. -20 to +85 ºC I ver. -40 to +85 ºC Tstg Storage temperature range under bias Rev.1.00 Topr R ver. page 5 of 16 Tbias -65 to +150 ºC R ver. 0 to +70 ºC W ver. -20 to +85 ºC I ver. -40 to +85 ºC R1W V3216R Series Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Vcc 2.7 3.0 3.6 V Vss 0 0 0 V Input high voltage VIH 2.4 - Vcc+0.2 V Input low voltage VIL -0.2 - 0.4 V 1 0 - +70 ºC 2 -20 - +85 ºC 2 -40 - +85 ºC 2 Supply voltage R ver. Ambient temperature range W ver. Ta I ver. Note Note 1. –2.0V in case of AC (Pulse width ≤ 30ns) 2. Ambient temperature range depends on R/W/I-version. Please see table on page 2. DC Characteristics Test conditions*2 Symbol Min. Typ.*1 Max. Unit Input leakage current |ILI| - - 1 µA Vin=Vss to Vcc Output leakage current |ILo| - - 1 µA CS1# =VIH or CS2=VIL or OE# = VIH or WE# =VIL or LB# =UB# =VIH,VI/O=Vss to Vcc Icc1 - 60 70 mA Icc2 - 20 25 mA - 15 20 mA - 0.1 0.3 mA CS2=VIL - 4 12 µA ~+25ºC - 7 24 µA ~+40ºC - - 50 µA ~+70ºC - - 80 µA ~+85ºC Parameter Average operating current Write Icc2 Read Standby current Standby current ISB Min. cycle, duty =100% I I/O = 0 mA, CS1# =VIL, CS2=VIH Others = VIH / VIL Cycle time = 1 µs, I I/O = 0 mA, CS1#≤ 0.2V, CS2 ≥ VCC-0.2V VIH ≥ VCC-0.2V , VIL ≤ 0.2V, Write & Read duty=100% respectively ISB1 V in ≥ 0V (1) 0V≤CS2≤0.2V or (2) CS2≥Vcc-0.2V, CS1# ≥Vcc-0.2V or (3)LB# =UB# ≥Vcc-0.2V, CS2≥Vcc-0.2V, CS1# ≤0.2V Average value Output hige voltage VOH 2.4 - - V IOH = -1mA Output Low voltage VOL - - 0.4 V IOL = 2mA Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. BYTE# pin supported by only TSOP type. BYTE# ≥ Vcc-0.2V or BYTE# ≤ 0.2V Rev.1.00 2004.4.13 page 6 of 16 R1W V3216R Series Capacitance (Ta = +25ºC, f =1MHz) Parameter Symbol Min. Typ. Max. Unit Test conditions Note Input capacitance C in - - 20 pF V in = 0V 1 Input / output capacitance C I/O - - 20 pF V I/O = 0V 1 Note 1. This parameter is sampled and not 100% tested. AC Characteristics Test Conditions (Vcc=2.7~3.6V, Ta = 0~+70ºC / -20~+85ºC / -40~+85ºC *) • Input pulse levels: VIL= 0.4V,VIH=2.4V • Input rise and fall time : 5ns • Input and output timing reference levels : 1.4V • Output load : See figures (Including scope and jig) 1.4V RL=500Ω DQ CL=30pF Note: Temperature range depends on R/W/I-version. Please see table on page 2. Rev.1.00 2004.4.13 page 7 of 16 R1W V3216R Series Read Cycle Parameter Symbol Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB#,UB# access time Chip select to output in low-Z LB#,UB# enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB#,UB# disable to high-Z Output disable to output in high-Z Rev.1.00 2004.4.13 page 8 of 16 R1WV3216R**-7S Min. Max. R1WV3216R**-8S Min. Max. Unit Notes tRC tAA 70 - 85 - ns - 70 - 85 ns tACS1 tACS2 tOE tOH tBA tCLZ tBLZ tOLZ tCHZ1 tCHZ2 tBHZ tOHZ - 70 - 85 ns - 70 - 85 ns - 35 - 45 ns 10 - 10 - ns - 70 - 85 ns 10 - 10 - ns 2,3 5 - 5 - ns 2,3 5 - 5 - ns 2,3 0 25 0 30 ns 1,2,3 0 25 0 30 ns 1,2,3 0 25 0 30 ns 1,2,3 0 25 0 30 ns 1,2,3 R1W V3216R Series Write Cycle Parameter Symbol Write cycle time Address valid to end of write Chip selection to end of write Write pulse width LB#,UB# valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Write to output in high-Z tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ R1WV3216R**-7S Min. Max. R1WV3216R**-8S Min. Max. Unit Notes 70 - 85 - ns 65 - 70 - ns 65 - 70 - ns 5 55 - 60 - ns 4 65 - 70 - ns 0 - 0 - ns 6 0 - 0 - ns 7 35 - 40 - ns 0 - 0 - ns 5 - 5 - ns 2 0 25 0 30 ns 1,2 0 25 0 30 ns 1,2 Note 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. AT any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and form device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low . A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. Rev.1.00 2004.4.13 page 9 of 16 R1W V3216R Series Byte enable (supported by only 52-pin µTSOP ) Parameter Symbol tBS tBR Byte setup time Byte recovery time R1WV3216R**-7S Min. Max. - 5 - ms 5 - 5 - ms CS2 CS1# BYTE# Rev.1.00 2004.4.13 page 10 of 16 Unit 5 BYTE# Timing Waveform tBS R1WV3216R**-8S Min. Max. tBR Notes R1W V3216R Series Timing Waveform Read Cycle tRC A 0~20 (Word Mode) Valid address A -1~20 tAA tBA (Byte Mode) tOH LB#,UB# tBHZ tACS1 CS1# tCHZ1 tACS2 CS2 tCHZ2 tOE OE# tOLZ WE# = "H" level tCLZ tBLZ DQ0~15 (Word Mode) DQ0~7 (Byte Mode) Rev.1.00 2004.4.13 page 11 of 16 tOHZ Valid data R1W V3216R Series Write Cycle (1) (WE# Clock) tWC A 0~20 (Word Mode) Valid address A -1~20 (Byte Mode) tBW LB#,UB# tCW CS1# tCW CS2 tAW tAS tWR tWP tWHZ WE# tOW tDW DQ0~15 (Word Mode) Valid data DQ0~7 (Byte Mode) Rev.1.00 tDH 2004.4.13 page 12 of 16 R1W V3216R Series Write Cycle (2) (CS1# ,CS2 Clock, OE#=VIH) tWC A 0~20 (Word Mode) Valid address A -1~20 (Byte Mode) tBW LB#,UB# CS1# tAS tCW tWR tCW CS2 tWP WE# tDW DQ0~15 tDH (Word Mode) Valid data DQ0~7 (Byte Mode) Rev.1.00 2004.4.13 page 13 of 16 R1W V3216R Series Write Cycle (3) ( LB#,UB#Clock, OE#=VIH) tWC A 0~20 (Word Mode) Valid address A -1~20 tAS (Byte Mode) tBW tWR LB#,UB# tCW CS1# tCW CS2 WE# tWP tDW DQ0~15 tDH (Word Mode) Valid data DQ0~7 (Byte Mode) Rev.1.00 2004.4.13 page 14 of 16 R1W V3216R Series Data Retention Characteristics Parameter Symbol VDR Vcc for data retention MIn. Typ.*1 Max. Test conditions*2,3 Unit V in ≥ 0V (1) 0V ≤ CS2 ≤ 0.2V or (2) CS2 ≥ Vcc-0.2V, CS1# ≥ Vcc-0.2V or (3) LB# =UB# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V, CS1# ≤ 0.2V 2.0 - 3.6 V - 4 12 µA ~+25ºC Vcc=3.0V,Vin≥0V - 7 24 µA ~+40ºC (2) CS2 ≥ Vcc-0.2V, - - 50 µA ~+70ºC - - 80 µA ~+85ºC 0 - - ns 5 - - ms (1) 0V ≤ CS2 ≤ 0.2V or IccDR Data retention current Chip deselect to data retention time Operation recovery time tCDR tR CS1# ≥ Vcc-0.2V or (3) LB# =UB# ≥Vcc-0.2V, CS2 ≥ Vcc-0.2V, CS1# ≤ 0.2V Average value See retention waveform Note 1.Typical parameter of IccDR indicates the value for the center of distribution at Vcc=3.0V and not 100% tested. 2. BYTE# pin supported by TSOP type. BYTE# ≥ Vcc-0.2V or BYTE# ≤ 0.2V 3. Also CS2 controls address buffer, WE# buffer ,CS1# buffer ,OE# buffer ,LB# ,UB# buffer and Din buffer .If CS2 controls data retention mode,Vin levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state. Data Retention timing Waveform (1) (LB#,UB# Controlled) Vcc tCDR 2.70V tR 2.4V 2.4V LB# =UB# ≥ Vcc-0.2V LB# UB# Data Retention timing Waveform (2) (CS1# Controlled) Vcc tCDR 2.70V tR 2.4V 2.4V CS1# ≥ Vcc-0.2V CS1# Data Retention timing Waveform (3) (CS2 Controlled) Vcc tCDR CS2 2.70V 0.2V 0.2V 0V ≤ CS2 ≤ 0.2V Rev.1.00 2004.4.13 page 15 of 16 tR R1W V3216R Series Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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