ETC R8C/13

R8C/13 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0069-0010Z
Rev.0.10
2003.10.28
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU
core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions
featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing
instructions at high speed.
The data flash ROM (2 KB X 2 blocks) is embedded.
1.1 Applications
Electric household appliance, office equipment, housing equipment (sensor, security), general industrial
equipment, audio, etc.
Rev.0.10
Oct 28, 2003
page 1 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
1. Overview
1.2 Performance Outline
Table 1.1. lists the performance outline of this MCU.
Table 1.1 Performance outline
Item
Performance
CPU
Number of basic instructions 89 instructions
Shortest instruction execution time 50 ns (f(XIN) = 20 MHZ, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V)
Operating mode
Single-chip
Address space
1M bytes
Memory capacity
See Table 1.2.
Peripheral
Interrupt
Internal: 10 sources, External: 5 sources,
function
Software: 4 sources, Priority level: 7 levels
Watchdog timer
15 bits x 1 (with prescaler)
Reset start function selectable
Timer
Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel,
Timer Z: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits x 1 channel
Circuits of input capture and output compare.
Serial I/O
•1 channel
Clock synchronous, UART
•1 channel
UART
A-D converter
10-bit A-D converter: 1 circuit, 12 channels
Clock generation circuit
2 circuits
•Main clock generation circuit (Equipped with a built-in
feedback resistor)
•Ring oscillator (high speed, low speed)
On High-speed ring oscillator the frequency adjustment
function is usable.
Oscillation stop detection function Stop detection of main clock oscillation
Voltage detection circuit
Included
Power on reset circuit
Included
Port
Input/Output: 22 (including LED drive port), Input: 2
(LED drive I/O port: 8, max. 20 mA)
Electrical
Power supply voltage
VCC = 3.0 to 5.5 V (f(XIN) = 20 MHZ)
characteristics
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ)
Power consumption
Typ. 9 mA (VCC = 5.0 V, (f(XIN) = 20 MHZ, High-speed mode)
Typ. 5 mA (VCC = 3.0 V, (f(XIN) = 10 MHZ, High-speed mode)
TBD (VCC = 3.0 V, Wait mode)
Typ. 0.7 µA (VCC = 3.0 V, Stop mode)
Flash memory Program/erase voltage
VCC = 2.7 to 5.5 V
Number of program/erase
10000 times (Data area)
100 times (Program area)
Operating ambient temperature
-20 to 85 °C
-40 to 85 °C (option)
Package
32-pin plastic mold LQFP
Option: If you require this option, please specify so.
Rev.0.10
Oct 28, 2003
page 2 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
1. Overview
1.3 Block Diagram
Figure 1.1 shows this MCU block diagram.
8
8
I/O port
Port P0
Port P1
1
5
Port P3
2
Port P4
Peripheral functions
Timer
Timer X (8 bits)
Timer Y (8 bits)
Timer Z (8 bits)
Timer C (16 bits)
A-D converter
(10 bits ✕ 12 channels)
System clock generator
UART or Clock synchronous
serial I/O
(8 bits ✕ 1 channel)
XIN-XOUT
High-speed ring oscillator
Low-speed ring oscillator
UART
(8 bits ✕ 1 channel)
Memory
R8C Series CPU core
Watchdog timer
(15 bits)
R0H
R1H
R0L
R1L
R2
R3
SB
USP
ISP
INTB
A0
A1
FB
ROM
(Note 1)
RAM
(Note 2)
PC
FLG
Multiplier
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Figure 1.1 Block Diagram
Rev.0.10
Oct 28, 2003
page 3 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
1. Overview
1.4 Product Information
Table 1.2 lists the products.
Table 1.2 Product List
As of October 2003
ROM capacity
Type No.
**
R5F21133FP
**
R5F21134FP
**
R5F21132DFP
**
R5F21133DFP
**
R5F21134DFP
**
: Under development
**
R5F21132FP
Type No. R 5 F
Program area
Data area
RAM capacity
Package type
8K bytes
2K bytes x 2
512 bytes
32P6U-A
12K bytes
2K bytes x 2
768 bytes
32P6U-A
16K bytes
2K bytes x 2
1K bytes
32P6U-A
8K bytes
2K bytes x 2
512 bytes
32P6U-A
12K bytes
2K bytes x 2
768 bytes
32P6U-A
16K bytes
2K bytes x 2
1K bytes
32P6U-A
Remarks
Flash memory version
D version
21 13 4 D FP
Package type:
FP : 32P6U
Shows characteristics and others.
D: Operating ambient temperature –40 °C to 85 °C
No symbol: Operating ambient temperature –20 °C to 85 °C
ROM capacity:
2 : 8 KBytes.
3 : 12 KBytes.
4 : 16 KBytes.
R8C/13 group
R8C/Tiny series
Memory type:
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.2 Type No., Memory Size, and Package
Rev.0.10
Oct 28, 2003
page 4 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
1. Overview
1.5 Pin Assignments
Figure 1.3 shows the pin configuration (top view).
P30/CNTR0/CMP10
AVSS
P31/TZOUT/CMP11
AVCC/VREF
P32/INT2/CNTR1/CMP12
P33/INT3/ TCIN
P07/AN0
IVCC
PIN CONFIGURATION (top view)
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
P06/AN1
P05/AN2
P04/AN3
MODE
P03/AN4
P02/AN5
P01/AN6
P00/AN7/TxD11
R8C/13 Group
16
15
14
13
12
11
10
9
P45/INT0
P10/KI0/AN8/CMP00
P11/KI1/AN9/CMP01
P12/KI2/AN10/CMP02
P13/KI3/AN11
P14/TxD0
P15/RxD0
P16/CLK0
RESET
XOUT/P47 (Note 1)
VSS
XIN/P46
VC C
P17/INT1/CNTR0
P37/TxD10/RxD1
CNVSS
1 2 3 4 5 6 7 8
Notes:
1. P47 functions only as an input port.
2. When using On-chip debugger, do not use pins P00/AN7/TxD11
and P37/TxD10/RxD1.
Package: 32P6U-A
Figure 1.3 Pin Configuration (Top View)
Rev.0.10
Oct 28, 2003
page 5 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
1. Overview
1.6 Pin Description
Table 1.3 shows the pin description
Table 1.3 Pin description
Signal name
Power supply
input
IVcc
Analog power
supply input
Pin name
Vcc,
Vss
IVcc
AVcc, AVss
Reset input
CNVss
MODE
Main clock input
RESET
CNVss
MODE
XIN
I/O type
Input
INT interrupt input INT
0 to_____
INT3
_____
Key input interrupt KI0 to KI3
input
Timer X
CNTR
0
__________
CNTR0
Timer Y
CNTR1
Timer Z
TZOUT
Timer C
TCIN
CMP00 to CMP03,
CMP10 to CMP13
Serial interface
CLK0
RxD0, RxD1
TxD0, TxD10,
TxD11
Reference voltage VREF
input
A-D converter
AN0 to AN11
I/O port
P00 to P07,
P10 to P17,
P30 to P33, P37,
P45
Input
Input
Function
Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the
Vss pin.
Connect this pin to Vss via a capacitor.
These are power supply input pins for A-D converter.
Connect the AVss pin to Vss. Connect a capacitor
between pins AVcc and AVss.
“L” on this input resets the MCU.
Connect this pin to Vss via a resistor.
Connect this pin to Vcc via a resistor.
These pins are provided for the main clock generating circuit input/output. Connect a ceramic resonator
or a crystal oscillator between the XIN and XOUT pins.
To use an externally derived clock, input it to the XIN
pin and leave
the XOUT pin open.
______
These are INT interrupt input pins.
These are key input interrupt input pins.
Input/Output
Output
Input/Output
Output
Input
Output
This is the timer X I/O pin.
This is the timer X output pin.
This is the timer Y I/O pin.
This is the timer Z output pin.
This is the timer C input pin.
These are the timer C output pins.
Input/Output
Input
Output
This is a transfer clock I/O pin.
These are serial data input pins.
These are serial data output pins.
Input
Input port
Input
This is a reference voltage input pin for A-D converter.
These are analog input pins for A-D converter.
These are 8-bit CMOS I/O ports. Each port has an
input/output select direction register, allowing each
pin in that port to be directed for input or output individually.
Any port set to input can select whether to use a pullup resistor or not by program.
P10 to P17 also function as LED drive ports.
These are input only pins.
Output
Input
___________
Input
Input
Input
Input
Main clock output XOUT
_____
Rev.0.10
_______
Oct 28, 2003
Output
_______
P46, P47
page 6 of 26
Input
Input/Output
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
b15
b8 b7
b0
R2
R0H(R0's high bits) R0L(R0's low bits)
R3
R1H(R1's high bits) R1L(R1's low bits)
R2
Data registers (Note 1)
R3
A0
Address registers (Note 1)
A1
FB
b19
b15
Frame base registers (Note 1)
b0
INTBH
Interrupt table register
INTBL
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
PC
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
AA
AAAAAA
AA
AA
AA
AA
AA
AA
AA
AA
AAAAAA
AAAAAAAAAAAA
AA
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note 1: These registers comprise a register bank. There are two register banks.
Figure 2.1 Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32bit data register (R2R0). R3R1 is the same as R2R0.
Rev.0.10 Oct 28, 2003
page 7 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
2. Central Processing Unit (CPU)
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
Rev.0.10
Oct 28, 2003
page 8 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
3. Memory
3. Memory
Figure 3.1 is a memory map of this MCU. The address space extends the 1M bytes from address 0000016
to FFFFF16.
The internal ROM (program area) is allocated in a lower address direction beginning with address 0FFFF16.
For example, a 16-Kbyte internal ROM is allocated to the addresses from 0C00016 to 0FFFF16.
The fixed interrupt vector table is allocated to the addresses from 0FFDC16 to 0FFFF16. Therefore, store
the start address of each interrupt routine here.
The internal ROM (data area) is allocated to the addresses from 0200016 to 02FFF16.
The internal RAM is allocated in an upper address direction beginning with address 0040016. For example,
a 1-Kbyte internal RAM is allocated to the addresses from 0040016 to 007FF16. In addition to storing data,
the internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
Special function registers (SFR) are allocated to the addresses from 0000016 to 002FF16. Peripheral function control registers are located here. Of the SFR, any space which has no functions allocated is reserved
for future use and cannot be used by users.
0000016
SFR
(See Chapter 4 for details.)
002FF16
0040016
Internal RAM
0XXXX16
0200016
Internal ROM
(data area)1
0FFDC16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
02FFF16
Watchdog timer,Oscillation stop detection,Voltage detection
0YYYY16
Internal ROM
(program area)
(Reserved)
(Reserved)
Reset
0FFFF16
0FFFF16
Expanding area
FFFFF16
Note1 The data flash ROM block A (2K bytes) and block B (2K bytes) are shown.
Type name
Internal RAM
Address 0XXXX16
Size
R5F21134FP, R5F21134DFP
16K bytes
0C00016
1K bytes
007FF16
R5F21133FP, R5F21133DFP
12K bytes
0D00016
768 bytes
006FF16
R5F21132FP, R5F21132DFP
8K bytes
0E00016
512 bytes
005FF16
Figure 3.1 Memory Map
Rev.0.10
Internal ROM
Address 0YYYY16
Size
Oct 28, 2003
page 9 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
4. Special Function Register (SFR)
4. Special Function Register (SFR)
Register
Address
Symbol
After reset
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
Processor mode register 0 1
Processor mode register 1
System clock control register 0
System clock control register 1
High-speed ring control register 0
Address match interrupt enable register
Protect register
High-speed ring control register 1
Oscillation stop detection register
Watchdog timer reset register
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
PM0
PM1
CM0
CM1
HR0
AIER
PRCR
HR1
OCD
WDTR
WDTS
WDC
RMAD0
0016
0016
011010002
001000002
0016
XXXXXX002
00XXX0002
4016
000001002
XX16
XX16
000XXXXX2
0016
0016
X016
Address match interrupt register 1
RMAD1
0016
0016
X016
Voltage detection register 1 2
Voltage detection register 2 2
VCR1
VCR2
0016
1000000016
INT0 input filter select register
Voltage detection interrupt register 2
INT0F
D4INT
XXXXX0002
0016 3
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
X : Undefined
Blank columns are all reserved space. No access is allowed.
Notes:
1. Software reset or the watchdog timer reset does not affect bits 0 to 1 of PM0 register.
2. Software reset or the watchdog timer reset does not affect this register.
3. Owing to Reset input.
4. In the case of RESET pin = “H” retaining.
Rev.0.10
Oct 28, 2003
page 10 of 26
010000012 4
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
4. Special Function Register (SFR)
Register
Symbol
After reset
Key input interrupt control register
A-D conversion interrupt control register
KUPIC
ADIC
XXXXX0002
XXXXX0002
Compare 1 interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
CMP1IC
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TXIC
TYIC
TZIC
INT1IC
INT3IC
TCIC
CMP0IC
INT0IC
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XX00X0002
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
INT2 interrupt control register
Timer X interrupt control register
Timer Y interrupt control register
Timer Z interrupt control register
INT1 interrupt control register
INT3 interrupt control register
Timer C interrupt control register
005C16
Compare 0 interrupt control register
005D16
INT0 interrupt control register
005E16
005F16
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
X : Undefined
Blank columns are all reserved space. No access is allowed.
Rev.0.10
Oct 28, 2003 page 11 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
4. Special Function Register (SFR)
Register
Address
Symbol
After reset
Timer Y, Z mode register
Prescaler Y
Timer Y secondary
Timer Y primary
Timer Y, Z waveform output control register
Prescaler Z
Timer Z secondary
Timer Z primary
TYZMR
PREY
TYSC
TYPR
PUM
PREZ
TZSC
TZPR
0016
FF16
FF16
FF16
0016
FF16
FF16
FF16
Timer Y, Z output control register
Timer X mode register
Prescaler X
Timer X register
Count source set register
TYZOC
TXMR
PREX
TX
TCSS
0016
0016
FF16
FF16
0016
Timer C register
TC
0016
0016
External input enable register
INTEN
0016
Key input enable register
KIEN
0016
Timer C control register 0
Timer C control register 1
Capture, compare 0 register
TCC0
TCC1
TM0
009E16
Compare 1 register
TM1
009F16
00A016
UART0 transmit/receive mode register
U0MR
U0BRG
U0TB
0016
0016
XX16
XX16
XX16
XX16
0016
XX16
XX16
XX16
000010002
000000102
XX16
XX16
0016
XX16
XX16
XX16
000010002
000000102
XX16
XX16
0016
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
009B16
009C16
009D16
00A116
00A216
UART0 bit rate generator
UART0 transmit buffer register
00A316
00A416
00A516
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
00A616
UART0 receive buffer register
U0C0
U0C1
U0RB
00A716
00A816
UART1 transmit/receive mode register
00A916
UART1 bit rate generator
UART1 transmit buffer register
00AA16
U1MR
U1BRG
U1TB
00AB16
00AD16
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
00AE16
UART1 receive buffer register
U1C0
U1C1
U1RB
UART transmit/receive control register 2
UCON
00AC16
00AF16
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
X : Undefined
Blank columns are all reserved space. No access is allowed.
Rev.0.10
Oct 28, 2003
page 12 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
4. Special Function Register (SFR)
Register
Address
A-D register
Symbol
AD
A-D control register 2
ADCON2
0016
A-D control register 0
A-D control register 1
ADCON0
ADCON1
00000XXX2
0016
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
P0
P1
PD0
PD1
XX16
XX16
0016
0016
Port P3 register
P3
XX16
Port P3 direction register
Port P4 register
PD3
P4
0016
XX16
Port P4 direction register
PD4
0016
00FF16
Pull-up control register 0
Pull-up control register 1
Port P1 drivability control register
Timer C output control register
PUR0
PUR1
DRR
TCOUT
00XX00002
XXXXXX0X2
0016
0016
01B316
Flash memory control register 4
FMR4
0100000X2
Flash memory control register 1
FMR1
1000000X2
Flash memory control register 0
FMR0
XX0000012
00C016
00C116
After reset
XX16
XX16
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
03FA16
00FB16
00FC16
00FD16
00FE16
01B416
01B516
01B616
01B716
X : Undefined
Blank columns are all reserved space. No access is allowed.
Rev.0.10
Oct 28, 2003 page 13 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
5. Electrical Characteristics
5. Electrical Characteristics
Table 5.1 Absolute Maximum Ratings
Condition
Rated value
Unit
VCC
Symbol
Supply voltage
Parameter
VCC=AVCC
-0.3 to 6.5
V
AVCC
Analog supply voltage
VCC=AVCC
-0.3 to 6.5
V
VI
Input voltage
-0.3 to VCC+0.3
V
VO
Output voltage
-0.3 to VCC+0.3
V
Pd
Power dissipation
300
mW
Topr
Operating ambient temperature
-20 to 85 / -40 to 85 (D version)
C
Tstg
Storage temperature
Topr=25 C
C
-65 to 150
Table 5.2 Recommended Operating Conditions
Symbol
Parameter
VC C
AVcc
Supply voltage
Analog supply voltage
Vss
Supply voltage
Conditions
Min.
2.7
Standard
Typ.
5.0
5.5
VCC
0
Unit
V
V
V
V
AVss
Analog supply voltage
VIH
"H" input voltage
0.8VCC
VCC
V
VIL
"L" input voltage
0
0.2VCC
V
-60.0
mA
-10.0
mA
- 5 .0
mA
60
mA
I OH (peak)
Sum of all pins' IOH
"H" peak all
output currents (peak)
"H" peak output current
I OH (avg)
"H" average output current
I OL (sum)
Sum of all pins' IOL
"L" peak all
output currents (peak)
"L" peak output Except P10 to P17
current
P10 to P17
I OH (sum)
I OL (peak)
I OL (avg)
f (XIN)
"L" average
output current
0
Drive ability HIGH
Drive ability LOW
Except P10 to P17
P10 to P17
Drive ability HIGH
Drive ability LOW
Main clock input oscillation frequency 3.0V ≤ Vcc ≤ 5.5V
2.7V ≤ Vcc < 3.0V
0
0
Note
1: Referenced to VCC = AVCC = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified.
2: The mean output current is the mean value within 100ms.
Rev.0.10
Max.
Oct 28, 2003
page 14 of 26
10
mA
30
mA
10
mA
5
15
5
20
10
mA
mA
mA
MHz
MHz
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
5. Electrical Characteristics
Table 5.3 A-D Conversion Characteristics
Symbol
Parameter
–
Resolution
–
Absolute
accuracy
RLADDER
tCONV
VREF
VIA
–
Measuring condition
Vref =VCC
10
Bit
10 bit mode
f(XIN)=øAD=10 MHz, Vref=Vcc=5.0V
±3
LSB
8 bit mode
f(XIN)=øAD=10 MHz, Vref=Vcc=5.0V
±2
LSB
10 bit mode
f(XIN)=øAD=10 MHz, Vref=Vcc=3.3V
±5
LSB
8 bit mode
f(XIN)=øAD=10 MHz, Vref=Vcc=3.3V
±2
LSB
VREF=VCC
40
kΩ
µs
Ladder resistance
Conversion time
Standard
Unit
Min. Typ. Max.
10
10 bit mode f(XIN)=øAD=10 MHz, Vref=Vcc=5.0V
8 bit mode f(XIN)=øAD=10 MHz, Vref=Vcc=5.0V
3.3
2.8
µs
V
Reference voltage
Analog input voltage
2.0
VCC
0
Vref
V
A-D operation
Without sample & hold
clock frequency2 With sample & hold
0.25
10
MHz
10
MHz
1.0
Note
1: Referenced to VCC=AVCC=2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified.
2: When fAD is 10 MHz more, divide the fAD and make A-D operation clock frequency (ØAD) lower than
10 MHz.
3: When the Vcc is less than 4.2V, divide the fAD and make A-D operation clock frequency (ØAD) lower than fAD/2.
P0
P1
P2
P3
P4
Figure 5.1 Port P0 to P4 measurement circuit
Rev.0.10
Oct 28, 2003
page 15 of 26
30pF
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
5. Electrical Characteristics
Table 5.4 Flash Memory (Program area) Electrical Characteristics
Parameter
Symbol
Program/Erase
Measuring condition
cycle 2
Standard
Min.
Typ.
100
–
–
Byte program time
VCC = 5.0 V at Topr = 25 °C
50
–
Block erase time
VCC = 5.0 V at Topr = 25 °C
0.4
td(SR-ES)
Max
3
Time delay from Suspend Request until Erase Suspend
Unit
cycle
µs
s
TBD
ms
–
Program, Erase Voltage
2.7
5.5
V
–
Read Voltage
2.7
–
Program, Erase Temperature
5.5
60
°C
0
V
Table 5.5 Flash Memory (Data area Block A, Block B) Electrical Characteristics 4
Symbol
Parameter
Measuring condition
Program/Erase cycle 2
–
–
–
td(SR-ES)
Standard
Min.
Typ.
Max
Unit
cycle
10000 3
Byte program time
VCC = 5.0 V at Topr = 25 °C
65
µs
Block erase time
VCC = 5.0 V at Topr = 25 °C
0.3
s
TBD
ms
Program, Erase Voltage
2.7
5.5
V
Read Voltage
2.7
5.5
85
°C
Time delay from Suspend Request until Erase Suspend
–
–
–
Program, Erase Temperature
–20 8
V
Note
1: Referenced to VCC=AVcc=2.7 to 5.5V at Topr = 0 to 60 °C unless otherwise specified.
2: Definition of Program/Erase
The cycle of Program/Erase shows a cycle for each block.
If the program/erase number is “n” (n = 100, 10000), “n” times erase can be performed for each block.
For example, if performing one-byte write to the distinct addresses on Block A of 2K-byte block 2048 times and then
erasing that block, the number of Program/Erase cycles is one time.
However, performing multiple writes to the same address before an erase operation is prohibited (overwriting
prohibited).
3: Maximum numbers of Program/Erase cycles for which all electrical characteristics is guaranteed.
4: Table 5.5 applies for Block A or B when the Program/Erase cycles are more than 1000. The byte program time and
block erase time up to 1000 cycles are the same as that of the program area (see Table 5.4).
5: To reduce the number of Program/Erase cycles, a block erase should ideally be performed after writing in series as
many distinct addresses (only one time each) as possible. If programming a set of 16 bytes, write up to 128 sets and
then erase them one time. This will result in ideally reducing the number of Program/Erase cycles. Additionally,
averaging the number of Program/Erase cycles for Block A and B will be more effective. It is important to track the total
number of block erases and restrict the number.
6: If error occurs during block erase, attempt to execute the clear status register command, then the block erase
command at least three times until the erase error disappears.
7: Customers desiring Program/Erase failure rate information should contact their Renesas technical support representative.
8: –40 °C for D version.
Erase-suspend request
(interrupt request)
FMR46
td(SR-ES)
Figure 5.2 Time delay from Suspend Request until Erase Suspend
Rev.0.10
Oct 28, 2003
page 16 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
5. Electrical Characteristics
Table 5.6 Voltage Detection Circuit Electrical Characteristics
Symbol
Vdet4
Measuring condition
Parameter
Voltage detection level
Min.
3.3
Voltage detection interrupt request generating time2
Voltage detection circuit self consumption current
td(E-A)
Standard
Typ.
3.8
Max.
4.3
V
TBD
Waiting time till voltage detection circuit operation starts3
V
V
40
VC27="1"
Unit
20
V
Note
1: The measureing condition is Vcc=AVcc=5.0 V and Topr=25 °C.
2: This shows the time till the voltage detection interrupt request is generated since the voltage passes Vdet.
3: This shows the required time till the voltage detection circuit operates when setting to "1" again.
Table 5.7 Power-on Reset Circuit Electrical Characteristics
Symbol
Measuring condition
Parameter
Power-on reset start time2
Min.
Standard
Typ.
Max.
TBD
Vcc<0.5V
Unit
ms
V
Power-on reset cancel operation start voltage
3.3
3.8
4.3
Hardware reset 2 cancel operation start voltage
3.3
3.8
4.3
V
TBD
ms
Supply start up condition when using power-on reset circuit
Intergradation time to 0V<2.7V
Note
1: The measuring condition is Vcc=AVcc=5.0 V and Topr=25 °C.
2: Keep Vcc<0.5V for over regulated time to execute the reset operation.
Table 5.8 High-speed Ring Oscillator Circuit Electrical Characteristics
Symbol
Parameter
Measuring condition
Settable high-speed ring oscillator minimum period
Set "0016" in the HR1 register
High-speed ring oscillator adjusted unit
Differences when setting "0116" and "0016"
in the HR register
Min.
Standard
Typ.
Max.
Unit
TBD
ns
1
ns
Note
1: The measuring condition is Vcc=AVcc=5.0 V and Topr=25 °C.
Table 5.9 Power Circuit Timing Characteristics
Symbol
Parameter
td(P-R)
Time for internal power supply stabilization during powering-on2
td(R-S)
STOP release time3
Measuring condition
Note
1: The measuring condition is Vcc=AVcc=2.7 to 5.0 V and Topr=25 °C.
2: This shows the wait time untill the internal power supply generating circuit is stabilized during power-on.
3: This shows the time till BCLK starts from the interrupt acknowledgement to cancel stop mode.
Rev.0.10
Oct 28, 2003
page 17 of 26
Min.
Standard
Typ.
Max.
Unit
2
ms
150
µs
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
5. Electrical Characteristics
Table 5.10 Electrical Characteristics (1)
[Vcc=5V]
Measuring condition
Parameter
Symbol
"H" output voltage
Except XOUT
IOH=-5mA
IOH=-200µA
XOUT
Drive ability HIGH
Drive ability LOW
VOH
"L" output voltage
VOL
IOH=-1 mA
IOH=-500µA
P10 to P17
Except XOUT
IOH= 5 mA
IOH= 200 µA
P10 to P17
Drive ability HIGH
IOH= 10 mA
Drive ability LOW
IOH= 5 mA
Drive ability HIGH
Drive ability LOW
IOH= 1 mA
IOH=500µA
XOUT
Min.
VCC-2.0
VCC-0.3
VCC-2.0
VCC-2.0
0.2
VT+-VT-
Hysteresis
IIH
"H" input current
VI=5V
IIL
"L" input current
VI=0V
RPULLUP
Pull-up resistance
Feedback resistance
VI=0V
INT0, INT1, INT2, INT3, KI0, KI1,
KI2, KI3, CNTRo, CNTR1, TCIN,
RxD0, RxD1
0.2
RESET
RfXIN
fRING-S
VRAM
Low-speed ring oscillator frequency
At stop mode
Note
1 : Referenced to VCC=AVCC=4.2 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=20MHz unless otherwise specified.
Rev.0.10
Oct 28, 2003
30
XIN
RAM retention voltage
page 18 of 26
Standard
Typ.
Max.
40
2.0
Unit
VCC
VCC
VCC
VCC
V
V
2.0
V
0.45
V
2.0
2.0
V
V
2.0
V
2.0
V
1.0
V
V
V
2.2
V
5.0
µA
-5.0
µA
50
167
1.0
125
250
kΩ
MΩ
kHz
V
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
5. Electrical Characteristics
Table 5.11 Electrical Characteristics (2)
Symbol
[Vcc=5V]
Measuring condition
Parameter
High-speed
mode
Medium-speed
mode
ICC
Power supply current
(VCC=3.3 to 5.5V)
In single-chip mode, the output
pins are open and other pins
are VSS
High-speed ring
oscillator mode
XIN=20 MHz (square wave)
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
No division
XIN=16 MHz (square wave)
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
No division
XIN=10 MHz (square wave)
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
No division
XIN=20 MHz (square wave)
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
Division by 8
XIN=16 MHz (square wave)
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
Division by 8
XIN=10 MHz (square wave)
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
Division by 8
Main clock off
High-speed ring oscillator on=8 MHz
Low-speed ring oscillator on=125 kHz
No division
Main clock off
High-speed ring oscillator on=8 MHz
Low-speed ring oscillator on=125 kHz
Division by 8
Low-speed ring
oscillator mode
Main clock off
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
Division by 8
Wait mode
Main clock off
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
When a WAIT instruction is executed2
Peripheral clock operation
Main clock off
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
When a WAIT instruction is executed2
Peripheral clock off
Wait mode
Stop mode
Main clock off
High-speed ring oscillator off
Low-speed ring oscillator off
CM10="1"
Peripheral clock off
VC27="0"
Note
1: The power supply current measuring is executed using the measuring program on frash memory.
2: Timer Y is operated with timer mode.
Rev.0.10
Oct 28, 2003
page 19 of 26
Min.
Standard
Typ.
Max.
Unit
9
15
mA
8
14
mA
5
mA
4
mA
3
mA
2
mA
4
8
1.5
mA
mA
0.4
2.0
mA
TBD
TBD
µA
TBD
TBD
µA
0.8
3.0
µA
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
5. Electrical Characteristics
Timing requirements (Unless otherwise noted: VCC = 5V, VSS = 0V at Ta = 25 °C) [VCC=5V]
Table 5.12 XIN input
Symbol
tC(XIN)
tWH(XIN)
tWL(XIN)
Parameter
XIN input cycle time
XIN input HIGH pulse width
XIN input LOW pulse width
Standard
Min.
Max.
62.5
30
30
Unit
Standard
Min.
Max.
100
40
40
Unit
Standard
Max.
Min.
Unit
ns
ns
ns
________
Table 5.13 CNTR0 input, CNTR1 input, INT2 input
Symbol
Parameter
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
CNTR0 input cycle time
CNTR0 input HIGH pulse width
CNTR0 input LOW pulse width
ns
ns
ns
________
Table 5.14 TCIN input, INT3 input
Symbol
Parameter
tC(TCIN)
400 1
TCIN input cycle time
tWH(TCIN)
200 2
TCIN input HIGH pulse width
tWL(TCIN)
200 2
TCIN input LOW pulse width
Note
1 : Use the greater value,either ( 1/ digital filter clock frequency x 6) or min. value.
2 : Use the greater value,either ( 1/ digital filter clock frequency x 3) or min. value.
ns
ns
ns
Table 5.15 Serial I/O
Symbol
tC(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Parameter
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
RxDi input setup time
RxDi input hold time
Standard
Min.
Max.
200
100
100
80
0
35
90
Unit
Standard
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
________
Table 5.16 External interrupt INT0 input
Symbol
tW(INH)
tW(INL)
Parameter
________
INT0
input HIGH pulse width
________
INT0 input LOW pulse width
250 1
250 2
ns
ns
Note
________
________
1 : When the INT0 input filter select bit selects the digital filter, use the INT0 input HIGH pulse width to the
greater value,either
( 1/ digital filter clock frequency x 3) or min. value.
________
________
2 : When the INT0 input filter select bit selects the digital filter, use the INT0 input LOW pusle width to the
greater value,either ( 1/ digital filter clock frequency x 3) or min. value.
Rev.0.10
Oct 28, 2003
page 20 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
5. Electrical Characteristics
VCC = 5V
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
tc(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TxDi
td(C-Q)
tsu(D-C)
RxDi
tW(INL)
INTi
tW(INH)
Figure 5.3 Vcc=5V timing diagram
Rev.0.10
Oct 28, 2003
page 21 of 26
th(C-D)
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
5. Electrical Characteristics
Table 5.17 Electrical Characteristics (3)
Symbol
[Vcc=3V]
Measuring condition
Parameter
"H" output voltage
VOH
"L" output voltage
VOL
Except XOUT
IOH=-1mA
XOUT
Drive ability HIGH
Drive ability LOW
P10 to P17
Except XOUT
IOH= 1 mA
P10 to P17
Drive ability HIGH
XOUT
VT+-VT-
Hysteresis
II H
"H" input current
IOH=-0.1 mA
IOH=-50 µA
Min.
VCC
V
VCC-0.5
VCC-0.5
VCC
VCC
V
V
0 .5
V
IOH= 2 mA
IOH= 1 mA
0.5
V
Drive ability LOW
0.5
V
Drive ability HIGH
Drive ability LOW
IOH= 0.1 mA
IOH=50 µA
0 .5
0.5
V
V
0.2
0 .8
V
0 .2
1 .8
4.0
V
µA
-4.0
µA
RESET
II L
"L" input current
VI=3V
VI=0V
RPULLUP
RfXIN
Pull-up resistance
VI=0V
fRING-S
Low-speed ring oscillator frequency
VRAM
RAM retention voltage
Oct 28, 2003
66
160
40
3.0
125
XIN
At stop mode
2 .0
Note
1 : Referenced to VCC=AVCC=2.7 to 3.3V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified.
Rev.0.10
page 22 of 26
Unit
VCC-0.5
INT0, INT1, INT2, INT3, KI0, KI1,
KI2, KI3, CNTRo, CNTR1, TCIN,
RxD0, RxD1
Feedback resistance
Standard
Max.
Typ.
500
kΩ
250
MΩ
kHz
V
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
5. Electrical Characteristics
Table 5.18 Electrical Characteristics (4)
Symbol
[Vcc=3V]
Measuring condition
Parameter
High-speed
mode
Medium-speed
mode
ICC
Power supply current
(VCC=2.7 to 3.3V)
In single-chip mode, the output
pins are open and other pins
are VSS
High-speed ring
oscillator mode
XIN=20 MHz (square wave)
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
No division
XIN=16 MHz (square wave)
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
No division
XIN=10 MHz (square wave)
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
No division
XIN=20 MHz (square wave)
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
Division by 8
XIN=16 MHz (square wave)
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
Division by 8
XIN=10 MHz (square wave)
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
Division by 8
Main clock off
High-speed ring oscillator on=8 MHz
Low-speed ring oscillator on=125 kHz
No division
Main clock off
High-speed ring oscillator on=8 MHz
Low-speed ring oscillator on=125 kHz
Division by 8
Low-speed ring
oscillator mode
Main clock off
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
Division by 8
Wait mode
Main clock off
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
When a WAIT instruction is executed2
Peripheral clock operation
Main clock off
High-speed ring oscillator off
Low-speed ring oscillator on=125 kHz
When a WAIT instruction is executed2
Peripheral clock off
Wait mode
Stop mode
Main clock off
High-speed ring oscillator off
Low-speed ring oscillator off
CM10="1"
Peripheral clock off
VC27="0"
Note
1: The power supply current measuring is executed using the measuring program on frash memory.
2: Timer Y is operated with timer mode.
Rev.0.10
Oct 28, 2003
page 23 of 26
Min.
Standard
Typ.
Max.
Unit
8
13
mA
7
12
mA
5
mA
3
mA
2.5
mA
1.6
mA
3.5
7.5
mA
mA
1.5
0.4
2.0
mA
TBD
TBD
µA
TBD
TBD
µA
0.7
3.0
µA
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
5. Electrical Characteristics
Timing requirements (Unless otherwise noted: VCC = 3V, VSS = 0V at Ta = 25 °C) [VCC=3V]
Table 5.19 XIN input
Symbol
tC(XIN)
tWH(XIN)
tWL(XIN)
Parameter
XIN input cycle time
XIN input HIGH pulse width
XIN input LOW pulse width
Standard
Min.
Max.
143
70
70
Unit
Standard
Min.
Max.
300
120
120
Unit
Standard
Min.
Max.
Unit
ns
ns
ns
________
Table 5.20 CNTR0 input, CNTR1 input, INT2 input
Symbol
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
Parameter
CNTR0 input cycle time
CNTR0 input HIGH pulse width
CNTR0 input LOW pulse width
ns
ns
ns
________
Table 5.21 TCIN input, INT3 input
Symbol
Parameter
tC(TCIN)
1200 1
TCIN input cycle time
tWH(TCIN)
600 2
TCIN input HIGH pulse width
tWL(TCIN)
600 2
TCIN input LOW pulse width
Note
1 : Use the greater value,either ( 1/ digital filter clock frequency x 6) or min. value.
2 : Use the greater value,either ( 1/ digital filter clock frequency x 3) or min. value.
ns
ns
ns
Table 5.22 Serial I/O
Symbol
tC(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Parameter
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
RxDi input setup time
RxDi input hold time
Standard
Min.
Max.
300
150
150
160
0
55
90
Unit
Standard
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
________
Table 5.23 External interrupt INT0 input
Symbol
tW(INH)
tW(INL)
Parameter
________
INT0
input HIGH pulse width
________
INT0 input LOW pulse width
380 1
380 2
ns
ns
Note
________
________
1 : When the INT0 input filter select bit selects the digital filter, use the INT0 input HIGH pulse width to the
greater value,either
( 1/ digital filter clock frequency x 3) or min. value.
________
________
2 : When the INT0 input filter select bit selects the digital filter, use the INT0 input LOW pusle width to the
greater value,either ( 1/ digital filter clock frequency x 3) or min. value.
Rev.0.10
Oct 28, 2003
page 24 of 26
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
5. Electrical Characteristics
VCC = 3V
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
tc(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TxDi
td(C-Q)
tsu(D-C)
RxDi
tW(INL)
INTi
tW(INH)
Figure 5.4 Vcc=3V timing diagram
Rev.0.10
Oct 28, 2003
page 25 of 26
th(C-D)
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/13 Group
Package Dimensions
Package Dimensions
32P6U-A
MMP
Plastic 32pin 7✕7mm body LQFP
Weight(g)
JEDEC Code
–
Lead Material
Cu Alloy
MD
b2
HD
D
32
ME
e
EIAJ Package Code
LQFP32-P-0707-0.80
25
I2
24
Recommended Mount Pad
Symbol
E
HE
1
8
17
9
16
A
b
y
Rev.0.10
Oct 28, 2003
page 26 of 26
x
M
L
Lp
Detail F
c
A1
F
A2
e
A3
L1
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
A3
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
1.7
0.1
0.2
0
–
–
1.4
0.32
0.37
0.45
0.105
0.125
0.175
6.9
7.0
7.1
6.9
7.0
7.1
0.8
–
–
8.8
9.0
9.2
8.8
9.0
9.2
0.3
0.5
0.7
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.2
0.1
–
–
0°
10°
–
0.5
–
–
1.0
–
–
7.4
–
–
–
–
7.4
REVISION HISTORY
Rev.
R8C/13 Group Data Sheet
Date
Description
Summary
Page
0.10 Oct 28, 2003
First edition issued
A-1
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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