AD EVAL-SSM3302Z

Data Sheet
FEATURES
Filterless stereo Class-D amplifier with Σ-Δ modulation
2 × 10 W into 4 Ω load and 2 × 8 W into 8 Ω load at 12 V supply
with <1% total harmonic distortion plus noise (THD + N)
91% efficiency at 12 V, 8 W into 8 Ω speaker
98 dB signal-to-noise ratio (SNR)
Single-supply operation from 7 V to 18 V
Flexible gain adjustment pin from 9 dB to 24 dB
Fixed input impedance of 40 kΩ
Mono output mode pin for 1 × 20 W output power into 2 Ω
10 µA shutdown current
Short-circuit and thermal protection
Available in a 40-lead, 6 mm × 6 mm LFCSP
Pop-and-click suppression
User-selectable ultralow EMI emissions mode
Thermal warning indicator
Power-on reset
APPLICATIONS
Mobile computing
Flat panel televisions
Media docking stations
Portable electronics
Sound bars
GENERAL DESCRIPTION
The SSM3302 is a fully integrated, high efficiency, stereo Class-D
audio amplifier. The application circuit requires minimal external
components and operates from a single 7 V to 18 V supply. The
device is capable of delivering 2 × 10 W of continuous output
power into a 4 Ω load (or 2 × 8 W into 8 Ω) with <1% THD + N
from a 12 V supply. In addition, while mono mode is activated,
the user can drive a load as small as 2 Ω up to 20 W continuous
output power by stacking the stereo output terminals.
The SSM3302 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. This scheme
continues to provide high efficiency even at low output power.
The SSM3302 operates with 90% efficiency at 7 W into an 8 Ω
2 ×10 W Filterless Class-D
Stereo Audio Amplifier
SSM3302
load or with 82% efficiency at 10 W into 4 Ω from a 12 V supply,
and it has an SNR of >98 dB.
Spread spectrum pulse density modulation (PDM) is used to
provide lower EMI radiated emissions compared with other
Class-D architectures. The SSM3302 includes an optional
modulation select pin (ultralow EMI emission mode) that
significantly reduces the radiated emissions at the Class-D
outputs, particularly above 100 MHz. The SSM3302 can pass
FCC Class-B emissions testing with an unshielded 20 inch cable
using common-mode choke-based filtering.
The fully differential input of the SSM3302 provides excellent
rejection of common-mode noise on the input. The device also
includes a highly flexible gain select pin that only requires one
series resistor to choose a gain between 9 dB and 24 dB, with no
change to the input impedance. The benefit of this is to improve
gain matching between multiple SSM3302 devices within a single
application compared with using external resistors to set gain.
The SSM3302 includes an integrated voltage regulator that
generates a 5 V rail.
The SSM3302 has a micropower shutdown mode with a typical
shutdown current of 10 µA. Shutdown is enabled by applying a
logic low to the SD pin. The device also includes pop-and-click
suppression circuitry that minimizes voltage glitches at the output
during turn on and turn off, reducing audible noise during
activation and deactivation.
Other included features to simplify system level integration of
the SSM3302 are input low-pass filtering to suppress out-ofband DAC noise interference to the pulse density modulator,
fixed input impedance to simplify component selection across
multiple platform production builds, and a thermal warning
indicator pin.
The SSM3302 is specified over the commercial temperature
range (−40°C to +85°C). It has built-in thermal shutdown and
output short-circuit protection. It is available in a halide-free,
40-lead, 6 mm × 6 mm lead frame chip scale package (LFCSP).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
SSM3302
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Analog Supply............................................................................. 16 Applications....................................................................................... 1 Gain Selection............................................................................. 16 General Description ......................................................................... 1 Amplifier Protection .................................................................. 16 Revision History ............................................................................... 2 Pop-and-Click Suppression ...................................................... 16 Functional Block Diagram .............................................................. 3 EMI Noise.................................................................................... 16 Specifications..................................................................................... 4 Mono Mode................................................................................. 16 Absolute Maximum Ratings............................................................ 6 Output Modulation Description .............................................. 17 Thermal Resistance ...................................................................... 6 Layout .......................................................................................... 17 ESD Caution.................................................................................. 6 Input Capacitor Selection.......................................................... 17 Pin Configuration and Function Descriptions............................. 7 Bootstrap Capacitors.................................................................. 17 Typical Performance Characteristics ............................................. 8 Power Supply Decoupling ......................................................... 18 Typical Application Circuits.......................................................... 14 Outline Dimensions ....................................................................... 19 Applications Information .............................................................. 16 Ordering Guide .......................................................................... 19 Overview...................................................................................... 16 REVISION HISTORY
2/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
Data Sheet
SSM3302
FUNCTIONAL BLOCK DIAGRAM
PVDD
THERM
SSM3302
INR+
BOOTR+
40kΩ
40kΩ
OUTR+
GAIN
CONTROL
MODULATOR
(Σ-∆)
FET
DRIVER
INR–
OUTR–
BOOTR–
BIAS
SDNR
INTERNAL
OSCILLATOR
MONO
BIAS
SDNL
BOOTL+
40kΩ
40kΩ
OUTL+
GAIN
CONTROL
MODULATOR
(Σ-∆)
FET
DRIVER
INL–
OUTL–
BOOTL–
VREG
GAIN
VREG
(AVDD)
AGND
Figure 1.
Rev. 0 | Page 3 of 20
REGEN
PGND
10198-001
INL+
EDGE
EDGE
CONTROL
SSM3302
Data Sheet
SPECIFICATIONS
PVDD = 12 V, TA = 25oC, RL = 8 Ω + 64 μH, EDGE = AGND, gain = 9 dB, VREG = off, unless otherwise noted.
Table 1.
Parameter
DEVICE CHARACTERISTICS
Output Power/Channel
Symbol
Test Conditions/Comments
PO
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 15 V
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 15 V
RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 15 V
RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 15 V
RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 2 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
(mono mode)
RL = 2 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
(mono mode)
RL = 2 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
(mono mode)
RL = 2 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
(mono mode)
PO = 7 W, 8 Ω, PVDD = 12 V, EDGE = low (normal operation)
PO = 7 W, 8 Ω, PVDD = 12 V, EDGE = AVDD (ultralow
EMI mode)
PO = 5 W into 8 Ω, f = 1 kHz, PVDD = 12 V
Efficiency
η
Total Harmonic
Distortion + Noise
Input Common-Mode
Voltage Range
Common-Mode
Rejection Ratio
Channel Separation
Average Switching
Frequency
Differential Output
Offset Voltage
POWER SUPPLY
Supply Voltage Range
Power Supply Rejection
Ratio
THD + N
Supply Current (Stereo)
Min
Typ
Unit
12 1
8
2.7
151
10
3.2
201
131
4.8
241
161
5.7
29 2
W
W
W
W
W
W
W
W
W
W
W
W
W
9.42
W
36.62
W
12.72
W
91.5
82
%
%
0.01
%
1.0
VCM
Max
AVDD − 1
V
CMRR
VCM = 2.5 V ± 100 mV at 1 kHz, output referred
43
dB
XTALK
fSW
PO = 0.5 W, f = 1 kHz
80
300
dB
kHz
VOOS
Gain = 9 dB
PVDD
PSRRDC
Guaranteed from PSRR test
PVDD = 7 V to 15 V, dc input floating
PSRRAC
ISYPVDD
VRIPPLE = 100 mV at 1 kHz, inputs are ac grounded, CIN = 0.1 μF
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 15 V, VREGEN = AVDD
(internal VREG active)
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 15 V, VREGEN = AGND
(internal VREG disabled)
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 12 V, VREGEN = AGND
(internal VREG disabled)
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 7 V, VREGEN = AGND
(internal VREG disabled)
Rev. 0 | Page 4 of 20
3.0
mV
18
70
V
dB
80
12.2
dB
mA
6.2
mA
5
mA
3
mA
7
Data Sheet
Parameter
Shutdown Current
ANALOG SUPPLY
External Supply Voltage
On-Board Regulator
Regulator Current
Regulator Power Supply
Rejection
GAIN CONTROL
Closed-Loop Voltage Gain
Input Impedance
SHUTDOWN CONTROL
Input Voltage High
Input Voltage Low
Turn-On Time
Turn-Off Time
Output Impedance
AMPLIFIER PROTECTION
Overcurrent Threshold
Overtemperature
Warning
Overtemperature
Shutdown
Recovery Temperature
NOISE PERFORMANCE
Output Voltage Noise
Signal-to-Noise Ratio
SSM3302
Symbol
ISYAVDD
Test Conditions/Comments
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 15 V, VREGEN = AGND
(internal VREG disabled)
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 12 V, VREGEN = AGND
(internal VREG disabled)
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 7 V, VREGEN = AGND
(internal VREG disabled)
SD = AGND
Min
AVDD
VVREG
IVREG
PSRRVREG
Permissible range for external AVDD, VREGEN = AGND
4.5
AV
ZIN
See Table 5 for gain options
ISD
VIH
VIL
tWU
tSD
ZOUT
Typ
5.85
Max
Unit
mA
5.8
mA
5.6
mA
10
μA
5.5
V
V
mA
dB
24
dB
kΩ
5
20
70
9
40
40
500
56
V
V
ms
μs
kΩ
IOC
TWARN
6
120
A
°C
TSD
145
°C
TREC
85
°C
100
μV rms
98
dB
en
SNR
1.35
0.35
SD rising edge from AGND to AVDD
SD falling edge from AVDD to AGND
SD = GND
PVDD = 12 V, f = 20 Hz to 20 kHz, inputs are ac grounded,
gain = 9 dB, A-weighted
PO = 10 W, RL = 8 Ω
1
Although the SSM3302 has good audio quality above 2 × 10 W into 4 Ω, continuous output power beyond 2 × 10 W into 4 Ω must be avoided due to device packaging
limitations.
2
Mono mode. Output power beyond 20 W needs special care for thermally considered printed circuit board (PCB) design.
Rev. 0 | Page 5 of 20
SSM3302
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 2.
θJA (junction to air) is specified for the worst-case conditions,
that is, a device soldered in a circuit board for surface-mount
packages. θJA and θJC are determined according to JESD51-9 on
a 4-layer printed circuit board (PCB) with natural convection
cooling.
Parameter
Power Supply Voltage (PVDD)
Analog Supply Voltage (AVDD)
Input Voltage
ESD Susceptibility
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
−0.3 V to +25 V
−0.3 V to +6 V
−0.3 V to +6 V
4 kV
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
Table 3. Thermal Resistance
Package Type
40-Lead, 6 mm × 6 mm LFCSP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 20
θJA
31
θJC
2.5
Unit
°C/W
Data Sheet
SSM3302
40
39
38
37
36
35
34
33
32
31
PGND
PGND
PGND
PVDD
PVDD
PVDD
PVDD
PGND
PGND
PGND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SSM3302
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
BOOTR+
OUTR+
OUTR+
OUTR–
OUTR–
BOOTR–
AGND
REGEN
SDNR
GAIN
NOTES
1. USE MULTIPLE VIAS TO CONNECT THE EXPOSED PAD
TO THE GROUND PLANE.
2. PINS LABELED NC CAN BE ALLOWED TO FLOAT,
BUT IT IS BETTER TO CONNECT THESE PINS TO
GROUND. AVOID ROUTING HIGH SPEED SIGNALS
THROUGH THESE PINS BECAUSE NOISE COUPLING
MAY RESULT.
10198-002
INL+
INL–
NC
TEST
TEST
MONO
THERM
NC
INR–
INR+
11
12
13
14
15
16
17
18
19
20
BOOTL+ 1
OUTL+ 2
OUTL+ 3
OUTL– 4
OUTL– 5
BOOTL– 6
AGND 7
VREG/AVDD 8
SDNL 9
EDGE 10
Figure 2. Pin Configuration (Top Side View)
Table 4. Pin Function Descriptions
Pin No.
1
2, 3
4, 5
Mnemonic
BOOTL+
OUTL+
OUTL−
Description
Bootstrap Input/Output for Left Channel, Noninverting Output.
Noninverting Output for Left Channel.
Inverting Output for Left Channel.
6
7
8
9
10
11
12
13, 18
BOOTL−
AGND
VREG/AVDD
SDNL
EDGE
INL+
INL−
NC
Bootstrap Input/Output for Left Channel, Inverting Output.
Analog Ground.
5 V Regulator Output (if REGEN = high)/AVDD Input (if REGEN = low).
Shutdown, Left Channel. Active low digital input.
Edge Control (Low Emission Mode). Active high digital input.
Noninverting Input for Left Channel.
Inverting Input for Left Channel.
This pin is not connected internally (see Figure 2).
14, 15
TEST
Test Pins. Tie to AGND.
16
MONO
Mono Output Mode Enable.
17
19
20
21
22
23
24
25
26, 27
28, 29
30
31, 32, 33, 38, 39, 40
34, 35, 36, 37
THERM
INR−
INR+
GAIN
SDNR
REGEN
AGND
BOOTR−
OUTR−
OUTR+
BOOTR+
PGND
PVDD
Exposed Pad
Overtemperature Warning (Open Collector).
Inverting Input for Right Channel.
Noninverting Input for Right Channel.
Gain Select from 9 dB to 24 dB.
Shutdown, Right Channel. Active low digital input.
5 V Regulator Enable, Active High.
Analog Ground.
Bootstrap Input/Output for Right Channel, Inverting Output.
Inverting Output for Right Channel.
Noninverting Output for Right Channel.
Bootstrap Input/Output for Right Channel, Noninverting Output.
Power Stage Ground.
Power Stage Power Supply.
Thermal Exposed Pad. Use multiple vias to connect this pad to the ground plane.
Rev. 0 | Page 7 of 20
SSM3302
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise stated, all data at PVDD = 12 V, EDGE = low, MONO = low, REGEN = high, and GAIN = 9 dB.
100
10
100
RL = 8Ω + 33µH
GAIN = 9dB
EDGE = LOW
PVDD = 7V
10
RL = 8Ω + 33µH
GAIN = 9dB
PVDD = 12V
1
THD + N (%)
THD + N (%)
PVDD = 12V
PVDD = 18V
0.1
1
EDGE = HIGH
0.1
EDGE = LOW
0.01
0.001
0.01
0.1
1
10
100
OUTPUT POWER (W)
0.001
1µ
10198-003
0.001
0.0001
0.1m
1m
10m
100m
1
10
100
10
100
10
100
OUTPUT POWER (W)
Figure 3. THD + N vs. Output Power into 8 Ω;
PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
Figure 6. THD + N vs. Output Power into 8 Ω;
EDGE = High, EDGE = Low
100
10
0.01m
10198-006
0.01
100
RL = 4Ω + 15µH
GAIN = 9dB
EDGE = LOW
RL = 4Ω + 15µH
GAIN = 9dB
PVDD = 7V
10
1
THD + N (%)
THD + N (%)
PVDD = 12V
PVDD = 18V
0.1
1
EDGE = HIGH
0.1
EDGE = LOW
0.01
0.001
0.01
0.1
1
10
100
OUTPUT POWER (W)
0.001
1µ
10198-004
0.001
0.0001
1m
10m
100m
1
Figure 7. THD + N vs. Output Power into 4 Ω;
EDGE = High, EDGE = Low
100
100
RL = 2Ω + 7.5µH
GAIN = 9dB
PVDD = 7V
10
10
PVDD = 12V
1
THD + N (%)
1
PVDD = 18V
0.1
0.1
EDGE = HIGH
0.01
0.001
0.001
0.1m
1m
10m
100m
1
10
100
OUTPUT POWER (W)
10198-005
0.01
0.01m
Figure 5. THD + N vs. Output Power into 2 Ω;
Mono Mode; Gain = 9 dB; PVDD = 7 V, PVDD = 12 V, 1 PVDD = 8 V
EDGE = LOW
0.0001
1µ
0.01m
0.1m
1m
10m
100m
1
OUTPUT POWER (W)
Figure 8. THD + N vs. Output Power into 2 Ω;
EDGE = High, EDGE = Low
Rev. 0 | Page 8 of 20
10198-008
RL = 2Ω + 7.5µH
GAIN = 9dB
THD + N (%)
0.1m
OUTPUT POWER (W)
Figure 4. THD + N vs. Output Power into 4 Ω;
PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
0.0001
1µ
0.01m
10198-007
0.01
Data Sheet
SSM3302
100
100
PVDD = 7V
RL = 8Ω + 33µH
GAIN = 9dB
EDGE = LOW
10
PVDD = 12V
RL = 8Ω + 33µH
GAIN = 9dB
EDGE = LOW
10
PO = 7.5W
1
THD + N (%)
0.1
1
0.1
PO = 2.5W
PO = 0.25W
0.01
0.01
PO = 0.5W
100
1k
10k
100k
FREQUENCY (Hz)
0.001
10
10198-009
0.001
10
1k
10k
100k
Figure 12. THD + N vs. Frequency;
RL = 8 Ω; PVDD = 12 V; PO = 2.5 W, PO = 5 W, PO = 7.5 W
100
100
PVDD = 7V
RL = 4Ω + 15µH
GAIN = 9dB
EDGE = LOW
PVDD = 12V
RL = 4Ω + 15µH
GAIN = 9dB
EDGE = LOW
10
PO = 5W
1
THD + N (%)
THD + N (%)
100
FREQUENCY (Hz)
Figure 9. THD + N vs. Frequency;
RL = 8 Ω; PVDD = 7 V; PO = 0.25 W, PO = 0.5 W, PO = 2.5 W
10
PO = 5W
10198-012
THD + N (%)
PO = 2.5W
0.1
1
0.1
PO = 0.5W
PO = 2.5W
PO = 5W
0.01
PO = 2.5W
100
1k
10k
100k
FREQUENCY (Hz)
0.001
10
10198-010
1k
100k
100
PVDD = 7V
RL = 2Ω + 7.5µH
GAIN = 9dB
EDGE = 0V
MONO = 5V
10
PO = 3.5W
THD + N (%)
1
0.1
PVDD = 12V
RL = 4Ω + 7.5µH
GAIN = 9dB
EDGE = LOW
MONO = 5V
1
0.1
PO = 0.5W
PO = 0.5W
0.01
PO = 2.5W
0.01
PO = 2.5W
100
1k
PO = 5W
10k
100k
FREQUENCY (Hz)
10198-011
0.001
10
10k
Figure 13. THD + N vs. Frequency;
RL = 4 Ω; PVDD = 12 V; PO = 2.5 W, PO = 5 W, PO = 10 W
100
THD + N (%)
100
FREQUENCY (Hz)
Figure 10. THD + N vs. Frequency;
RL = 4 Ω; PVDD = 7 V; PO = 0.5 W, PO = 2.5 W, PO = 5 W
10
PO = 10W
Figure 11. THD + N vs. Frequency;
RL = 2 Ω; Mono Mode; PVDD = 7 V; PO = 0.5 W, PO = 2.5 W, PO = 3.5 W
0.001
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 14. THD + N vs. Frequency;
RL = 2 Ω; Mono Mode; PVDD = 12 V; PO = 0.5 W, PO = 2.5 W, PO = 5 W
Rev. 0 | Page 9 of 20
10198-014
0.001
10
10198-013
0.01
SSM3302
Data Sheet
100
16
PVDD = 18V
RL = 8Ω + 33µH
GAIN = 9dB
EDGE = LOW
QUIESCENT CURRENT (mA)
THD + N (%)
10
NO LOAD
14
1
0.1
PO = 5W
PO = 2.5W
0.01
8Ω + 33µH
12
4Ω + 15µH
10
8
6
4
100
1k
10k
100k
FREQUENCY (Hz)
0
10198-015
0.001
10
7
10
11
12
13
14
15
16
17
18
Figure 18. Quiescent Current vs. Supply Voltage,
RL = 8 Ω + 33 μH, No Load, , RL = 4 Ω + 15 μH
16
100
PVDD = 18V
RL = 4Ω + 15µH
GAIN = 9dB
EDGE = 0
1
PO = 10W
PO = 5W
0.01
10k
100k
FREQUENCY (Hz)
6
4
7
8
9
10
11
12
13
14
15
16
17
SUPPLY VOLTAGE (V)
18
Figure 19. Quiescent Current vs. Supply Voltage,
Mono Mode, No Load, RL = 4 Ω + 15 μH, RL = 2 Ω + 7.5 μH
Figure 16. THD + N vs. Frequency;
RL = 4 Ω; PVDD = 18 V; PO = 2.5 W, PO = 5 W, PO = 10 W
100
25
PVDD = 18V
RL = 2Ω + 7.5µH
GAIN = 9dB
EDGE = 0
MONO = 5V
MAXIMUM OUTPUT POWER (W)
10
2Ω + 7.5µH
8
0
10198-016
1k
4Ω + 15µH
10
2
PO = 2.5W
100
12
10198-019
0.1
0.001
10
NO LOAD
14
QUIESCENT CURRENT (mA)
10
1
0.1
PO = 0.5W
PO = 5W
0.01
RL = 8Ω + 33µH
GAIN = 9dB
EDGE = 0
20
15
THD = 10%
10
THD + N = 1%
5
100
1k
10k
100k
FREQUENCY (Hz)
10198-017
PO = 2.5W
0.001
10
0
7
9
11
13
15
17
SUPPLY VOLTAGE (V)
Figure 20. Maximum Output Power vs. Supply Voltage;
RL = 8 Ω; THD + N = 1%, THD + N = 10%
Figure 17. THD + N vs. Frequency;
RL = 2 Ω; Mono Mode; PVDD = 18 V; PO = 0.5 W, PO = 2.5 W, PO = 5 W
Rev. 0 | Page 10 of 20
10198-020
THD + N (%)
9
SUPPLY VOLTAGE (V)
Figure 15. THD + N vs. Frequency;
RL = 8 Ω; PVDD = 18 V; PO = 2.5 W, PO = 5 W, PO = 10 W
THD + N (%)
8
10198-018
2
PO = 10W
Data Sheet
SSM3302
800
RL = 4Ω + 15µH
GAIN = 9dB
EDGE = 0
700
20
THD = 10%
15
THD + N = 1%
10
5
PVDD = 7V
500
PVDD = 12V
400
300
PVDD = 18V
200
RL = 4Ω + 15µH
GAIN = 9dB
REGEN = 5V
100
7
8
9
10
11
12
13
15
14
SUPPLY VOLTAGE (V)
0
0
2.0
2.5
3.0
3.5
4.0
4.5
3500
RL = 2Ω + 7.5µH
GAIN = 9dB
EDGE = 0
MONO
3000
SUPPLY CURRENT (mA)
50
THD = 10%
40
THD = 1%
30
20
10
2500
PVDD = 12V
PVDD = 7V
2000
PVDD = 18V
1500
1000
RL = 2Ω + 7.5µH
GAIN = 9dB
REGEN = 5V
500
9
7
11
13
15
0
10198-022
17
SUPPLY VOLTAGE (V)
0
5
10
15
20
25
30
35
40
OUTPUT POWER (W)
Figure 22. Maximum Output Power vs. Supply Voltage;
RL = 2 Ω; Mono Mode; THD + N = 1%, THD + N = 10%
Figure 25. Supply Current vs. Output Power into 2 Ω;
Mono Mode; PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
100
800
PVDD =7V
90
700
80
PVDD = 7V
600
EFFICIENCY (%)
70
500
PVDD = 12V
400
300
PVDD = 18V
PVDD = 12V
PVDD = 18V
60
50
40
30
200
20
RL = 8Ω + 33µH
GAIN = 9dB
REGEN = 5V
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
OUTPUT POWER (W)
RL = 8Ω + 33µH
GAIN = 9dB
EDGE = LOW
10
5.0
10198-023
100
0
0
5
10
15
20
25
OUTPUT POWER (W)
Figure 26. Efficiency vs. Output Power into 8 Ω;
PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
Figure 23. Supply Current vs. Output Power into 8 Ω;
PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
Rev. 0 | Page 11 of 20
30
10198-026
MAXIMUM OUTPUT POWER (W)
1.5
Figure 24. Supply Current vs. Output Power into 4 Ω;
PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
60
SUPPLY CURRENT (mA)
1.0
OUTPUT POWER (W)
Figure 21. Maximum Output Power vs. Supply Voltage;
RL = 4 Ω; THD + N = 1%, THD + N = 10%
0
0.5
10198-025
0
600
10198-024
SUPPLY CURRENT (mA)
25
10198-021
MAXIMUM OUTPUT POWER (W)
30
SSM3302
Data Sheet
100
100
PVDD = 7V
90
90
80
PVDD = 12V
60
EDGE = HIGH
70
PVDD = 18V
EFFICIENCY (%)
50
40
30
60
50
40
30
20
RL = 4Ω + 15µH
GAIN = 9dB
EDGE = LOW
0
5
10
15
20
25
10
30
OUTPUT POWER (W)
0
10198-027
10
0
20
25
30
100
PVDD = 7V
90
90
80
EDGE = LOW
80
PVDD = 12V
EDGE = HIGH
70
PVDD = 18V
EFFICIENCY (%)
70
60
50
40
30
60
50
40
30
20
20
RL = 2Ω + 7.5µH
GAIN = 9dB
EDGE = LOW
0
5
10
15
20
25
30
35
10
40
OUTPUT POWER (W)
0
10198-028
10
0
5
10
15
20
25
30
35
OUTPUT POWER (W)
Figure 28. Efficiency vs. Output Power into 2 Ω;
Mono Mode; PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
10198-031
EFFICIENCY (%)
15
Figure 30. Efficiency vs. Output Power into 4 Ω;
PVDD = 12 V; EDGE = High, EDGE = Low
100
Figure 31. Efficiency vs. Output Power into 2 Ω;
Mono Mode; PVDD = 12 V; EDGE = High, EDGE = Low
100
0
EDGE = LOW
90
–10
80
EDGE = HIGH
–20
70
CMRR (dB)
60
50
40
–30
–40
–50
30
–60
20
–70
10
0
0
5
10
15
20
25
OUTPUT POWER (W)
30
10198-029
EFFICIENCY (%)
10
OUTPUT POWER (W)
Figure 27. Efficiency vs. Output Power into 4 Ω;
PVDD = 7 V, PVDD = 12 V, PVDD = 18 V
0
5
10198-030
20
Figure 29. Efficiency vs. Output Power into 8 Ω;
PVDD = 12 V; EDGE = High, EDGE = Low
–80
20
200
2,000
20,000
FREQUENCY (Hz)
Figure 32. CMRR vs. Frequency, VRIPPLE = 100 mV rms, AC-Coupled
Rev. 0 | Page 12 of 20
10198-032
EFFICIENCY (%)
70
0
EDGE = LOW
80
Data Sheet
SSM3302
0
–10
–20
PSRR (dB)
–30
–40
–50
–60
VDD = 5V
VA = 5V
VB = 0V
10198-038
–70
–90
10
100
1k
10k
100k
FREQUENCY (Hz)
10198-033
–80
Figure 35. Turn-On Response
(Showing SDNL Pin or SDNR Pin Rising Edge and Output)
Figure 33. PSRR vs. Frequency, VRIPPLE = 100 mV rms
0
–40
–60
–80
–120
10
10198-039
–100
100
1k
10k
FREQUENCY (Hz)
100k
10198-037
CROSSTALK (dB)
–20
Figure 36. Turn-Off Response
(Showing SDNL Pin or SDNR Pin Falling Edge and Output)
Figure 34. Crosstalk vs. Frequency,
PO = 0.5 W, RL = 8 Ω
Rev. 0 | Page 13 of 20
SSM3302
Data Sheet
TYPICAL APPLICATION CIRCUITS
470µF
PVDD
7V TO 18V
10µF
2× 1µF
OVERTEMPERATURE
WARNING
PVDD
THERM
SSM3302
0.1µF
RIGHT INPUT+
40kΩ
INR+
40kΩ
RIGHT INPUT–
0.1µF
BOOTR+
GAIN
CONTROL
MODULATOR
(Σ-∆)
FET
DRIVER
OUTR–
INR–
BOOTR–
BIAS
SHUTDOWN – RIGHT
0.22µF
OUTR+
0.22µF
SDNR
INTERNAL
OSCILLATOR
MONO
SHUTDOWN – LEFT
BIAS
SDNL
0.1µF
LEFT INPUT+
INL+
0.1µF
BOOTL+
40kΩ
40kΩ
LEFT INPUT–
EDGE
EDGE
CONTROL
EMISSION
CONTROL
0.22µF
OUTL+
GAIN
CONTROL
MODULATOR
(Σ-∆)
FET
DRIVER
OUTL–
INL–
BOOTL–
0.22µF
VREG
VREG/
AVDD
GAIN
RGAIN
REGEN
PGND
5V
2.2µF
GAIN = 9dB, 12dB, 15dB, 18dB, or 24dB
REGULATOR
ENABLE
Figure 37. Stereo Mode Configuration
Rev. 0 | Page 14 of 20
10198-034
GAIN SELECT
AGND
Data Sheet
SSM3302
470µF
PVDD
7V TO 18V
10µF
2× 1µF
OVERTEMPERATURE
WARNING
PVDD
THERM
SSM3302
BOOTR+
40kΩ
INR+
40kΩ
GAIN
CONTROL
MODULATOR
(Σ-∆)
FET
DRIVER
OUTR–
INR–
BOOTR–
BIAS
AVDD
INPUT+
INL+
BIAS
0.1µF
BOOTR+
40kΩ
40kΩ
INPUT–
EDGE
EDGE
CONTROL
INTERNAL
OSCILLATOR
SDNL
0.1µF
0.22µF
SDNR
MONO
SHUTDOWN
0.22µF
OUTR+
EMISSION
CONTROL
0.22µF
OUTR+
GAIN
CONTROL
MODULATOR
(Σ-∆)
FET
DRIVER
OUTR–
INL–
BOOTR–
0.22µF
VREG
VREG/
AVDD
GAIN
GAIN = 9dB, 12dB, 15dB, 18dB, or 24dB
AGND
REGEN
PGND
5V
2.2µF
REGULATOR
ENABLE
Figure 38. Mono Mode Configuration
Rev. 0 | Page 15 of 20
10198-035
GAIN SELECT
RGAIN
SSM3302
Data Sheet
APPLICATIONS INFORMATION
OVERVIEW
AMPLIFIER PROTECTION
The SSM3302 stereo Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external component
count, conserving board space and reducing system cost. The
SSM3302 does not require an output filter; it relies on the inherent
inductance of the speaker coil and the natural filtering of the
speaker and human ear to recover the audio component of the
square wave output.
The SSM3302 includes protection circuitry to prevent damage
in case of overcurrent and overtemperature conditions. Shorts
across the output terminals, or between either terminal and
PVDD or PGND, are also detected; in this case, the output
transistors do not switch until the fault is removed.
Most Class-D amplifiers use some variation of pulse-width
modulation (PWM), but the SSM3302 uses Σ-Δ modulation to
determine the switching pattern of the output devices, resulting in
several important benefits. Unlike pulse-width modulators, Σ-Δ
modulators do not produce a sharp peak with many harmonics in
the AM broadcast band. In addition, Σ-Δ modulation reduces the
amplitude of spectral components at high frequencies, reducing
EMI emission that might otherwise be radiated by speakers and
long cable traces. Due to the inherent spread spectrum nature of
Σ-Δ modulation, the need for oscillator synchronization is eliminated for designs incorporating multiple SSM3302 amplifiers.
The SSM3302 also integrates overcurrent and overtemperature
protection, as well as an overtemperature warning indicator pin.
ANALOG SUPPLY
The SSM3302 includes an integrated low dropout (LDO) linear
regulator to generate a 5 V supply for the input stage. This regulator
can be enabled using the REGEN pin. This analog supply voltage is
available at the VREG/AVDD pin. Connect a 2.2 μF decoupling
capacitor from this pin to the AGND pin.
Alternatively, an external 5 V analog supply can be connected to
the AVDD pin. In this case, tie REGEN low to disable the
internal regulator.
The internal 5 V regulator can supply up to 20 mA of current to
the VREG pin if other analog circuits use the same supply. The
regulator includes short-circuit protection, but no current
limiter or other protection is provided.
GAIN SELECTION
The preset gain of SSM3302 can be selected between 9 dB and
24 dB with one external resistor and no change to the input impedance. Gain can be further adjusted to a user-defined setting by
inserting series external resistors at the inputs. A major benefit
of fixed input impedance is that there is no need to recalculate
the input corner frequency (fc) when gain is adjusted. The same
input coupling components can be used for all gain settings.
Table 5. Gain Function Descriptions
Gain Setting (dB)
GAIN Pin Configuration
24
18
15
12
9
Tie to AVDD
Tie to AVDD through 47 kΩ
Open
Tie to AGND through 47 kΩ
Tie to AGND
If the temperature exceeds the threshold temperature (approximately 145°C), the chip is disabled until the temperature drops
below the recovery threshold (85°C). This hysteresis prevents
rapid cycling of the output at high temperatures.
Additionally, a temperature warning signal is available on the
THERM pin. If the die temperature rises above 120°C, a logic
high is output on this pin.
POP-AND-CLICK SUPPRESSION
Voltage transients at the outputs of the audio amplifiers may occur
when shutdown is activated or deactivated. Voltage transients as
small as 10 mV can be heard as an audible pop in the speaker.
Clicks and pops are defined as undesirable audible transients
generated by the amplifier system that do not come from the
system input signal.
Such transients may be generated when the amplifier system
changes its operating mode. For example, system power-up and
power-down can be sources of audible transients.
The SSM3302 has a pop-and-click suppression architecture that
reduces these output transients, resulting in noiseless activation
and deactivation.
EMI NOISE
The SSM3302 uses a proprietary modulation and spread spectrum
technology to minimize EMI emissions from the device. The
SSM3302 can pass FCC Class-B emissions testing with unshielded
20 inch cable using ferrite bead-based filtering. For applica
tions that have difficulty passing FCC Class-B emission tests, the
SSM3302 includes a modulation select pin (ultralow EMI emission
mode) that significantly reduces the radiated emissions at the
Class-D outputs, particularly above 100 MHz. Note that reducing
the supply voltage greatly reduces radiated emissions.
MONO MODE
The SSM3302 can also be configured to stack its stereo outputs
into a monaural amplifier configuration by enabling the mono
output mode using the MONO pin. The user can drive a load as
small as 2 Ω up to 20 W continuous output power—a particularly
useful feature for driving the subwoofer in a 2.1 audio system.
To activate this operation, pull up the MONO pin to the level of
VREG/AVDD. In mono mode, OUTL+ and OUTR+ (Pin 2/Pin 3
and Pin 28/Pin 29) provide the noninverting output, and OUTL−
and OUTR− (Pin 4/Pin 5 and Pin 26/Pin 27) provide the inverting
output. While the device is in mono mode, audio input is taken
only from the left channel set of inputs: INL+ and INL− (Pin 11
and Pin 12).
Rev. 0 | Page 16 of 20
Data Sheet
SSM3302
Because the mono mode uses output sense circuitry attached to
the left channel outputs, run PCB traces directly from the speaker
to the left channel outputs and then extend the PCB traces to
the right channel outputs.
OUTPUT MODULATION DESCRIPTION
The SSM3302 uses three-level, Σ-Δ output modulation. Each
output can swing from PGND to PVDD and vice versa. Ideally,
when no input signal is present, the output differential voltage is
0 V because there is no need to generate a pulse. In a real-world
situation, however, there are always noise sources present.
Due to this constant presence of noise, a differential pulse is
occasionally generated in response to this stimulus. A small
amount of current flows into the inductive load when the
differential pulse is generated. However, most of the time, the
output differential voltage is 0 V. This feature ensures that the
current flowing through the inductive load is small.
When the user sends an input signal, an output pulse is generated
to follow the input voltage. The differential pulse density is
increased by raising the input signal level. Figure 39 depicts threelevel, Σ-Δ output modulation with and without input stimulus.
OUTPUT = 0V
OUTR+/
OUTL+
+5V
0V
+5V
OUTR–/
OUTL–
0V
+5V
VOUT
0V
–5V
OUTPUT > 0V
OUTR+/
OUTL+
+5V
0V
OUTPUT < 0V
OUTR+/
OUTL+
Properly designed multilayer PCBs can reduce EMI emission
and increase immunity to the RF field by a factor of 10 or more
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.
If the system has separate ground planes for small signal and
high power connections, there should be no overlap between
these planes. Stitch the power plane to the SSM3302 exposed pad
using multiple vias. Proper layout improves heat conduction
into the board, allowing operation at larger output power levels
without overtemperature issues.
Input capacitors are required if the input signal is not biased within
the recommended input dc common-mode voltage range, if
high-pass filtering is needed, or if a single-ended source is used.
If high-pass filtering is needed at the input, the input capacitor
and the input resistor of the SSM3302 form a high-pass filter
with a corner frequency determined by the following equation:
0V
VOUT
To maintain high output swing and high peak output power,
ensure that the PCB traces that connect the output pins to the
load and supply pins are as wide as possible to maintain the
minimum trace resistances. It is also recommended that a large
ground plane be used for minimum impedances. In addition,
good PCB layout isolates critical analog paths from sources of
high interference. High frequency circuits (analog and digital)
should be separated from low frequency circuits.
INPUT CAPACITOR SELECTION
+5V
0V
+5V
OUTR–/
OUTL–
and minimum inductance, ensure that track widths are at least
200 mil for every inch of length and use 1 oz. or 2 oz. copper. Use
large traces for the power supply inputs and amplifier outputs.
Proper grounding guidelines help to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal.
+5V
0V
+5V
OUTR–/
OUTL–
fC = 1/(2π × RIN × CIN)
0V
VOUT
–5V
10198-036
0V
Figure 39. Three-Level, Σ-Δ Output Modulation With and
Without Input Stimulus
The input capacitor can significantly affect the performance of
the circuit. Failure to use input capacitors degrades the output
offset of the amplifier.
BOOTSTRAP CAPACITORS
LAYOUT
As output power increases, care must be taken to lay out PCB traces
and wires properly among the amplifier, load, and power supply;
a poor layout increases voltage drops, consequently decreasing
efficiency. A good practice is to use short, wide PCB tracks to
decrease voltage drops and minimize inductance. For lowest DCR
The output stage of the SSM3302 uses a high-side NMOS driver,
rather than PMOS driver. To generate the gate drive voltage for
the high-side NMOS driver, a bootstrap capacitor for each output
terminal acts as a floating power supply for the switching cycle.
Using 0.22 μF ceramic capacitors with a voltage rating of 6.3 V
or greater is recommended.
Rev. 0 | Page 17 of 20
SSM3302
Data Sheet
POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion, and high
power supply rejection ratio, proper power supply decoupling
is necessary. Noise transients on the power supply lines are
short-duration voltage spikes. These spikes can contain frequency
components that extend into the hundreds of megahertz. Decouple
the power supply input with a good quality, low ESL, low ESR
bulk capacitor larger than 220 μF. This capacitor bypasses low
frequency noises to the ground plane.
For high frequency transient noises, place two separate 1 μF
capacitors as close as possible to the PVDD pins of the device.
Connect one of the 1 μF capacitors between the left-side PVDD
terminals and PGND terminals, and connect the other 1 μF
capacitor between the right-side PVDD terminals and PGND
terminals. Placing the decoupling capacitor as close as possible
to the SSM3302 helps to achieve the best performance.
Rev. 0 | Page 18 of 20
Data Sheet
SSM3302
OUTLINE DIMENSIONS
0.30
0.23
0.18
31
40
30
0.50
BSC
1
0.80
0.75
0.70
0.45
0.40
0.35
10
11
20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
4.45
4.30 SQ
4.25
EXPOSED
PAD
21
TOP VIEW
PIN 1
INDICATOR
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
05-06-2011-A
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
Figure 40. 40-Lead Lead Free Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
SSM3302ACPZ
SSM3302ACPZ-RL
SSM3302ACPZ-R7
EVAL-SSM3302Z
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
40-Lead Lead Free Chip Scale Package [LFCSP_WQ]
40-Lead Lead Free Chip Scale Package [LFCSP_WQ]
40-Lead Lead Free Chip Scale Package [LFCSP_WQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
Package Option
CP-40-10
CP-40-10
CP-40-10
SSM3302
Data Sheet
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10198-0-2/12(0)
Rev. 0 | Page 20 of 20