2.5V/3.3V DUAL 1:5 DIFFERENTIAL LVECL/LVPECL/HSTL CLOCK DRIVER FEATURES ClockWorks™ SY100EP210U DESCRIPTION ■ 2.5V and 3.3V power supply options The SY100EP210U is a high-speed, precision low skew 1-to-5 dual differential clock driver. HSTL inputs can be used when the EP210U is operating in PECL mode. The EP210U specifically guarantees critical AC parameters over temperature and voltage. Optimal design, layout, and processing minimize skew within device and from device-to-device. The SY100EP210U, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the EP210U to be used for high performance clock distribution in +3.3V or +2.5V systems. Single-ended input operation is limited to a VCC ≥ 3.0V in PECL mode, or VEE ≤ –3.0V in ECL mode. Designers can take advantage of the EP210U’s performance to distribute low skew clocks across the backplane or to multiple points on a board. ■ Guaranteed AC parameters over temperature: • fMAX > 3.0GHz • < 35ps within-device skew • < 350ps tr / tf • < 490ps propagation delay (differential) ■ Wide temperature range: –40°C to +85°C ■ Differential design ■ VBB output ■ Fully compatible with industry standard 100K I/O levels ■ Available in 32-pin TQFP Package BLOCK DIAGRAM Qa0 Qb0 /Qa0 /Qb0 Qa1 CLKa 75kΩ /CLKa VEE /Qa1 Qb1 CLKb 75kΩ VEE /Qb1 /CLKb 75kΩ VEE VCC 75kΩ Qa2 VCC VEE 75kΩ 75kΩ /Qa2 Qb2 /Qb2 Qa3 Qb3 /Qa3 /Qb3 Qa4 Qb4 /Qa4 VBB /Qb4 Rev.: A 1 Amendment: /2 Issue Date: August 2001 ClockWorks™ SY100EP210U Micrel Pin VCC /Qa2 PIN NAMES Qa2 Qa1 /Qa1 Qa0 /Qa0 VCC PIN CONFIGURATION VCC 1 32 31 30 29 28 27 26 25 24 NC 2 23 /Qa3 3 22 Qa4 /CLKa 4 21 /Qa4 20 Qb0 Top View TQFP T32-1 18 Qb1 VEE 8 17 9 10 11 12 13 14 15 16 /Qb1 VCC Qb2 7 /Qb2 /Qb0 /CLKb Qb3 19 /Qb3 6 Qb4 5 /Qb4 VBB CLKb VCC CLKa, /CLKa LVPECL, LVECL, HSTL Clock Input: CLKa input includes a 75kΩ pull-down. Default is LOW if left floating. /CLKa includes both pull-up and pull-down resistors. Default condition is VCC/2. CLKb, /CLKb LVPECL, LVECL, HSTL Clock Input: CLKb input includes a 75kΩ pull-down. Default is LOW if left floating. /CLKb includes both pull-up and pull-down resistors. Default condition is VCC/2. Qn0:4, /Qn0:4 LVPECL or LVECL Outputs: Terminate to VCC–2V. (see “Termination” section) VBB Reference Voltage for Single-Ended Inputs: It provides the switching reference for the input differential amplifier. When used, bypass with a 0.0µF capacitor to the most positive reference (usually VCC) as shown in Figure 3. VCC Positive Power Supply: For LVPECL operation, connect VCC to 3.3V or 2.5V. For LVECL operation, connect to GND. Bypass with 0.1µF//0.01µF low ESR capacitors. VEE Negative Power Supply: For LVPECL operation, connect to GND. For LVECL operation, connect to –3.3V or –2.5V. Qa3 CLKa Function ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating VCC — VEE Power Supply Voltage VIN Input Voltage (VCC = 0V, VIN not more negative than VEE) Input Voltage (VEE = 0V, VIN not more positive than VCC) IOUT Output Current IBB VBB Sink/Source Current(2) TA Operating Temperature Range Tstore Storage Temperature Range θJA Package Thermal Resistance (Junction-to-Ambient) θJC Package Thermal Resistance (Junction-to-Case) –Continuous –Surge –Still-Air –500lfpm Value Unit 6.0 V –6.0 to 0 +6.0 to 0 V V 50 100 mA ±0.5 to 0 mA –40 to +85 °C –65 to +150 °C 50 42 °C/W 20 °C/W NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. 2. Use for inputs of same package only. 2 ClockWorks™ SY100EP210U Micrel DC ELECTRICAL CHARACTERISTICS(1) TA = –40°C Symbol Parameter TA = +85°C Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit 2.37 –2.37 — — 3.8 –3.8 2.37 –2.37 — — 3.8 –3.8 2.37 –2.37 — — 3.8 –3.8 V Condition VCC Power Supply Voltage IEE Internal Supply Current — 70 90 — 70 90 — 70 90 mA IIH Input HIGH Current — — 150 — — 150 — — 150 µA VIN = VIH IIL Input LOW Current CLKa, CLKb /CLKa, /CLKb 0.5 –150 — — — — 0.5 –150 — — — — 0.5 –150 — — — — µA µA VIN = 0V VIN = 0V — — — — 2 — — — — pF CIN (LVPECL) (LVECL) TA = +25°C Min. Input Capacitance NOTES: 1. 100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. 3.3V LVPECL DC ELECTRICAL CHARACTERISTICS(1) VCC = 3.3V ±10% TA = –40°C Symbol TA = +25°C TA = +85°C Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit VIH Input HIGH Voltage 2135 — 2420 2135 — 2420 2135 — 2420 mV VIL Input LOW Voltage 1490 — 1675 1490 — 1675 1490 — 1675 mV VOL Output LOW Voltage 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV 50Ω to VCC –2V VOH Output HIGH Voltage 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV 50Ω to VCC –2V 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV 1.2 — VCC 1.2 — VCC 1.2 — VCC mV Voltage(2) VBB Output Reference VIHCMR Input HIGH Voltage Common Mode Range(3) Condition NOTES: 1. 100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. Input and output varies 1:1 with VCC. 2. Single-ended input operation is limited to VCC ≥ 3.0V in LVPECL mode. VBB reference varies 1:1 with VCC. 3. The VIHCMR (Min) varies with VEE. VIHCMR (Max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 2.5V LVPECL DC ELECTRICAL CHARACTERISTICS(1) VCC = 2.5V ±10%, VEE = 0V TA = –40°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition VOL Output LOW Voltage 555 680 895 555 680 895 555 680 895 mV 50Ω to VCC –2V VOH Output HIGH Voltage 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV 50Ω to VCC –2V 1.2 — VCC 1.2 — VCC 1.2 — VCC VIHCMR Voltage(2) Input HIGH Common Mode Range V NOTES: 1. 100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. Input and output varies 1:1 with VCC. 2. The VIHCMR (Min) varies with VEE. VIHCMR (Max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 3 ClockWorks™ SY100EP210U Micrel LVECL DC ELECTRICAL CHARACTERISTICS(1) VEE = –2.375V to –3.8V; VCC = 0V TA = –40°C Symbol Parameter Min. Typ. TA = +25°C Max. Min. Typ. TA = +85°C Max. Min. Typ. Max. Unit Condition VIL Input LOW Voltage (Single-Ended) –1810 — –1625 –1810 — –1625 –1810 — –1625 mV VIH Input HIGH Voltage (Single-Ended) –1165 — –0880 –1165 — –0880 –1165 — –0880 mV VOL Output LOW Voltage –1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695 mV 50Ω to VCC –2V VOH Output HIGH Voltage –1145 –1020 –0895 –1145 –1020 –0895 –1145 –1020 –0895 mV 50Ω to VCC –2V VBB Output Reference Voltage(2) –1525 –1425 –1325 –1525 –1425 –1325 –1525 –1425 –1325 mV VIHCMR Input HIGH Voltage Common Mode Range(3) VEE +1.2 0.0 VEE +1.2 0.0 VEE +1.2 0.0 V NOTES: 1. 100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. 2. Single-ended input operation is limited to VEE ≤ –3.0V in ECL/LVECL mode. VBB reference varies 1:1 with VCC. 3. The VIHCMR (Min) varies with VEE. The VIHCMR range is referenced to the most positive side of the differential input signal. HSTL DC ELECTRICAL CHARACTERISTICS VCC = 2.375V to 3.8V; VEE = 0V TA = –40°C Symbol TA = +25°C TA = +85°C Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit VIH VIL Input HIGH Voltage 1200 — — 1200 — — 1200 — — mV Input LOW Voltage — — 400 — — 400 — — 400 mV VX Input Crossover Voltage 680 — 900 680 — 900 680 — 900 mV 4 Condition ClockWorks™ SY100EP210U Micrel AC ELECTRICAL CHARACTERISTICS (LVPECL) VCC = 2.375 to 3.8V, VEE = 0V; (LVECL) VEE = –2.375V to –3.8V, VCC = 0V TA = –40°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit fMAX Maximum Frequency(1) HSTL/LVPECL 3.0 — — 3.0 — — 3.0 — — GHz tPD Propagation Delay(2) 220 300 380 270 350 430 300 410 490 ps Within-Device Skew — 20 25 — 20 25 — 20 25 ps Skew(4) — 85 160 — 85 160 — 85 160 ps tSKEW (3) Part-to-Part tJITTER Cycle-to-Cycle Jitter (rms) — 0.2 <1 — 0.2 <1 — 0.2 <1 ps(rms) VPP (5) Minimum Input Swing 150 800 1200 150 800 1200 150 800 1200 mV tr, tr Output Rise/Fall Times (20% to 80%) 100 170 250 120 190 270 120 280 350 ps Condition NOTES: 1. fMAX guaranteed for functionality only (toggel frequency). 2. CLK 0 to Bank A and CLK 1 to Bank B; Differential. Maximum propagation delay is worst-case, over temperature and voltage. 3. Skew is measured between outputs under identical transitions. 4. Measured for same transitions. 5. See “Timing Waveform.” TIMING WAVEFORM CLKa/b 150mV to 1200mV /CLKa/b PRODUCT ORDERING CODE Ordering Code Package Type Operating Range Package Marking SY100EP210UTI T32-1 Industrial XEP210U SY100EP210UTITR* T32-1 Industrial XEP210U *Tape and Reel 5 ClockWorks™ SY100EP210U Micrel TYPICAL CHARACTERISTICS Frequency Response vs. Output Amplitude Frequency Response vs. Output Amplitude 900 300 FREQUENCY (MHz) Frequency Response vs. Output Amplitude @2.5V Frequency Response vs. Output Amplitude @3.3V 6 4000 3500 0 FREQUENCY (MHz) 3000 200 100 4000 3500 3000 2500 2000 1500 0 100 1000 200 400 2500 300 500 2000 400 600 1500 500 700 1000 600 VSUP = 3.3V VDIFFIN = 800mV 800 500 700 OUTPUT AMPLITUDE (mV) VSUP = 2.5V VDIFFIN = 800mV 800 500 OUTPUT AMPLITUDE (mV) 900 ClockWorks™ SY100EP210U Micrel TERMINATION RECOMMENDATIONS +3.3V +3.3V ZO = 50Ω R1 130Ω R1 130Ω +3.3V R2 82Ω R2 82Ω Vt = VCC –2V ZO = 50Ω Figure 1. Parallel Termination–Thevenin Equivalent Notes: 1. For +2.5V systems: R1 = 250Ω R2 = 62.5Ω +3.3V +3.3V Z = 50Ω Z = 50Ω 50Ω 50Ω “source” “destination” Rb 46Ω to 50Ω Figure 2. Three-Resistor “Y–Termination” Notes: 1. Power-saving alternative, Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. Rb resistor sets the DC bias voltage, equal to Vt. +3.3V +3.3V Q +3.3V R1 130Ω R1 130Ω ZO = 50Ω +3.3V 50Ω /Q VBB Vt = VCC –2V R2 82Ω 0.01µF R2 82Ω +3.3V Figure 3. Terminating Unused I/O Notes: 1. Unused output (/Q) must be terminated to balance the output. 2. Micrel's differential I/O logic devices include a VBB reference pin . 3. Connect unused input through 50Ω to VBB. Bypass with a 0.01µF capacitor to GND. 4. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω 7 ClockWorks™ SY100EP210U Micrel 32 LEAD THIN QUAD FLATPACK (T32-1) Rev. 01 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB USA http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2001 Micrel Incorporated 8