Data Sheet March 29, 2002 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Features Applications Supports standard OC-192/STM-64 data rate of 9.95328 Gbits/s up through forward error correction (FEC) rate of 10.7092 Gbits/s as well as the Ethernet rate of 10.3125 Gbits/s ■ SONET/SDH optical modules ■ SONET/SDH line origination equipment ■ SONET/SDH add/drop multiplexers ■ Supports clockless data transfer mode ■ SONET/SDH cross connects ■ Supports forward directional clocking for parallel transfer of input data with 311 MHz or 622 MHz clocks ■ SONET/SDH test equipment ■ Digital video transmission ■ ■ Supports contradirectional clocking for parallel transfer of input data based on a 622 MHz output clock ■ Allows a 155.52 MHz or 622.08 MHz reference clock using common phase-locked loop (PLL) loop components ■ Additional 10 Gbits/s current-mode logic (CML) serial data output for system loopback ■ Supports 10 GHz clock output for clocked laser driver applications ■ Loss of lock indication ■ Single 3.3 V supply ■ Low-voltage differential signaling (LVDS) 622.08 Mbits/s signal I/Os ■ CMOS I/Os compatible with low-voltage transistortransistor logic (LVTTL) signaling ■ Power dissipation as low as 1.35 W ■ Available in a 198-ball grid array (CBGA) package ■ Jitter generation/transfer compliant with the following: — Telcordia Technologies™ GR-253 CORE — ITU-T G.825 — ITU-T G.958 Description The Agere Systems Inc. TTRN0110G device provides a 16:1 multiplexer, accepts 16 differential LVDS data inputs and a 155.52 MHz or 622.08 MHz reference clock, and generates a CML 10 Gbits/s clock and data output. Both forward directional and contradirectional clocking schemes are supported for transferring data across the parallel interface. When contraclocking is used, the TTRN0110G provides one of four phases of a 622.08 MHz clock output back upstream to the data chip. The device also supports a clockless parallel data transfer mode. The TTRN0110G can be operated within the standard OC-192/STM-64 data rate of 9.9532 GHz and the FEC rate of 10.7092 Gbits/s. TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Table of Contents Contents Page Features .................................................................................................................................................................... 1 Applications ............................................................................................................................................................... 1 Description.................................................................................................................................................................1 Block Diagram......................................................................................................................................................... 3 Ball Information..........................................................................................................................................................4 Ball Diagram ........................................................................................................................................................... 4 Ball Assignments ....................................................................................................................................................5 Ball Description ....................................................................................................................................................... 7 Functional Overview ................................................................................................................................................11 Ethernet and FEC Rate Support..............................................................................................................................11 Clock Synthesizer Operation ...................................................................................................................................11 Clock Synthesizer Loop Filter ...............................................................................................................................11 Clock Synthesizer Settling Time ...........................................................................................................................12 Loss of Lock Indicator (LCKLOSSN) ....................................................................................................................12 Clock Synthesizer Generated Jitter ......................................................................................................................12 Clock Synthesizer Jitter Transfer ..........................................................................................................................13 Multiplexer Operation ..............................................................................................................................................14 10 GHz Clock Output Enable (ENCK10G)............................................................................................................14 Loopback 10 GHz Data Output (LBDP/N, ENLBDN) ............................................................................................14 Reset (RESETN)...................................................................................................................................................14 Clocking Modes and Timing Adjustments ...............................................................................................................15 Forward Directional 622 Clocking Mode (CLKMOD[1:0] = 00, EXTCNTR, PICLKP/N, OVRFLW) ......................15 Forward Directional 311 Clocking Mode (CLKMOD[1:0] = 10, EXTCNTR, PICLKP/N, OVRFLW) ......................15 Contradirectional Clocking Mode (CLKMOD[1:0] = 01, PHADJ[1:0], EXTCNTR) ................................................16 Clockless Transfer Mode (CLKMOD[1:0]= 11, EXTCNTR) ..................................................................................17 CML Output Structure (Used on Balls D10GP/N, CK10GP/N, LBDP/N).................................................................18 Absolute Maximum Ratings.....................................................................................................................................19 Handling Precautions ..............................................................................................................................................19 Recommended Operating Conditions .....................................................................................................................19 Electrical Characteristics .........................................................................................................................................20 LVDS, CMOS, CML Inputs and Outputs ...............................................................................................................20 Frequency Characteristics.......................................................................................................................................22 Reference Frequency (REFCLKP/N, REFFREQ) (Standard SONET Rate).........................................................22 Reference Frequency (REFCLKP/N, REFFREQ) (FEC Rate) .............................................................................22 Timing Characteristics .............................................................................................................................................23 Transmit Timing ....................................................................................................................................................23 Packaging Characteristics .......................................................................................................................................27 Package Crush Characteristics.............................................................................................................................27 CBGA Package Information..................................................................................................................................27 PWB Design Information.......................................................................................................................................27 Assembly Information ...........................................................................................................................................28 Reference Materials..............................................................................................................................................28 Package Diagram—198-Ball CBGA (Bottom View) ..............................................................................................29 Ordering Information................................................................................................................................................30 2 Agere Systems Inc. TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Description (continued) Block Diagram TO DIGITAL LOGIC D0P D0N RESETN ENLBDN LBDP LBDN 16:1 MULTIPLEXER DATA BUFFER INPUT REGISTER D1P D1N DATA RETIME D10GP D10GN INVDATN D15P D15N CK10GP CK10GN ENCK10G OVERFLOW EXTCNTR RREFCML CLKMOD[1:0] RREFVCO DECODE RREFLVDS PICLKP PICLKN TIMING GENERATION ENCK155N CK155P CK155N DIVIDE BY 4 CK622P CK622N MANUAL PHASE ADJUST DIVIDE BY 16 TEST PHADJ[1:0] 0 REFFREQ PHASE/ FREQ. DETECTOR REFCLKP REFCLKN LCKLOSSN CHARGE PUMP VCO ACQUISITION INDICATOR 1 TESTN TSTCKP FECN LFP LFN 0356.a(F) Note: Diagram is representative of device functionality and conceptual signal flow. Internal implementation details may be different than shown. Figure 1. Functional Block Diagram of TTRN0110G Agere Systems Inc. 3 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Ball Information Ball Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B C D E F G H J K L M N P R TOP VIEW 0642.a(F) Figure 2. TTRN0110G CBGA Ball Diagram (198-ball) 4 Agere Systems Inc. TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Ball Information (continued) Ball Assignments Table 1. Ball Assignments for 198-Ball CBGA by Ball Number Order Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 GND GND GND GND CK10GN GND CK10GP GND D10GN GND D10GP GND GND GND GND GND GND GND GND — GND — GND — GND — GND VCCD GND GND C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 GND GND GND VCCD — GND — — — GND — GND — — TSTCKP LBDP — — — GND — VCCD RREFCML VCCD — GND — GND GND GND E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 GND GND GND GND — GND INVDATN GND TESTN GND GND GND VCCA VCCA LFN LBDN — — — GND GND ENLBDN GND ENCK10G GND GND RREFLVDS VCCA RREFVCO LFP G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 GND GND GND GND VCCD GND GND GND GND GND GND LCKLOSSN — VCCD VCCA VCCD GND GND — GND GND GND GND GND GND GND GND GND RESETN CLKMOD[0] Note: — refers to no ball. A ball has been removed for routing purposes. Agere Systems Inc. 5 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Ball Information (continued) Ball Assignments (continued) Table 1. Ball Assignments for 198-Ball CBGA by Ball Number Order (continued) Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 D0P GND GND GND VCCD VCCD GND GND GND GND GND GND VCCD OVRFLW CLKMOD[1] D0N GND GND GND — GND GND GND VCCD GND VCCD — ENCK155N FECN EXTCNTR L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 D1P GND GND GND GND VCCD GND VCCD — GND GND GND GND PHADJ[1] REFFREQ D1N GND D4P GND D7P GND GND — GND D15P GND GND GND REFCLKN PHADJ[0] N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 D2P D3P D4N GND D7N GND D10N D12P GND D15N GND GND GND REFCLKP GND D2N D3N GND D6P D8P D9P D10P D12N D13N D14N CK155N PICLKN CK622N GND GND R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 GND D5P D5N D6N D8N D9N D11P D11N D13P D14P CK155P PICLKP CK622P GND GND Note: — refers to no ball. A ball has been removed for routing purposes. 6 Agere Systems Inc. TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Ball Information (continued) Ball Description Note: In Table 2, when operating the TTRN0110G device at the OC-192/STM-64 rate, 10 Gbits/s should be interpreted as 9.9532 Gbits/s. When operating the TTRN0110G device at the Ethernet rate, 10 Gbits/s should be interpreted as 10.3125 Gbits/s. When operating the TTRN0110G device at RS FEC OC-192/ STM64 rates, 10 Gbits/s should be interpreted as 10.6642 Gbits/s or 10.7092 Gbits/s. Table 2. Ball Descriptions—10 Gbits/s and Related Signals Ball Symbol* Type† Level A11 A9 D10GP D10GN O CML Name/Description Data Output (10 Gbits/s NRZ). 10 Gbits/s differential data output. Note: This data rate will scale when operating at different rates. D1 F1 LBDP LBDN O CML A7 A5 CK10GP CK10GN O CML FECN u Loopback Data Output. Additional 10 Gbits/s differential data output for system loopback. Note: This data rate will scale when operating at different rates. K14 Clock Output (10 GHz). 10 GHz differential clock output. Note: This clock rate will scale when operating at different rates. I CMOS FEC Rate (Active-Low). Selects between two operating rate ranges within the OC-192/STM-64 rate of 9.9532 GHz and the FEC rate of 10.7092 GHz. 0 = Will extend the operating range out to the FEC rate of 10.7092 GHz. 1 or no connection = OC-192/STM-64 rate of 9.9532 GHz to the Ethernet rate of 10.3 GHz. Note: All input and output SONET/SDH clock and data rates will scale when operating at different rates. D8 RREFCML I Analog Resistor Reference CML. CML current bias reference resistor. F9 ENCK10G Iu CMOS Enable CK10GP/N Clock Output. 0 = CK10GP/N buffer powered off. 1 or no connection = CK10GP/N buffer enabled. F7 ENLBDN Iu CMOS Enable LBDP/N Data Output (Active-Low). 0 = LBDP/N buffer enabled. 1 or no connection = LBDP/N buffer powered off. E7 INVDATN Iu CMOS Invert D10G Data Output (Active-Low). 0 = Invert. 1 or no connection = Noninvert. C15 TSTCKP It CML E9 TESTN Iu CMOS Select Test Clock (Active-Low). 0 = Select test clock. 1 or no connection = Select VCO. F14 RREFVCO I Analog Resistor Reference VCO. VCO bias reference resistor. Connect an 806 kΩ resistor to VCCD. Test Clock Input. (Buffer is powered down when TESTN = 1.) * Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low. † I = input, O = output. Iu indicates an internal pull-up resistor on this pin. Id indicates an internal pull-down resistor on this pin. It = an internal termination resistance of 50 Ω to VCCD on this pin. Agere Systems Inc. 7 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Ball Information (continued) Ball Description (continued) Note: In Table 3, when operating the TTRN0110G device at the OC-192/STM-64 rate, 622 Mbits/s and 155 Mbits/s should be interpreted as 622.08 Mbits/s and 155.52 Mbits/s, respectively. When operating the TTRN0110G device at the Ethernet rate, 622 Mbits/s and 155 Mbits/s should be interpreted as 641.52 Mbits/s and 166.63 Mbits/s, respectively. When operating the TTRN0110G device at the RS FEC OC-192/STM-64 rates, 622 Mbits/s and 155 Mbits/s should be interpreted as 669.33 Mbits/s and 167.33 Mbits/s, respectively. Table 3. Ball Descriptions—622.08 Mbits/s and Related Signals Ball Symbol* Type† Level M10 N10 R10 P10 R9 P9 N8 P8 R7 R8 P7 N7 P6 R6 P5 R5 M5 N5 P4 R4 R2 R3 M3 N3 N2 P2 N1 P1 L1 M1 J1 K1 D15P D15N D14P D14N D13P D13N D12P D12N D11P D11N D10P D10N D9P D9N D8P D8N D7P D7N D6P D6N D5P D5N D4P D4N D3P D3N D2P D2N D1P D1N D0P D0N I LVDS Name/Description Data Input (622 Mbits/s). 622 Mbits/s differential data input. D15 is the most significant bit and is transmitted first on the D10GP/N output. Note: This data rate will scale when operating at different rates. * Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low. † I = input, O = output. Iu indicates an internal pull-up resistor on this pin. Id indicates an internal pull-down resistor on this pin. It = an internal termination resistance of 50 Ω to VCCD on this pin. 8 Agere Systems Inc. TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Ball Information (continued) Ball Description (continued) Table 3. Ball Descriptions—622.08 Mbits/s and Related Signals (continued) Ball Symbol* Type† Level R13 P13 CK622P CK622N O LVDS M15 L14 PHADJ[0] PHADJ[1] Id CMOS Phase Adjust. Adjusts phase of CK622 in 90 degree steps. R11 P11 CK155P CK155N O LVDS K13 ENCK155N Iu CMOS Enable CK155P/N Clock Output (Active-Low). 0 = CK155P/N buffer enabled. 1 or no connection = CK155P/N buffer powered off. R12 P12 PICLKP PICLKN I LVDS H15 J15 CLKMOD[0] CLKMOD[1] u I CMOS Clock Mode Select. Selects clocking method for data transfer mode. [0] [1] 0 0 = Forward directional clocking mode (622 MHz). 0 1 = Forward directional clocking mode (311 MHz). 1 0 = Contraclocking mode. 1 1 or no connections = Clockless mode. G12 LCKLOSSN O CMOS Loss of Lock (Active-Low). 0 = PLL out of lock. K15 EXTCNTR Id CMOS External Center. Centers the pointers in the parallel data storage element. Connected to OVRFLW for fastest FIFO overrun recovery. J14 OVRFLW O CMOS Data Storage Overflow. Indicates (active-high) when an overflow has occurred in the parallel data storage element. N14 M14 REFCLKP REFCLKN I LVDS L15 REFFREQ Iu CMOS Reference Clock Frequency. Selects frequency of REFCLKP/N. 0 = 155 MHz. 1 or no connection = 622 MHz. F15 E15 LFP LFN I Analog Loop Filter PLL. Connect LFP and LFN to loop filter (see Table 6 on page 11). F12 RREFLVDS I Analog Resistor Reference LVDS. LVDS bias reference resistor. Connect a 1.5 kΩ resistor to VCCD. Name/Description Clock Output (622 MHz). 622 MHz differential clock output. Note: This clock frequency will scale when operating at different rates. Clock Output (155 MHz). 155 MHz differential clock output. Note: This clock frequency will scale when operating at different rates. Parallel Input Clock (622 MHz 311 MHz). 622 MHz or 311 MHz differential clock input used to register parallel data when using forward directional clocking mode. Note: This clock frequency will scale when operating at different rates. Reference Clock Input (622.08 MHz or 155.52 MHz). Note: This clock frequency will scale when operating at different rates. * Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low. † I = input, O = output. Iu indicates an internal pull-up resistor on this pin. Id indicates an internal pull-down resistor on this pin. It = an internal termination resistance of 50 Ω to VCCD on this pin. Agere Systems Inc. 9 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Ball Information (continued) Ball Description (continued) Table 4. Ball Descriptions—Reset Ball H14 Symbol* Type† Level RESETN u CMOS I Name/Description Reset (Active-Low). Resets all synchronous logic. During a reset, the true data outputs are in the low state and the barred data outputs are in the high state. Reset must be held active low for a minimum of 6.4 ns while the internal oscillator is active. 0 = Reset. 1 or no connection = Normal operation. * Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low. † I = input, O = output. Iu indicates an internal pull-up resistor on this pin. Id indicates an internal pull-down resistor on this pin. It = an internal termination resistance of 50 Ω to VCCD on this pin. Table 5. Ball Descriptions—Power and Ground Note: VCCA and VCCD have the same dc value, which is represented as VCC unless otherwise specified. However, high-frequency filtering is suggested between the individual supplies. Ball Symbol* Type† Level E13, E14, F13, G15 VCCA I Power Analog Power Supply (3.3 V). B13, C4, D7, D9, G5, G14, H1, J5, J6, J13, K9, K11, L6, L8 VCCD I Power Digital Power Supply (3.3 V). A1—A4, A6, A8, A10, A12—A15, B1—B4, B6, B8, B10, B12, B14, B15, C1—C3, C6, C10, C12, D5, D11, D13—D15, E1—E4, E6, E8, E10—E12, F5, F6, F8, F10, F11, G1—G4, G6—G11, H2, H3, H5—H13, J2—J4, J7—J12, K2—K4, K6—K8, K10, L2—L5, L7, L10—L13, M2, M4, M6, M7, M9, M11—M13, N4, N6, N9, N11—N13, N15, P3, P14, P15, R1, R14, R15 GND I Ground Ground. Name/Description * Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low. † I = input, O = output. Iu indicates an internal pull-up resistor on this pin. Id indicates an internal pull-down resistor on this pin. It = an internal termination resistance of 50 Ω to VCCD on this pin. 10 Agere Systems Inc. Data Sheet March 29, 2002 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Functional Overview Clock Synthesizer Operation The TTRN0110G performs the clock synthesis and 16:1 data multiplexing operations required to support 10 Gbits/s1 OC-192/STM-64 applications compliant with Telcordia Technologies and ITU standards. Parallel 622 Mbits/s data is clocked into an input register. Both forward directional and contradirectional clocking modes are supported as well as a clockless data transfer mode. The data is then multiplexed into a 10 Gbits/s serial stream and output buffered for interfacing to a laser driver. A 10 GHz clock is synthesized from a reference clock and is used to retime the serial data. The 10 GHz clock is optionally available as an output. The clock synthesizer uses a PLL to synthesize a 10 GHz clock from a reference frequency. A 622 MHz clock derived from the 10 GHz synthesized clock may be used to clock in the parallel data in contradirectional clocking applications. Ethernet and FEC Rate Support Table 6. Clock Synthesizer Loop Filter Component Values The TTRN0110G will support both the normal OC-192/ STM-64 rate of 9.9532 GHz and the forward error correction (FEC) rate of 10.7092 GHz. The FECN pin selects the rate range at which the part is operated. Throughout this document, the specifications are given in terms of the normal operating rate only. All frequency-based specifications are to be multiplied by the appropriate scaling factor when not operating at the OC-192/STM-64 rate. All time-based specifications, with the exception of electrical signal rise and fall times, are also to be multiplied by the appropriate scaling factor. For example, a reference clock would need to be applied at 167.33 MHz or 669.32 MHz (a multiplication factor of 255/237), for the parallel data interface to operate at 669.32 MHz when FECN = 0. Clock Synthesizer Loop Filter A typical loop filter that provides adequate damping for less than 0.1 dB of jitter peaking is shown in Table 6. Connect the filter components to LFP and LFN. The component values can be varied to adjust the loop dynamic response (see Table 6). Components Values for 8 MHz Loop Bandwidth C1* 0.15 µF ± 10% C2, C3 ~1 pF† R1 3 kΩ ± 5% * Capacitor C1 should be either ceramic or nonpolar. † This value is the composite of any physical capacitance in addition to any parasitic capacitance. These capacitors are by default not populated. LFP LFN C1 C2 VCCA R1 C3 VCCA 2249(F) Figure 3. Clock Synthesizer Loop Filter Components 1. The OC-192/STM-64 data rate of 9.95328 Gbits/s is typically approximated as 10 Gbits/s in this document when referring to the application rate. Similarly, the low-speed parallel interface data rate of 622.08 Mbits/s is typically approximated as 622 Mbits/s. The exact frequencies are used only when necessary for clarity. Agere Systems Inc. 11 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Clock Synthesizer Operation (continued) Clock Synthesizer Settling Time The clock synthesizer will acquire phase/frequency lock after a valid REFCLKP/N signal is applied. The actual time to acquire lock is a function of the loop bandwidth selected. The loop will acquire lock within 5 ms when using the external loop bandwidth components corresponding to a corner of less than 8 MHz. Loss of Lock Indicator (LCKLOSSN) The LCKLOSSN pin indicates (active-low) when the clock synthesizer has exceeded phase-lock limits with the incoming REFCLKP/N phase. The lock detect function compares the phases of the input 155 MHz or 622 MHz clock at the REFCLKP/N pins with the internally generated 622 MHz output clock at the CK622P/N pin. When the phase difference in the two signals is close to zero, as determined by a second internal phase detector and filter, the lock detect signal LCKLOSSN is set to a logic high. When the phase difference between the two signals is changing at a rate exceeding the filter's cut-off frequency, the TTRN0110G is declared out of lock and LCKLOSSN is set to a logic low. If a set of highly damped phase-locked loop parameters is chosen, LCKLOSSN may exhibit more than one positive edge transition during the acquisition process before a steady logic-high state is achieved. Upon a transition from the out-of-lock condition to the in-lock condition, the parallel data storage element pointers are centered. Clock Synthesizer Generated Jitter The clock synthesizer’s generated jitter performance meets the requirements shown in Table 7. These specifications apply to the jitter generated at the 10 GHz clock pins CK10GP/N when the jitter on the reference clock REFCLKP/N is within the specifications given in Table 12 on page 20 or Table 18 on page 22, and the loop filter components are chosen to provide a loop bandwidth of less than 8 MHz. Table 7. Clock Synthesizer Generated Jitter Specifications Parameter Generated Jitter (p-p) SONET Rate: Measured with 50 kHz to 80 MHz Bandpass Filter 1 UI = 1/9.95328 GHz Generated Jitter (p-p) FEC Rate: Measured with 53.6 kHz to 85.7 MHz Bandpass Filter 1 UI = (14/15)(9.95328 GHz) Typical Max (Device)* Unit 0.050 0.090 UIp-p 0.050 0.090 UIp-p * This denotes the device specification for system SONET/SDH compliance when the loop filter in Table 6 and Figure 3 is used while meeting the transfer jitter bandwidth of 8 MHz. 12 Agere Systems Inc. TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Clock Synthesizer Operation (continued) Clock Synthesizer Jitter Transfer The clock synthesizer’s jitter transfer performance meets the requirement shown in Figure 4 when the loop filter values shown in Table 6 on page 11 are used. 10 (8 MHz, 0.1 dB) JITTER OUT/JITTER IN (dB) 0 –10 –20 –30 –40 –50 –60 0.001 0.01 0.1 1 10 100 FREQUENCY (MHz) 2250(F) Figure 4. Clock Synthesizer Jitter Transfer Agere Systems Inc. 13 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Multiplexer Operation The parallel 622 Mbits/s data is clocked into an input buffer, then clocked into a 16:1 multiplexer. The relationship between the parallel D[15:0]P/N input data and the serial output data D10GP/N is given in Figure 5. The D15 bit is the most significant bit (MSB) and is shifted out first in time in the serial output stream. D15 (MSB) D14 D1 (D15 SERIALLY SHIFTED OUT FIRST) D0 (LSB) D15 (D0 SERIALLY SHIFTED OUT LAST) TIME 5-8063(F) Figure 5. Parallel Input to Serial Output Data Relationship 10 GHz Clock Output Enable (ENCK10G) The 10 GHz CML clock output CK10GP/N may be disabled by setting the ENCK10G pin to logic low. ENCK10G is an active-high CMOS input with an internal pull-up resistor so the default condition will enable the CK10GP/N output and a ground or logic-low signal must be applied to disable the CK10GP/N output. When disabled, the CK10GP/N pins should either be left floating or be connected to a load, which returns to VCC. The output must not be connected directly to ground when it is disabled. Loopback 10 GHz Data Output (LBDP/N, ENLBDN) An alternate 10 Gbits/s CML data output is available on the LBDP/N pin. This pin is provided for use in system loopback testing and avoids the need for off-chip signal splitting of the data signal path. Setting the ENLBDN pin to logic-low will enable the alternate 10 Gbits/s loopback data output. ENLBDN enable is an active-low CMOS input with an internal pull-up resistor so the default condition will disable the LBDP/N output, and a ground or logic-low signal must be applied to enable the loopback output. When disabled, the LBDP/N pin should either be left floating, or be connected to a load which returns to VCC. The output must not be connected directly to ground when it is disabled. Reset (RESETN) The RESETN signal must be held active-low for a minimum of 6.4 ns when the internal VCO is active and running, in order for the internal logic to be completely reset. 14 Agere Systems Inc. Data Sheet March 29, 2002 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Clocking Modes and Timing Adjustments The TTRN0110G supports four timing modes for the 622 Mbits/s data input: forward directional 622, forward directional 311, contradirectional, and clockless transfer, as selected by the CLKMOD[1:0] pins. Forward Directional 622 Clocking Mode (CLKMOD[1:0] = 00, EXTCNTR, PICLKP/N, OVRFLW) In forward directional 622 clocking mode (CLKMOD[1:0] = 00), data is clocked into a 16-bit wide input register on the TTRN0110G device by the PICLKP/N parallel input clock. The setup and hold times for the data relative to PICLK are given in Figure 8 on page 23 and Table 19 on page 25. An internal data buffer is used to absorb timing drift between PICLK and the internal clocks derived from the 10 GHz internal oscillator. A PICLK phase drift of up to ±2400 ps relative to the internal clocks can be absorbed by the buffer, as long as the bandwidth of this phase drift is less than 500 kHz. Note that the read and write addresses for the data buffer must be initially reset in order for the buffer to absorb the full range of PICLK phase drift. The read and write addresses for the data buffer are reset at the time the PLL acquires lock and the loss-oflock indicator transitions from the out-of-lock condition to the in-lock condition. After LCKLOSSN goes high, the buffer will be centered and data integrity will be obtained within approximately 2 µs. The data buffer can also be recentered by applying EXTCNTR (active-high) for a minimum of 6.4 ns. After EXTCNTR goes low, the buffer will be centered and data integrity will be lost and subsequently restored within approximately 2 µs. If the timing drift exceeds ±2400 ps, the data buffer will indicate overflow with a logic-high signal on the OVRFLW pin for a minimum of 6.4 ns. After a time interval of 4.8 ns after OVRFLW goes low, the buffer will be recentered and data integrity will be lost and subsequently restored within approximately 2 µs. During the 11.2 ns between the rising edge of OVRFLW and the recentering of the buffer, data integrity may be lost if the timing drift exceeds ±2000 ps. Forward Directional 311 Clocking Mode (CLKMOD[1:0] = 10, EXTCNTR, PICLKP/N, OVRFLW) In forward directional 311 clocking mode (CLKMOD[1:0] = 10), data is clocked into a 16-bit wide input register on the TTRN0110G device by the PICLKP/N parallel input clock. In contrast to forward directional 622 mode, the PICLK signal is at half the data rate (311 MHz instead of 622 MHz). The setup and hold times for the data relative to PICLK are given in Figure 9 on page 23 and Table 19 on page 25. An internal data buffer is used to absorb timing drift between PICLK and the internal clocks derived from the 10 GHz internal oscillator. A PICLK phase drift of up to ±2400 ps relative to the internal clocks can be absorbed by the buffer, as long as the bandwidth of this phase drift is less than 500 kHz. Note that the read and write addresses for the data buffer must be initially reset in order for the buffer to absorb the full range of PICLK phase drift. The read and write addresses for the data buffer are reset at the time the PLL acquires lock and the loss-oflock indicator transitions from the out-of-lock condition to the in-lock condition. After LCKLOSSN goes high, the buffer will be centered and data integrity will be obtained within approximately 2 µs. The data buffer can also be recentered by applying EXTCNTR (active-high) for a minimum of 6.4 ns. After EXTCNTR goes low, the buffer will be centered and data integrity will be lost and subsequently restored within approximately 2 µs. If the timing drift exceeds ±2400 ps, the data buffer will indicate overflow with a logic-high signal on the OVRFLW pin for a minimum of 6.4 ns. After a time interval of 4.8 ns after OVRFLW goes low, the buffer will be recentered and data integrity will be lost and subsequently restored within approximately 2 µs. During the 11.2 ns between the rising edge of OVRFLW and the recentering of the buffer, data integrity may be lost if the timing drift exceeds ±2000 ps. If the output clock CK622P/N is not used when in CLKMOD[1:0] = 10, it can be left unconnected to conserve power. If the output clock CK622P/N is not used when in CLKMOD[1:0] = 00, it can be left unconnected to conserve power. Agere Systems Inc. 15 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Clocking Modes and Timing Adjustments (continued) Contradirectional Clocking Mode (CLKMOD[1:0] = 01, PHADJ[1:0], EXTCNTR) In the contradirectional clocking mode (CLKMOD[1:0] = 01), the TTRN0110G device sends a 622 MHz clock with one of four user-selectable phases out to the upstream device for clocking the data toward the TTRN0110G. The user can program PHADJ[1:0] to adjust the phase of CK622P/N as a function of printed wiring board (PWB) layout and upstream device propagation delay in order to meet the setup and hold time of the 622 Mbits/s data input to the TTRN0110G. PHADJ[1:0] changes the phase of the CK622P/N clock without changing the input data sampling time. PHADJ[1:0] setting information is given in Table 8, and the phase relationship of CK622P/N for each PHADJ[1:0] setting is shown in Figure 6. Table 8. PHADJ Settings for CK622 Output Clock (Contraclocking Mode) Input Pins Phase PHADJ[1] PHADJ[0] 0 0 1 1 0 1 0 1 0 (See part A of Figure 6.) –270 (See part D of Figure 6.) –180 (See part C of Figure 6.) –90 (See part B of Figure 6.) In this mode, the TTRN0110G input data still passes through the data buffer described in the forward directional clocking sections; however, there will no longer be any phase drift or overflow since the CK622P/N output serves as the master clock for the upstream device. The read and write addresses for the data buffer are initially reset at the time the PLL acquires lock and the loss-of-lock indicator transitions from the out-of-lock condition to the inlock condition. After LCKLOSSN goes high, the buffer will be recentered and data integrity will be obtained within approximately 2 µs. A. (0 DEG.) B. (–90 DEG.) C. (–180 DEG.) D. (–270 DEG.) TIME 5-8064(F) Figure 6. CK622 Phase Relation vs. PHADJ Setting 16 Agere Systems Inc. Data Sheet March 29, 2002 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Clocking Modes and Timing Adjustments (continued) Clockless Transfer Mode (CLKMOD[1:0]= 11, EXTCNTR) In clockless transfer mode (CLKMOD[1:0] = 11), data may be sent to the TTRN0110G device without providing PICLKP/N. An internal delay-locked loop (DLL) automatically produces a 622 MHz clock that is aligned to the parallel data based on the phase of the D0P/N data input. The skew of all data bits D[15:1]P/N relative to D0P/N must be less than 650 ps, as shown in Figure 11 on page 24. An internal data buffer is used to absorb timing drift between D0 and the internal clocks derived from the 10 GHz internal oscillator. A D0 phase drift of up to ±1600 ps relative to the internal clocks can be absorbed by the buffer, as long as the bandwidth of this phase drift is less than 500 kHz. Note: The read and write addresses for the data buffer must be initially reset in order for the buffer to absorb the full range of D[15:0]P/N phase drift. The read and write addresses for the data buffer are reset at the time the PLL acquires lock and the loss-of-lock indicator transitions from the out-of-lock condition to the in-lock condition. After LCKLOSSN goes high, the buffer will be centered and data integrity will be obtained within approximately 2 µs. The data buffer can also be recentered by applying EXTCNTR (active-high) for a minimum of 6.4 ns. After EXTCNTR goes low, the buffer will be centered and data integrity will be lost and subsequently restored within approximately 2 µs. If the timing drift exceeds ±1600 ps, the data buffer will indicate overflow with a logic-high signal on the OVRFLW pin for a minimum of 6.4 ns. After a time interval of 4.8 ns after OVRFLW goes low, the buffer will be recentered and data integrity will be lost and subsequently restored within approximately 2 µs. During the 11.2 ns between the rising edge of OVRFLW and the recentering of the buffer, data integrity may be lost if the timing drift exceeds ±2000 ps. If the output clock CK622P/N is not used when in CLKMOD[1:0] = 11, it can be left unconnected to conserve power. Because the clockless data transfer mode uses the transitions on the D0 data bit as a phase reference for clocking the data, a constraint of a maximum number of consecutive zeros of less than 128 data periods is placed on the D0 bit when operating in the clockless data transfer mode. Agere Systems Inc. 17 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 CML Output Structure (Used on Outputs D10GP/N, CK10GP/N, LBDP/N) The CML architecture is essentially a current-steering mechanism combined with an amplifier. This makes the output swing of the signal a function of the termination resistor and the output current. The on-chip, 50 Ω termination resistor provides a back termination and the output may be direct or ac-coupled to the load. For the direct coupled case, the 50 Ω load should be referenced to the positive 3.3 V supply, VCCD. This will ensure dc levels that comply with the limits set. VTT VTT DEVICE-INTERNAL CML OUTPUT BUFFER CIRCUIT 50 Ω VCCD 50 Ω 50 Ω 50 Ω C + EXTERNAL OUTPUT TERMINATION INPUT SIGNAL – C ENABLE VCCD IOUT NOTE: SHOWN FOR ac COUPLING WHERE VTT MAY BE EITHER VCCD OR GND; DIRECT COUPLING MAY ALSO BE USED, BUT VTT MUST BE VCCD. IREF RREFCML 3 kΩ + VREF – X 2251(F) Figure 7. Typical CML Output Structure 18 Agere Systems Inc. TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 9. Absolute Maximum Ratings Parameter Power Supply Voltage (VCC) Storage Temperature Pin Voltage Min Max Unit GND – 0.5 –40 GND – 0.5 VCC + 0.5 125 VCC + 0.5 V °C V Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Agere Systems employs a human-body model (HBM) and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in the defined model. No industrywide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. Table 10. Handling Precautions Device Voltage Model TTRN0110G ≥200 V ≥200 V HBM (human-body model) CDM (charged-device model) Note: All LVDS, CMOS, and analog pins have an ESD HBM threshold of ≥2,000 V. Recommended Operating Conditions Table 11. Recommended Operating Conditions Parameter Power Supply (dc voltage) Temperature: Case Power Dissipation: D10G Active, CK10G Disabled, LBD Disabled, CLK Disabled Power Dissipation: D10G Active, CK10G Active, LBD Disabled, CLK Disabled Power Dissipation: D10G Active, CK10G Active, LBD Active, CLK Disabled Power Dissipation: D10G Active, CK10G Active, LBD Active, CLK Active Agere Systems Inc. Symbol Min Typ Max Unit VCCD, VCCA TC 3.135 0 3.3 25 3.465 85 V °C PD 1.25 1.35 1.45 W PD 1.50 1.65 1.75 W PD 1.70 1.90 2.05 W PD 1.80 1.95 2.10 W 19 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Electrical Characteristics LVDS, CMOS, CML Inputs and Outputs Notes: 1. For Table 12 through Table 16, VCC = 3.3 V ± 5%, TC = 0 °C to 85 °C. 2. For more information on interpreting CML specifications, see the CML Output Structure (Used on Outputs D10GP/N, CK10GP/N, LBDP/N) section on page 18. Table 12. LVDS Input dc Characteristics Applicable Pins Symbol D[15:0]P/N, REFCLKP/N PICLKP/N VCM VDIFF RIN Parameter Conditions Min Typ Max Unit Input Common-mode Voltage Range Avg(VIA,VIB)† 0 1200 2400 mV Input Peak Differential Voltage |VIA – VIB| 100 — 800 mV f = 622.08 MHz 80 100 120 Ω Differential Input Impedance* * Looser than ICORE/IEEE ® spec of ±10 Ω. † VIA,VIB represent P and N differential pins. Table 13. LVDS Output dc Characteristics Applicable Pins Symbol CK622P/N, CK155P/N VOH VOL Conditions Min Typ Max Unit Output Voltage High, VOA or VOB RLOAD = 100 Ω ± 1% — — 1475 mV Output Voltage Low, VOA or VOB RLOAD = 100 Ω ± 1% 925 — — mV |VOD| Output Differential Voltage† RLOAD = 100 Ω ± 1% 250 — 400 mV VOS Output Offset Voltage RLOAD = 100 Ω ± 1% 1125 — 1275 mV RO Differential Output Impedance Vcm = 1.0 V and 1.4 V 80 100 280 Ω RO Mismatch Between A and B Vcm = 1.0 V and 1.4 V — — 20 % ∆RO Parameter |∆VOD| Change in |VOD| Between Logic 0 and Logic 1 RLOAD = 100 Ω ± 1% — — 25 mV |∆VOS| Change in |VOS| Between Logic 0 and Logic 1 RLOAD = 100 Ω ± 1% — — 25 mV ISA, ISB Output Current Driver shorted to GND — — 24 mA ISAB Output Current Drivers shorted together — — 12 mA — — — —* mA |IXA|,|IXB| Power-off Output Leakage * This leakage parameter is not specified due to EDS clamp diode conducting current during forward bias test. † This voltage is measured on each P/N output. 20 Agere Systems Inc. TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Electrical Characteristics (continued) LVDS, CMOS, CML Inputs and Outputs (continued) Table 14. CMOS Input dc Characteristics Applicable Pins Symbol RESETN, FECN, CLKMOD[1:0], REFFREQ, ENCK10G, ENLBDN, ENCK155N, TESTN PHADJ[1:0], EXTCNTR VIH VIL IIH IIL VIH VIL IIH IIL Parameter Conditions Min Max Unit Input Voltage High Input Voltage Low Input Current High Leakage Input Current Low Leakage — — VIN = VCC VIN = GND VCC – 1.0 GND — –225 VCC 1.0 10 — V V µA µA Input Voltage High Input Voltage Low Input Current High Leakage Input Current Low Leakage — — VIN = VCC VIN = GND VCC – 1.0 GND — –10 VCC 1.0 225 — V V µA µA Conditions Min Max Unit IOH = –4.0 mA IOL = 4.0 mA — VCC – 0.5 GND — VCC 0.5 15 V V pF Table 15. CMOS Output dc Characteristics Applicable Pins Symbol LCKLOSSN OVRFLW VOH VOL Cl Parameter Output Voltage High Output Voltage Low Output Load Capacitance Table 16. CML Input Characteristics Applicable Pins Symbol Parameter Conditions Min Typ Max Unit TSTCLKP VAMP1 RLOSS RLOSS Single-ended Input Amplitude Input Return Loss Input Return Loss — At 10 GHz At <7 GHz 200 12 15 – 12 15 1000 — — mV dB dB Agere Systems Inc. 21 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Frequency Characteristics Reference Frequency (REFCLKP/N, REFFREQ) (Standard SONET Rate) The device requires a 155.52 MHz or a 622.08 MHz differential LVDS reference clock input. Table 17 provides the characteristics of the REFCLKP/N input. Table 17. Reference Frequency Characteristics (Standard SONET) Parameter Min Typ Max Unit Reference Frequency (REFCLKP/N): When REFFREQ = 0 When REFFREQ = 1 — — 155.52 622.08 — — MHz MHz Duty Cycle 40 50 60 % Phase Jitter* — — 0.750 ps(rms) 0 25 85 °C 3.15 — 3.45 V Temperature† Supply Voltage ‡ * Measured under one 3.3 V LVDS load. Includes frequency components up to 8 MHz. Assumes ≤0.500 ps for the device and ≤0.100 ps for laser driver and optics for a total rms jitter performance of less than 0.01 UI. † Specified range is to be compatible with environmental specification of TTRN0110G. Applications requiring a reduced temperature range may specify the reference frequency oscillator accordingly. Reference Frequency (REFCLKP/N, REFFREQ) (FEC Rate) The device requires a (255/237)155.52 MHz or a (255/237)622.08 MHz differential LVDS reference clock input. Table 18 provides the characteristics of the REFCLKP/N input. Table 18. Reference Frequency Characteristics (FEC Rate) Parameter Min Typ Max Unit Reference Frequency (REFCLKP/N): When REFFREQ = 0 When REFFREQ = 1 — — (255/237)155.52 (255/237)622.08 — — MHz MHz Duty Cycle 40 50 60 % — — 0.750 ps(rms) 0 — 85 °C 3.15 — 3.45 V Phase Jitter * Temperature† Supply Voltage ‡ * Measured under one 3.3 V LVDS load. Includes frequency components up to 8 MHz. Assumes ≤0.500 ps for the device and ≤0.100 ps for laser driver and optics for a total rms jitter performance of less than 0.01 UI. † Specified range is to be compatible with environmental specification of TTRN0110G. Applications requiring a reduced temperature range may specify the reference frequency oscillator accordingly. 22 Agere Systems Inc. TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Timing Characteristics Note: All timing diagrams involving differential signals represent the positive signal as a solid line and the negative signal as a dashed line. This is especially important when referencing the rising or falling edge of a differential signal. Transmit Timing Figure 8 shows the required timing relationships between the input clock PICLKP/N and the input data D[15:0]P/N in forward directional 622 clocking mode. tPERIOD INPUT PICLKP/N (622 MHz) tSU INPUTS D[15:0]P/N (622 Mbits/s) tHOLD DATA 1 DATA 2 2252(F) Figure 8. Transmit Timing Waveforms (Forward Directional 622 Clocking Mode) Figure 9 shows the timing relationships between the input clock PICLKP/N and the input data D[15:0]P/N in forward directional 311 clocking mode. (0.5)tPERIOD INPUT PICLKP/N (311 MHz) tSU INPUTS D[15:0]P/N (622 Mbits/s) tHOLD DATA 1 DATA 2 2253(F) Figure 9. Transmit Timing Waveform (Forward Directional 311 Clocking Mode) Agere Systems Inc. 23 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Timing Characteristics (continued) Transmit Timing (continued) Figure 10 shows the timing relationships between the output clock CK622P/N and the input data D[15:0]P/N. This relationship is true for both the contraclocking mode and the clockless transfer mode. tPERIOD OUTPUT CK622 tSU INPUTS tHOLD D[15:0]P/N DATA 1 DATA 2 2254(F) Note: TSU and THOLD only apply in contraclocking mode when CLKMOD[1:0] = 01. Figure 10. Transmit Timing Waveform (Contradirectional Clocking Mode) Figure 11 shows the skew relationship between the D0P/N data remainder of the D[15:1]P/N data bus required to support clockless data transfer. tPERIOD INPUT D0P/N DATA 1 DATA 2 tSKEW INPUTS D[15:1]P/N DATA 1 DATA 2 2255(F) Figure 11. Transmit Timing Waveform (Clockless Transfer Mode) 24 Agere Systems Inc. TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Timing Characteristics (continued) Transmit Timing (continued) The output 622 MHz clock and data signals are specified in Table 19. Table 19. LVDS Input ac Timing Characteristics Applicable Pins Symbol PICLKP/N — PICLKP/N tPERIOD D[15:0]P/N PICLKP/N (622 MHz) tSU Parameter Conditions Min Typ Max Unit All signals differential 40 50 60 % 622 MHz 311 MHz — — 1.6 3.2 — — ns ns Setup from Clock Edge to D[15:0]P/N CLKMOD[1:0] = 00, all signals differential 0.07 — — ns tHOLD Hold from Clock Edge to D[15:0]P/N CLKMOD[1:0] = 00, all signals differential 0.07 — — ns Duty Cycle Clock Period D[15:0]P/N PICLKP/N (311 MHz) tSU Setup from Clock Edge to D[15:0]P/N CLKMOD[1:0] = 10, all signals differential 0.68 — — ns tHOLD Hold from Clock Edge to D[15:0]P/N CLKMOD[1:0] = 10, all signals differential 0.78 — — ns D[15:0]P/N tSKEW* Skew Tolerable at Receiver Input to Meet Setup and Hold Time Requirements Any two package inputs — — 200 ps * Will be maintained for 100 mV < VID < 400 mV throughout the receiver common-mode operating range. Table 20. LVDS Output ac Timing Characteristics Applicable Pins Symbol CK622P/N CK155P/N — CK622P/N tPERIOD Parameter Duty Cycle Clock Period Conditions Min Typ Max Unit All signals differential 40 50 60 % — — 1.6 — ns — 6.4 — ns CK155P/N D[15:0]P/N CK622P/N* CK622P/N CK155P/N tSU Setup from Clock Edge to D[15:0]P/N 9.95328 Gbits/s 10.70920 Gbits/s — — –200 –400 — — ns ns tHOLD Hold from Clock Edge to D[15:0]P/N 9.95328 Gbits/s 10.70920 Gbits/s — — 350 520 — — ns ns tRISE Rise Time, 20% to 80% ZLOAD = 100 Ω ± 1% 100 260 400 ps tFALL Fall Time, 20% to 80% ZLOAD = 100 Ω ± 1% 100 260 400 ps Differential Skew — — — 70 ps Single Ended Output Amplitude — 250 — 500 mV tSKEW1† CK622P/N VAMP CK155P/N * CLKMOD[1:0] = 01, all signals differential. † As defined in the IEEE standard 1596.3—1996. Agere Systems Inc. 25 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Timing Characteristics (continued) Transmit Timing (continued) Figure 12 shows the timing relationships between the output 10 GHz clock CK10GP/N and the output 10 Gbits/s data D10GP/N. tPERIOD OUTPUT CK10GP/N tDD OUTPUT D10GP/N DATA 1 DATA 3 DATA 2 0357(F) Figure 12. Transmit Timing Waveform with 10 GHz Clock The output 10 GHz clock and data signals from Figure 12 are characterized in Table 21. Table 21. CML Output Pin ac Timing Characteristics Applicable Pins Symbol CK10GP/N — tPERIOD tDD D10GP/N, CK10GP/N CK10GP/N D10GP/N, LBDP/N D10GP/N, LBDP/N CK10GP/N 26 tRISE tFALL tSKEW1 RLOSS VAMP VAMP Parameter Duty Cycle CK10GP/N Clock Period Time Delay from Clock Edge to Data Edge Rise Time, 20% to 80% Fall Time, 20% to 80% Differential Skew Output Return Loss: 10 GHz <7 GHz Voltage Amplitude Singleended Voltage Amplitude Singleended Conditions Min Typ Max Unit RREFCML = 3 kΩ, RL = 50 Ω 40 — 30 50 100 50 60 — 70 % ps ps 10 10 — 20 20 — 35 35 3 ps ps ps — — 600 12 15 — — — 800 dB dB mV 450 — 650 mV 350 — 500 mV 800 — 1.0 V mV 600 — 800 mV 500 — 650 mV — — RREFCML = 2.2 kΩ, RL = 50 Ω RREFCML = 3.0 kΩ, RL = 50 Ω RREFCML = 3.5 kΩ, RL = 50 Ω RREFCML = 2.2 kΩ, RL = 50 Ω RREFCML = 3 kΩ, RL = 50 Ω RREFCML = 3.5 kΩ, RL = 50 Ω Agere Systems Inc. TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Packaging Characteristics Package Crush Characteristics Table 22. Crush Specifications Additional test information available upon request. Device Code Package Dimensions Conditions Min Typ Max Unit TTRN0110G 198-ball CBGA 15 mm x 15 mm Without pad With pad (0.040 in.) — — 25 25 — — lbs lbs CBGA Package Information The package used for the TTRN0110G is a ceramic ball grid array (CBGA). The substrate is 99.6% alumina (Al2O3) material. The standoff height is accomplished by using 0.013 in. diameter copper silver (CuAg) balls, which are attached using a eutectic braze to the thin film metal pads on the substrate. After brazing, the balls have a diameter at the braze fillet of 0.016 in. (at the interface of the ball and substrate), but still maintain their height of 0.013 in. for standoff height. PWB Design Information The layout of the bare PWB should use a 0.016 in. diameter pad. The pad should be defined by the copper and not by solder mask. (The only copper leading away from the pad should be the trace connected to it; the pad should not be part of a large ground plane unless only connected to the ground plane by a single trace.) Avoid placement of vias in the pads used for ball attachment on the PWB. Vias should be connected by a trace (or tear dropped) with a sufficient dam of solder mask to prevent solder from wicking into the via and away from the ball/PWB solder joint. The stencil opening should be designed at 0.016 in. as well, to match up with the CBGA pads. Agere Systems Inc. 27 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Packaging Characteristics (continued) Assembly Information Note: Each assembly process will have its own idiosyncrasies, due to product design, material differences, and equipment variations. Assembly information provided here is a beginning point from which the assembly process engineer should apply their knowledge and experience to obtain optimal results. It is recommended that the stencil thickness be set at 0.006 in. for a starting point. After trials with the recommended stencil opening size, stencil thickness, and process specific solder paste, a visual inspection should be done to assure a proper fillet and wetting is obtained for each ball. The reflowed solder fillet should resemble a cylindrical column from the PWB to the center of the ball. The reflow profile should be determined using a known set point for the oven such as the Joint Electron Device Engineering Council (JEDEC) profile. The JEDEC profile is defined as the following parameters: Table 23. JEDEC Profile Belt speed = 28 in./min. Zone 1 2 3 4 5 6 7 Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Temp Unit 140 140 150 150 150 150 180 180 180 180 205 205 245 245 °C °C °C °C °C °C °C °C °C °C °C °C °C °C A representative sample of the product (fitted with multiple thermocouples and a data logger) should be run through the oven to determine the optimum profile. The temperature of the CBGA device should not exceed 225 °C, and only be above the liquidus of the solder alloy (typically 180 °C) for less than 60 s. Reference Materials For further information, the user may wish to consult some of the many references that are available on the technical market today for CBGA assembly. The following are suggested for more detailed information, but there are many others too: ■ Ceramic Ball Grid Array Surface Mount Assembly and Rework, IBM Document #APD-SBSC-101.0, Cindy Milkovich, Lisa Jimarez, IBM Corporation, 1701 North Street, Endicott, NY 13760, (800) 925-3157 ■ Ball Grid Array Technology, John Lau (Editor), ISBN 0-07-036608-X, McGraw-Hill, Inc., 1221 Avenue of the Americas, New York, NY 10020 28 Agere Systems Inc. TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Packaging Characteristics (continued) Package Diagram—198-Ball CBGA (Bottom View) Dimensions are in millimeters. Tolerance is ±0.076 mm unless otherwise noted. 15.00 ± 0.080 SQR A1 BALL IDENTIFIER ZONE 15.00 ± 0.080 SQR 1.143 REF 1.885 SEATING PLANE SOLDER BALL 0.3734 ± 0.0013 0.330 ± 0.051 TYP 14 SPACES @ 1.00 = 14.00 R P N M L 0.330 ± 0.051 TYP DIA. 1.00 TYP. K J 14 SPACES @ 1.00 = 14.00 H G F E D C B A A1 BALL CORNER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0627(F) Agere Systems Inc. 29 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Data Sheet March 29, 2002 Ordering Information Device Code Package Temperature (TC) Comcode (Ordering Number) TTRN0110G 198-ball CBGA 0 °C to 85 °C 108698465 Telcordia Technologies is a trademark of Telcordia Technologies Inc. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: [email protected] N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright © 2002 Agere Systems Inc. All Rights Reserved March 29, 2002 DS02-062HSPL (Replaces DS01-236HSPL)