Revised March 1999 74LVX00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. ■ Input voltage level translation from 5V to 3V ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Order Number Package Number 74LVX00M 74LVX00SJ 74LVX00MTC M14A M14D MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names © 1999 Fairchild Semiconductor Corporation Description An , Bn Inputs On Outputs DS011551.prf www.fairchildsemi.com 74LVX00 Low Voltage Quad 2-Input NAND Gate February 1993 74LVX00 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) Supply Voltage (VCC) VI = −0.5V −20 mA −0.5V to 7V DC Input Voltage (VI) 2.0V to 3.6V Input Voltage (VI) 0V to 5.5V Output Voltage (VO) DC Output Diode Current (IOK) 0V to VCC −40°C to +85°C Operating Temperature (TA) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA Input Rise and Fall Time (∆t/∆V) −0.5V to VCC + 0.5V DC Output Voltage (VO) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operarting Conditions” table will define the conditions for actual device operation. DC Output Source ±25 mA or Sink Current (IO) DC VCC or Ground Current ±50 mA (ICC or IGND) 0 ns/V to 100 ns/V Note 2: Unused inputs must be held HIGH or LOW They may not float. −65°C to +150°C Storage Temperature (TSTG) Power Dissipation 180 mW DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter TA = +25°C VCC Min TA =−40°C to +85°C Typ Max Min HIGH Level Input 2.0 1.5 1.5 Voltage 3.0 2.0 2.0 3.6 2.4 2.4 Max 2.0 0.5 0.5 Voltage 3.0 0.8 0.8 3.6 0.8 0.8 2.0 1.9 2.0 1.9 Voltage 3.0 2.9 3.0 2.9 3.0 2.58 Conditions V LOW Level Input HIGH Level Output Units V VIN = VIL or VIH IOH = −50 µA IOH = −50 µA V IOH = −4 mA 2.48 LOW Level Output 2.0 0.0 Voltage 3.0 0.0 0.1 VIN = VIL or VIH IOL = 50 µA 0.1 0.1 0.1 3.0 0.36 0.44 IOL = 50 µA V IOL = 4 mA IIN Input Leakage Current 3.6 ±0.1 ±1.0 µA VIN = 5.5V or GND ICC Quiescent Supply Current 3.6 2.0 20.0 µA VIN = VCC or GND Noise Characteristics (Note 3) Symbol Parameter VCC (V) TA = 25°C Typ Limit Units CL (pF) VOLP Quiet Output Maximum Dynamic VOL 3.3 0.3 0.5 V 50 VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.3 −0.5 V 50 VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V 50 VILD Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50 Note 3: Input tr = tf = 3ns www.fairchildsemi.com 2 Symbol tPLH VCC (V) Parameter Propagation Delay Time TA = +25°C Min 2.7 tPHL 3.3 ± 0.3 Typ TA = −40°C to +85°C Max Min Max 5.4 10.1 1.0 12.5 7.9 13.6 1.0 16.0 4.1 6.2 1.0 7.5 9.7 1.0 6.6 Units CL (pF) 15 ns 50 15 11.0 50 tOSLH Output to Output Skew 2.7 1.5 1.5 50 tOSHL (Note 4) 3.3 1.5 1.5 ns Note 4: Parameter guaranteed by design tOSLH = |tPLHm–tPLHn|, tOSHL = |tPHLm–tPHLn| Capacitance Symbol TA = +25°C Parameter Min TA = −40°C to +85°C Typ Max 10 CIN Input Capacitance 4 CPD Power Dissipation 19 Min Units Max 10 pF pF Capacitance (Note 5) Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. 3 www.fairchildsemi.com 74LVX00 AC Electrical Characteristics 74LVX00 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 4 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74LVX00 Low Voltage Quad 2-Input NAND Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued)