MPCxxx Instruction Set This chapter lists the MPCxxx instruction set in alphabetical order by mnemonic. Note that each entry includes the instruction formats and a quick reference ‘legend’ that provides such information as the level(s) of the PowerPC architecture in which the instruction may be found—user instruction set architecture (UISA), virtual environment architecture (VEA), and operating environment architecture (OEA); and the privilege level of the instruction—user- or supervisor-level (an instruction is assumed to be user-level unless the legend specifies that it is supervisor-level); and the instruction formats. The format diagrams show, horizontally, all valid combinations of instruction fields. Note that the architecture specification refers to user-level and supervisor-level as problem state and privileged state, respectively. Instruction Formats Instructions are four bytes long and word-aligned, so when instruction addresses are presented to the processor (as in branch instructions) the two low-order bits are ignored. Similarly, whenever the processor develops an instruction address, its two low-order bits are zero. Bits 0–5 always specify the primary opcode. Many instructions also have an extended opcode. The remaining bits of the instruction contain one or more fields for the different instruction formats. Some instruction fields are reserved or must contain a predefined value as shown in the individual instruction layouts. If a reserved field does not have all bits cleared, or if a field that must contain a particular value does not contain that value, the instruction form is invalid. Split-Field Notation Some instruction fields occupy more than one contiguous sequence of bits or occupy a contiguous sequence of bits used in permuted order. Such a field is called a split field. Split fields that represent the concatenation of the sequences from left to right are shown in lowercase letters. These split fields— spr, and tbr—are described in Table 1. Table 1. Split-Field Notation and Conventions Field Description spr (11–20) This field is used to specify a special-purpose register for the mtspr and mfspr instructions. tbr (11–20) This field is used to specify either the time base lower (TBL) or time base upper (TBU). Motorola MPCxxx INSTRUCTION SET 1 Split fields that represent the concatenation of the sequences in some order, which need not be left to right (as described for each affected instruction) are shown in uppercase letters. These split fields—MB, ME, and SH—are described in Table 2. Instruction Fields Table 2 describes the instruction fields used in the various instruction formats. Table 2. Instruction Syntax Conventions Field Description AA (30) Absolute address bit. 0 The immediate field represents an address relative to the current instruction address (CIA). The effective (logical) address of the branch is either the sum of the LI field sign-extended to 32 bits and the address of the branch instruction or the sum of the BD field sign-extended to 32 bits and the address of the branch instruction. 1 The immediate field represents an absolute address. The effective address (EA) of the branch is the LI field sign-extended to 32 bits or the BD field sign-extended to 32 bits. Note: The LI and BD fields are sign-extended to 32. BD (16–29) Immediate field specifying a 14-bit signed two's complement branch displacement that is concatenated on the right with 0b00 and sign-extended to 32 bits. BI (11–15) This field is used to specify a bit in the CR to be used as the condition of a branch conditional instruction. BO (6–10) This field is used to specify options for the branch conditional instructions. crbA (11–15) This field is used to specify a bit in the CR to be used as a source. crbB (16–20) This field is used to specify a bit in the CR to be used as a source. CRM (12–19) This field mask is used to identify the CR fields that are to be updated by the mtcrf instruction. d (16–31) Immediate field specifying a 16-bit signed two's complement integer that is sign-extended to 32 bits. frC (21–25) NOT USED BY MPCxxx. frD (6–10) NOT USED BY MPCxxx. frS (6–10) NOT USED BY MPCxxx. IMM (16–19) NOT USED BY MPCxxx. LI (6–29) Immediate field specifying a 24-bit signed two's complement integer that is concatenated on the right with 0b00 and sign-extended to 32 bits. LK (31) Link bit. 0 Does not update the link register (LR). 1 Updates the LR. If the instruction is a branch instruction, the address of the instruction following the branch instruction is placed into the LR. MB (21–25) and ME (26–30) These fields are used in rotate instructions to specify a 32-bit mask. NB (16–20) This field is used to specify the number of bytes to move in an immediate string load or store. OE (21) This field is used for extended arithmetic to enable setting OV and SO in the XER. OPCD (0–5) Primary opcode field 2 MPCxxx INSTRUCTION SET Motorola Table 2. Instruction Syntax Conventions (Continued) Field Description rA (11–15) This field is used to specify a GPR to be used as a source or destination. rB (16–20) This field is used to specify a GPR to be used as a source. Rc (31) Record bit. 0 Does not update the condition register (CR). 1 Updates the CR to reflect the result of the operation. For integer instructions, CR bits 0–2 are set to reflect the result as a signed quantity and CR bit 3 receives a copy of the summary overflow bit, XER[SO]. The result as an unsigned quantity or a bit string can be deduced from the EQ bit. (Note that exceptions are referred to as interrupts in the architecture specification.) rD (6–10) This field is used to specify a GPR to be used as a destination. rS (6–10) This field is used to specify a GPR to be used as a source. SH (16–20) This field is used to specify a shift amount. SIMM (16–31) This immediate field is used to specify a 16-bit signed integer. TO (6–10) This field is used to specify the conditions on which to trap. UIMM (16–31) This immediate field is used to specify a 16-bit unsigned integer. XO (21–30, 22–30, 26–30) Extended opcode field. Notation and Conventions The operation of some instructions is described by a semiformal language (pseudocode). See Table 3 for a list of pseudocode notation and conventions used throughout this chapter. Table 3. Notation and Conventions Notation/Convention Meaning ← Assignment ←iea Assignment of an instruction effective address. ¬ NOT logical operator ∗ Multiplication ÷ Division (yielding quotient) + Two’s-complement addition – Two’s-complement subtraction, unary minus =, ≠ Equals and Not Equals relations <, ≤, >, ≥ Signed comparison relations . (period) Update. When used as a character of an instruction mnemonic, a period (.) means that the instruction updates the condition register field. Motorola MPCxxx INSTRUCTION SET 3 Table 3. Notation and Conventions (Continued) Notation/Convention Meaning c Carry. When used as a character of an instruction mnemonic, a ‘c’ indicates a carry out in XER[CA]. e Extended Precision. When used as the last character of an instruction mnemonic, an ‘e’ indicates the use of XER[CA] as an operand in the instruction and records a carry out in XER[CA]. o Overflow. When used as a character of an instruction mnemonic, an ‘o’ indicates the record of an overflow in XER[OV] and CR0[SO] for integer instructions. <U, >U Unsigned comparison relations ? Unordered comparison relation &, | AND, OR logical operators || Used to describe the concatenation of two values (that is, 010 || 111 is the same as 010111) ⊕, ≡ Exclusive-OR, Equivalence logical operators (for example, (a ≡ b) = (a ⊕ ¬ b)) 0bnnnn A number expressed in binary format. 0xnnnn A number expressed in hexadecimal format. (n)x The replication of x, n times (that is, x concatenated to itself n – 1 times). (n)0 and (n)1 are special cases. A description of the special cases follows: • (n)0 means a field of n bits with each bit equal to 0. Thus (5)0 is equivalent to 0b00000. • (n)1 means a field of n bits with each bit equal to 1. Thus (5)1 is equivalent to 0b11111. (rA|0) The contents of rA if the rA field has the value 1–31, or the value 0 if the rA field is 0. (rX) The contents of rX x[n] n is a bit or field within x, where x is a register xn x is raised to the nth power ABS(x) Absolute value of x CEIL(x) Least integer ≥ x Characterization Reference to the setting of status bits in a standard way that is explained in the text. CIA Current instruction address. The 32-bit address of the instruction being described by a sequence of pseudocode. Used by relative branches to set the next instruction address (NIA) and by branch instructions with LK = 1 to set the link register. Does not correspond to any architected register. Clear Clear the leftmost or rightmost n bits of a register to 0. This operation is used for rotate and shift instructions. Clear left and shift left Clear the leftmost b bits of a register, then shift the register left by n bits. This operation can be used to scale a known non-negative array index by the width of an element. These operations are used for rotate and shift instructions. Cleared Bits are set to 0. 4 MPCxxx INSTRUCTION SET Motorola Table 3. Notation and Conventions (Continued) Notation/Convention Meaning Do Do loop. • Indenting shows range. • “To” and/or “by” clauses specify incrementing an iteration variable. • “While” clauses give termination conditions. Extract Select a field of n bits starting at bit position b in the source register, right or left justify this field in the target register, and clear all other bits of the target register to zero. This operation is used for rotate and shift instructions. EXTS(x) Result of extending x on the left with sign bits GPR(x) General-purpose register x if...then...else... Conditional execution, indenting shows range, else is optional. Insert Select a field of n bits in the source register, insert this field starting at bit position b of the target register, and leave other bits of the target register unchanged. (No simplified mnemonic is provided for insertion of a field when operating on double words; such an insertion requires more than one instruction.) This operation is used for rotate and shift instructions. (Note that simplified mnemonics are referred to as extended mnemonics in the architecture specification.) Leave Leave innermost do loop, or the do loop described in leave statement. MASK(x, y) Mask having ones in positions x through y (wrapping if x > y) and zeros elsewhere. MEM(x, y) Contents of y bytes of memory starting at address x. NIA Next instruction address, which is the 32-bit address of the next instruction to be executed (the branch destination) after a successful branch. In pseudocode, a successful branch is indicated by assigning a value to NIA. For instructions which do not branch, the next instruction address is CIA + 4. Does not correspond to any architected register. OEA PowerPC operating environment architecture Rotate Rotate the contents of a register right or left n bits without masking. This operation is used for rotate and shift instructions. Set Bits are set to 1. Shift Shift the contents of a register right or left n bits, clearing vacated bits (logical shift). This operation is used for rotate and shift instructions. SPR(x) Special-purpose register x TRAP Invoke the system trap handler. Undefined An undefined value. The value may vary from one implementation to another, and from one execution to another on the same implementation. UISA PowerPC user instruction set architecture VEA PowerPC virtual environment architecture Motorola MPCxxx INSTRUCTION SET 5 Table 4 describes instruction field notation conventions used throughout this document. Table 4. Instruction Field Conventions The Architecture Specification Equivalent to: BA, BB, BT crbA, crbB, crbD (respectively) D d DS ds FXM CRM RA, RB, RT, RS rA, rB, rD, rS (respectively) SI SIMM U IMM UI UIMM /, //, /// 0...0 (shaded) Precedence rules for pseudocode operators are summarized in Table 5. Table 5. Precedence Rules Operators Associativity x[n], function evaluation Left to right (n)x or replication, x(n) or exponentiation Right to left unary –, ¬ Right to left ∗, ÷ Left to right +, – Left to right || Left to right =, ≠, <, ≤, >, ≥, <U, >U, ? Left to right &, ⊕, ≡ Left to right | Left to right – (range) None ←, ←iea None Operators higher in Table 5 are applied before those lower in the table. Operators at the same level in the table associate from left to right, from right to left, or not at all, as shown. For example, “–” (unary minus) associates from left to right, so a – b – c = (a – b) – c. Parentheses are used to override the evaluation order implied by Table 5, or to increase clarity; parenthesized expressions are evaluated before serving as operands. 6 MPCxxx INSTRUCTION SET Motorola MPCxxx Instruction Set The remainder of this chapter lists and describes the instruction set for the MPCxxx. The instructions are listed in alphabetical order by mnemonic. Figure 1 shows the format for each instruction description page. Instruction name addx addx Add Instruction syntax add rD,rA,rB (OE = 0 Rc = 0) add. rD,rA,rB (OE = 0 Rc = 1) addo rD,rA,rB (OE = 1 Rc = 0) addo. ] rD,rA,rB (OE = 1 Rc = 1) Instruction encoding 31 0 Pseudocode description of instruction operation Text description of instruction operation Registers altered by instruction D 5 6 A 10 11 B 15 16 20 OE 21 22 266 Rc 30 31 rD ← (rA) + (rB) The sum (rA) + (rB) is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) • XER: Affected: SO, OV(if OE = 1) Quick reference legend PowerPC Architecture Level SupervisorLevel UISA 64-Bit Optional Form XO Instruction Description Note that the execution unit that executes the instruction may not be the same for all PowerPC processors. Motorola MPCxxx INSTRUCTION SET 7 addx addx Add add add. addo addo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B 15 16 OE 266 20 21 22 Rc 30 31 rD ← (rA) + (rB) The sum (rA) + (rB) is placed into rD. The add instruction is preferred for addition because it sets few status bits. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs (see XER below). • XER: Affected: SO, OV (if OE = 1) PowerPC Architecture Level Supervisor Level UISA 8 Optional Form XO MPCxxx INSTRUCTION SET Motorola addcx addcx Add Carrying addc addc. addco addco. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B 15 16 OE 10 20 21 22 Rc 30 31 rD ¨ (rA) + (rB) The sum (rA) + (rB) is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV (if OE = 1) PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form XO MPCxxx INSTRUCTION SET 9 addex addex Add Extended adde adde. addeo addeo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B 15 16 OE 138 20 21 22 Rc 30 31 rD ¨ (rA) + (rB) + XER[CA] The sum (rA) + (rB) + XER[CA] is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV (if OE = 1) PowerPC Architecture Level Supervisor Level UISA 10 Optional Form XO MPCxxx INSTRUCTION SET Motorola addi addi Add Immediate addi rD,rA,SIMM 14 0 D 5 6 A 10 11 SIMM 15 16 31 if rA = 0 then rD ¨ EXTS(SIMM) else rD ¨ rA + EXTS(SIMM) The sum (rA|0) + SIMM is placed into rD. The addi instruction is preferred for addition because it sets few status bits. Note that addi uses the value 0, not the contents of GPR0, if rA = 0. Other registers altered: • None Simplified mnemonics: li rD,value la rD,disp(rA) subi rD,rA,value equivalent to equivalent to equivalent to PowerPC Architecture Level addi rD,0,value addi rD,rA,disp addi rD,rA,–value Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 11 addic addic Add Immediate Carrying addic rD,rA,SIMM 12 0 D 5 6 A 10 11 SIMM 15 16 31 rD ¨ (rA) + EXTS(SIMM) The sum (rA) + SIMM is placed into rD. Other registers altered: • XER: Affected: CA Simplified mnemonics: subic rD,rA,value equivalent to PowerPC Architecture Level addic rD,rA,–value Supervisor Level UISA 12 Optional Form D MPCxxx INSTRUCTION SET Motorola addic. addic. Add Immediate Carrying and Record addic. rD,rA,SIMM 13 0 D 5 6 A 10 11 SIMM 15 16 31 rD ¨ (rA) + EXTS(SIMM) The sum (rA) + SIMM is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs (see XER below). • XER: Affected: CA Simplified mnemonics: subic. rD,rA,value equivalent to PowerPC Architecture Level addic. rD,rA,–value Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 13 addis addis Add Immediate Shifted addis rD,rA,SIMM 15 0 D 5 6 A 10 11 SIMM 15 16 31 if rA = 0 then rD ¨ EXTS(SIMM || (16)0) else rD ¨ (rA) + EXTS(SIMM || (16)0) The sum (rA|0) + (SIMM || 0x0000) is placed into rD. The addis instruction is preferred for addition because it sets few status bits. Note that addis uses the value 0, not the contents of GPR0, if rA = 0. Other registers altered: • None Simplified mnemonics: lis rD,value subis rD,rA,value equivalent to equivalent to PowerPC Architecture Level addis rD,0,value addis rD,rA,–value Supervisor Level UISA 14 Optional Form D MPCxxx INSTRUCTION SET Motorola addmex addmex Add to Minus One Extended addme addme. addmeo addmeo. rD,rA rD,rA rD,rA rD,rA (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) Reserved 31 0 D 5 6 A 10 11 0000 0 15 16 OE 234 20 21 22 Rc 30 31 rD ¨ (rA) + XER[CA] – 1 The sum (rA) + XER[CA] + 0xFFFF_FFFF_FFFF_FFFF is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV (if OE = 1) PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form XO MPCxxx INSTRUCTION SET 15 addzex addzex Add to Zero Extended addze addze. addzeo addzeo. rD,rA rD,rA rD,rA rD,rA (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) Reserved 31 0 D 5 6 A 10 11 0000 0 15 16 OE 202 20 21 22 Rc 30 31 rD ¨ (rA) + XER[CA] The sum (rA) + XER[CA] is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV (if OE = 1) PowerPC Architecture Level Supervisor Level UISA 16 Optional Form XO MPCxxx INSTRUCTION SET Motorola andx andx AND and and. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 28 20 21 Rc 30 31 rA ← (rS) & (rB) The contents of rS are ANDed with the contents of rB and the result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 17 andcx andcx AND with Complement andc andc. rA,rS,rB rA,rS,rB 31 0 S (Rc = 0) (Rc = 1) A 5 6 10 11 B 15 16 60 20 21 Rc 30 31 rA ← (rS) + ¬ (rB) The contents of rS are ANDed with the one’s complement of the contents of rB and the result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) PowerPC Architecture Level Supervisor Level UISA 18 Optional Form X MPCxxx INSTRUCTION SET Motorola andi. andi. AND Immediate andi. rA,rS,UIMM 28 0 S 5 6 A 10 11 UIMM 15 16 31 rA ← (rS) & ((16)0 || UIMM) The contents of rS are ANDed with 0x0000 || UIMM and the result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 19 andis. andis. AND Immediate Shifted andis. rA,rS,UIMM 29 0 S 5 6 A 10 11 UIMM 15 16 31 rA ← (rS) + (UIMM || (16)0) The contents of rS are ANDed with UIMM || 0x0000 and the result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO PowerPC Architecture Level Supervisor Level UISA 20 Optional Form D MPCxxx INSTRUCTION SET Motorola bx bx Branch b ba bl bla target_addr target_addr target_addr target_addr (AA = 0 LK = 0) (AA = 1 LK = 0) (AA = 0 LK = 1) (AA = 1 LK = 1) 18 0 LI AA LK 5 6 29 30 31 if AA then NIA ←iea EXTS(LI || 0b00) else NIA ←iea CIA + EXTS(LI || 0b00) if LK then LR ←iea CIA + 4 target_addr specifies the branch target address. If AA = 0, then the branch target address is the sum of LI || 0b00 sign-extended and the address of this instruction. If AA = 1, then the branch target address is the value LI || 0b00 sign-extended. If LK = 1, then the effective address of the instruction following the branch instruction is placed into the link register. Other registers altered: Affected: Link Register (LR) PowerPC Architecture Level (if LK = 1) Supervisor Level UISA Motorola Optional Form I MPCxxx INSTRUCTION SET 21 bcx bcx Branch Conditional bc bca bcl bcla BO,BI,target_addr BO,BI,target_addr BO,BI,target_addr BO,BI,target_addr 16 BO 0 5 6 (AA = 0 LK = 0) (AA = 1 LK = 0) (AA = 0 LK = 1) (AA = 1 LK = 1) BI 10 11 BD 15 16 AA LK 29 30 31 m ← 32 if ¬ BO[2] then CTR ← CTR – 1 ctr_ok ← BO[2] | (BO[3]) cond_ok ← BO[0] | (CR[BI] ≡ BO[1]) if ctr_ok & cond_ok then if AA then NIA ←iea EXTS(BD || 0b00) else NIA ←iea CIA + EXTS(BD || 0b00) if LK then LR ←iea CIA + 4 The BI field specifies the bit in the condition register (CR) to be used as the condition of the branch. The BO field is encoded as described in Table 6. Table 6. BO Operand Encodings BO Description 0000y Decrement the count register (CTR), then branch if the condition is FALSE. 0001y Decrement the CTR, then branch if the condition is FALSE. 001zy Branch if the condition is FALSE. 0100y Decrement the CTR, then branch if the condition is TRUE. 0101y Decrement the CTR, then branch if the condition is TRUE. 011zy Branch if the condition is TRUE. 1z00y Decrement the CTR, then branch if the decremented CTR ≠ 0. 1z01y Decrement the CTR, then branch if the decremented CTR = 0. 1z1zz Branch always. In this table, z indicates a bit that is ignored. Note that the z bits should be cleared, as they may be assigned a meaning in some future version of the MPCxxx. The y bit provides a hint about whether a conditional branch is likely to be taken. target_addr specifies the branch target address. 22 MPCxxx INSTRUCTION SET Motorola If AA = 0, the branch target address is the sum of BD || 0b00 sign-extended and the address of this instruction. If AA = 1, the branch target address is the value BD || 0b00 sign-extended. If LK = 1, the effective address of the instruction following the branch instruction is placed into the link register. Other registers altered: Affected: Count Register (CTR) (if BO[2] = 0) Affected: Link Register (LR) (if LK = 1) Simplified mnemonics: blt target bne cr2,target bdnz target equivalent to equivalent to equivalent to PowerPC Architecture Level bc bc bc 12,0,target 4,10,target 16,0,target Supervisor Level UISA Motorola Optional Form B MPCxxx INSTRUCTION SET 23 bcctrx bcctrx Branch Conditional to Count Register bcctr bcctrl BO,BI BO,BI (LK = 0) (LK = 1) Reserved 19 BO 0 5 6 BI 10 11 0000 0 15 16 528 20 21 LK 30 31 cond_ok ← BO[0] | (CR[BI] ≡ BO[1]) if cond_ok then NIA ←iea CTR || 0b00 if LK then LR ←iea CIA + 4 The BI field specifies the bit in the condition register to be used as the condition of the branch. The BO field is encoded as described in Table 7. Table 7. BO Operand Encodings BO Description 0000y Decrement the count register (CTR), then branch if the condition is FALSE. 0001y Decrement the CTR, then branch if the condition is FALSE. 001zy Branch if the condition is FALSE. 0100y Decrement the CTR, then branch if the condition is TRUE. 0101y Decrement the CTR, then branch if the condition is TRUE. 011zy Branch if the condition is TRUE. 1z00y Decrement the CTR, then branch if the decremented CTR ≠ 0. 1z01y Decrement the CTR, then branch if the decremented CTR = 0. 1z1zz Branch always. In this table, z indicates a bit that is ignored. Note that the z bits should be cleared, as they may be assigned a meaning in some future version of the MPCxxx. The y bit provides a hint about whether a conditional branch is likely to be taken. The branch target address is CTR || 0b00. If LK = 1, the effective address of the instruction following the branch instruction is placed into the link register. If the “decrement and test CTR” option is specified (BO[2] = 0), the instruction form is invalid. 24 MPCxxx INSTRUCTION SET Motorola Other registers altered: Affected: Link Register (LR) (if LK = 1) Simplified mnemonics: bltctr bnectr cr2 equivalent to equivalent to PowerPC Architecture Level bcctr bcctr 12,0 4,10 Supervisor Level UISA Motorola Optional Form XL MPCxxx INSTRUCTION SET 25 bclrx bclrx Branch Conditional to Link Register bclr bclrl BO,BI BO,BI (LK = 0) (LK = 1) Reserved 19 0 BO 5 6 BI 10 11 0000 0 15 16 16 20 21 LK 30 31 m ← 32 if ¬ BO[2] then CTR ← CTR – 1 ctr_ok ← BO[2] | ((CTR ≠ 0) ⊕ BO[3]) cond_ok ← BO[0] | (CR[BI] ≡ BO[1]) if ctr_ok & cond_ok then NIA ←iea LR || 0b00 if LK then LR ←iea CIA + 4 The BI field specifies the bit in the condition register to be used as the condition of the branch. The BO field is encoded as described in Table 8. Table 8. BO Operand Encodings BO Description 0000y Decrement the CTR, then branch if the condition is FALSE. 0001y Decrement the CTR, then branch if the condition is FALSE. 001zy Branch if the condition is FALSE. 0100y Decrement the CTR, then branch if the condition is TRUE. 0101y Decrement the CTR, then branch if the condition is TRUE. 011zy Branch if the condition is TRUE. 1z00y Decrement the CTR, then branch if the decremented CTR ≠ 0. 1z01y Decrement the CTR, then branch if the decremented CTR = 0. 1z1zz Branch always. In this table, z indicates a bit that is ignored. Note that the z bits should be cleared, as they may be assigned a meaning in some future version of the MPCxxx. The y bit provides a hint about whether a conditional branch is likely to be taken. The branch target address is LR[0-29] || 0b00. If LK = 1, then the effective address of the instruction following the branch instruction is placed into the link register. 26 MPCxxx INSTRUCTION SET Motorola Other registers altered: Affected: Count Register (CTR) (if BO[2] = 0) Affected: Link Register (LR) (if LK = 1) Simplified mnemonics: bltlr bnelr cr2 bdnzlr equivalent to equivalent to equivalent to PowerPC Architecture Level bclr bclr bclr 12,0 4,10 16,0 Supervisor Level UISA Motorola Optional Form XL MPCxxx INSTRUCTION SET 27 cmp cmp Compare cmp crfD,L,rA,rB Reserved 31 0 crfD 5 6 0 L A 8 9 10 11 B 15 16 0000000000 20 21 0 30 31 a ← EXTS(rA) b ← EXTS(rB) if a < b then c ← 0b100 else if a > b then c ← 0b010 else c ← 0b001 CR[4 ∗ crfD–4 ∗ crfD + 3] ← c || XER[SO] The contents of rA are compared with the contents of rB treating the operands as signed integers. The result of the comparison is placed into CR field crfD. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, SO Simplified mnemonics: cmpd rA,rB cmpw cr3,rA,rB equivalent to equivalent to PowerPC Architecture Level cmp 0,1,rA,rB cmp 3,0,rA,rB Supervisor Level UISA 28 Optional Form X MPCxxx INSTRUCTION SET Motorola cmpi cmpi Compare Immediate cmpi crfD,L,rA,SIMM Reserved 11 0 crfD 5 6 0 L A 8 9 10 11 SIMM 15 16 31 a ← (rA) ifa < EXTS(SIMM) then c ← 0b100 else if a > EXTS(SIMM) then c ← 0b010 else c ← 0b001 CR[4 ∗ crfD–4 ∗ crfD + 3] ← c || XER[SO] The contents of rA are compared with the sign-extended value of the SIMM field, treating the operands as signed integers. The result of the comparison is placed into CR field crfD. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, SO Simplified mnemonics: cmpdirA,value cmpwi cr3,rA,value equivalent to equivalent to PowerPC Architecture Level cmpi 0,1,rA,value cmpi 3,0,rA,value Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 29 cmpl cmpl Compare Logical cmpl crfD,L,rA,rB Reserved 31 0 crfD 5 6 0 L A 8 9 10 11 B 15 16 32 20 21 0 31 a ← rA b ← rB ifa <U b then c ← 0b100 else if a >U b then c ← 0b010 else c ← 0b001 CR[4 ∗ crfD–4 ∗ crfD + 3] ← c || XER[SO] The contents of rA are compared with the contents of rB, treating the operands as unsigned integers. The result of the comparison is placed into CR field crfD. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, SO Simplified mnemonics: cmpldrA,rB cmplw cr3,rA,rB equivalent to equivalent to PowerPC Architecture Level cmpl 0,1,rA,rB cmpl 3,0,rA,rB Supervisor Level UISA 30 Optional Form X MPCxxx INSTRUCTION SET Motorola cmpli cmpli Compare Logical Immediate cmpli crfD,L,rA,UIMM Reserved 10 0 crfD 5 6 0 L A 8 9 10 11 UIMM 15 16 31 a ← (rA) ifa <U ((16)0 || UIMM) then c ← 0b100 else if a >U ((16)0 || UIMM) then c ← 0b010 else c ← 0b001 CR[4 ∗ crfD–4 ∗ crfD + 3] ← c || XER[SO] The contents of rA are compared with 0x0000|| UIMM, treating the operands as unsigned integers. The result of the comparison is placed into CR field crfD. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, SO Simplified mnemonics: cmpldir A,value cmplwi cr3,rA,value equivalent to equivalent to PowerPC Architecture Level cmpli 0,1,rA,value cmpli 3,0,rA,value Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 31 cntlzwx cntlzwx Count Leading Zeros Word cntlzw cntlzw. rA,rS rA,rS (Rc = 0) (Rc = 1) Reserved 31 0 S 5 6 A 10 11 0000 0 15 16 26 20 21 Rc 30 31 n ← 0 do while n < 32 if rS[n] = 1 then leave n ← n + 1 rA ← n A count of the number of consecutive zero bits starting at bit 0 of rS is placed into rA. This number ranges from 0 to 32, inclusive. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) Note: If Rc = 1, then LT is cleared in the CR0 field. PowerPC Architecture Level Supervisor Level UISA 32 Optional Form X MPCxxx INSTRUCTION SET Motorola crand crand Condition Register AND crand crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 257 20 21 0 30 31 CR[crbD] ← CR[crbA] & CR[crbB] The bit in the condition register specified by crbA is ANDed with the bit in the condition register specified by crbB. The result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form XL MPCxxx INSTRUCTION SET 33 crandc crandc Condition Register AND with Complement crandc crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 129 20 21 0 30 31 CR[crbD] ← CR[crbA] & ¬ CR[crbB] The bit in the condition register specified by crbA is ANDed with the complement of the bit in the condition register specified by crbB and the result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD PowerPC Architecture Level Supervisor Level UISA 34 Optional Form XL MPCxxx INSTRUCTION SET Motorola creqv creqv Condition Register Equivalent creqv crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 289 20 21 0 30 31 CR[crbD] ← CR[crbA] ≡ CR[crbB] The bit in the condition register specified by crbA is XORed with the bit in the condition register specified by crbB and the complemented result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD Simplified mnemonics: crset crbD equivalent to PowerPC Architecture Level creqv crbD,crbD,crbD Supervisor Level UISA Motorola Optional Form XL MPCxxx INSTRUCTION SET 35 crnand crnand Condition Register NAND crnand crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 225 20 21 0 30 31 CR[crbD] ← ¬ (CR[crbA] & CR[crbB]) The bit in the condition register specified by crbA is ANDed with the bit in the condition register specified by crbB and the complemented result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD PowerPC Architecture Level Supervisor Level UISA 36 Optional Form XL MPCxxx INSTRUCTION SET Motorola crnor crnor Condition Register NOR crnor crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 33 20 21 0 30 31 CR[crbD] ← ¬ (CR[crbA] | CR[crbB]) The bit in the condition register specified by crbA is ORed with the bit in the condition register specified by crbB and the complemented result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD Simplified mnemonics: crnot crbD,crbA equivalent to PowerPC Architecture Level crnor crbD,crbA,crbA Supervisor Level UISA Motorola Optional Form XL MPCxxx INSTRUCTION SET 37 cror cror Condition Register OR cror crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 449 20 21 0 30 31 CR[crbD] ← CR[crbA] | CR[crbB] The bit in the condition register specified by crbA is ORed with the bit in the condition register specified by crbB. The result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD Simplified mnemonics: crmove crbD,crbA equivalent to PowerPC Architecture Level cror crbD,crbA,crbA Supervisor Level UISA 38 Optional Form XL MPCxxx INSTRUCTION SET Motorola crorc crorc Condition Register OR with Complement crorc crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 417 20 21 0 30 31 CR[crbD] ← CR[crbA] | ¬ CR[crbB] The bit in the condition register specified by crbA is ORed with the complement of the condition register bit specified by crbB and the result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form XL MPCxxx INSTRUCTION SET 39 crxor crxor Condition Register XOR crxor crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 193 20 21 0 30 31 CR[crbD] ← CR[crbA] ⊕ CR[crbB] The bit in the condition register specified by crbA is XORed with the bit in the condition register specified by crbB and the result is placed into the condition register specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by crbD Simplified mnemonics: crclr crbD equivalent to PowerPC Architecture Level crxor crbD,crbD,crbD Supervisor Level UISA 40 Optional Form XL MPCxxx INSTRUCTION SET Motorola dcbf dcbf Data Cache Block Flush dcbf rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 86 20 21 0 30 31 EA is the sum (rA|0) + (rB). The dcbf instruction invalidates the block in the data cache addressed by EA, copying the block to memory first, if there is any dirty data in it. If the processor is a multiprocessor implementation and the block is marked coherency-required, the processor will, if necessary, send an address-only broadcast to other processors. The broadcast of the dcbf instruction causes another processor to copy the block to memory, if it has dirty data, and then invalidate the block from the cache. The action taken depends on the memory mode associated with the block containing the byte addressed by EA and on the state of that block. The list below describes the action taken for the various states of the memory coherency attribute (M bit). • Coherency required • — Unmodified block—Invalidates copies of the block in the data caches of all processors. — Modified block—Copies the block to memory. Invalidates copies of the block in the data caches of all processors. — Absent block—If modified copies of the block are in the data caches of other processors, causes them to be copied to memory and invalidated in those data caches. If unmodified copies are in the data caches of other processors, causes those copies to be invalidated in those data caches. Coherency not required — Unmodified block—Invalidates the block in the processor’s data cache. — Modified block—Copies the block to memory. Invalidates the block in the processor’s data cache. — Absent block (target block not in cache)—No action is taken. The function of this instruction is independent of the write-through, write-back and caching-inhibited/allowed modes of the block containing the byte addressed by EA. Motorola MPCxxx INSTRUCTION SET 41 This instruction may be treated as a load from the addressed byte with respect to address translation and memory protection. It may also be treated as a load for referenced and changed bit recording except that referenced and changed bit recording may not occur. Other registers altered: • None PowerPC Architecture Level Supervisor Level VEA 42 Optional Form X MPCxxx INSTRUCTION SET Motorola dcbi dcbi Data Cache Block Invalidate dcbi rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 470 20 21 0 30 31 EA is the sum (rA|0) + (rB). The action taken is dependent on the memory mode associated with the block containing the byte addressed by EA and on the state of that block. The list below describes the action taken if the block containing the byte addressed by EA is or is not in the cache. • Coherency required • — Unmodified block—Invalidates copies of the block in the data caches of all processors. — Modified block—Invalidates copies of the block in the data caches of all processors. (Discards the modified contents.) — Absent block—If copies of the block are in the data caches of any other processor, causes the copies to be invalidated in those data caches. (Discards any modified contents.) Coherency not required — Unmodified block—Invalidates the block in the processor’s data cache. — Modified block—Invalidates the block in the processor’s data cache. (Discards the modified contents.) — Absent block (target block not in cache)—No action is taken. When data address translation is enabled, MSR[DR] = 1, and the virtual address has no translation, a DSI exception occurs. The function of this instruction is independent of the write-through and caching-inhibited/allowed modes of the block containing the byte addressed by EA. This instruction operates as a store to the addressed byte with respect to address translation and protection. The referenced and changed bits are modified appropriately. This is a supervisor-level instruction. Other registers altered: • None Motorola PowerPC Architecture Level Supervisor Level OEA √ MPCxxx INSTRUCTION SET Optional Form X 43 dcbst dcbst Data Cache Block Store dcbst rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 54 20 21 0 30 31 EA is the sum (rA|0) + (rB). The dcbst instruction executes as follows: • • If the block containing the byte addressed by EA is in coherency-required mode, and a block containing the byte addressed by EA is in the data cache of any processor and has been modified, the writing of it to main memory is initiated. If the block containing the byte addressed by EA is in coherency-not-required mode, and a block containing the byte addressed by EA is in the data cache of this processor and has been modified, the writing of it to main memory is initiated. The function of this instruction is independent of the write-through and cachinginhibited/allowed modes of the block containing the byte addressed by EA. The processor treats this instruction as a load from the addressed byte with respect to address translation and memory protection. It may also be treated as a load for referenced and changed bit recording except that referenced and changed bit recording may not occur. Other registers altered: • None PowerPC Architecture Level Supervisor Level VEA 44 Optional Form X MPCxxx INSTRUCTION SET Motorola dcbt dcbt Data Cache Block Touch dcbt rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 278 20 21 0 30 31 EA is the sum (rA|0) + (rB). This instruction is a hint that performance will probably be improved if the block containing the byte addressed by EA is fetched into the data cache, because the program will probably soon load from the addressed byte. The hint is ignored if the block is cachinginhibited. Executing dcbt does not cause the system alignment error handler to be invoked. This instruction may be treated as a load from the addressed byte with respect to address translation, memory protection, and reference and change recording, except that no exception occurs in the case of a translation fault or protection violation. The program uses the dcbt instruction to request a cache block fetch before it is actually needed by the program. The program can later execute load instructions to put data into registers. However, the processor is not obliged to load the addressed block into the data cache. Other registers altered: • None PowerPC Architecture Level Supervisor Level VEA Motorola Optional Form X MPCxxx INSTRUCTION SET 45 dcbtst dcbtst Data Cache Block Touch for Store dcbtst rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 246 20 21 0 30 31 EA is the sum (rA|0) + (rB). This instruction is a hint that performance will be improved if the block containing the byte addressed by EA is fetched into the data cache, because the program will probably soon store into the addressed byte. The hint is ignored if the block is caching-inhibited. Executing dcbtst does not cause the system alignment error handler to be invoked. This instruction operates as a load from the addressed byte with respect to address translation and protection, except that no exception occurs in the case of a translation fault or protection violation. Also, if the referenced and changed bits are recorded, they are recorded as if the access was a load. The program uses dcbtst to request a cache block fetch to guarantee that a subsequent store will be to a cached location. The program can later execute store instructions to put data into memory. However, the processor is not obliged to load the addressed cache block into the data cache. Other registers altered: • None PowerPC Architecture Level Supervisor Level VEA 46 Optional Form X MPCxxx INSTRUCTION SET Motorola dcbz dcbz Data Cache Block Set to Zero dcbz rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 1014 20 21 0 30 31 EA is the sum (rA|0) + (rB). The dcbz instruction executes as follows: • • If the cache block containing the byte addressed by EA is in the data cache, all bytes are cleared. If the cache block containing the byte addressed by EA is not in the data cache and the corresponding page is caching-allowed, the cache block is allocated in the data cache (without fetching the block from main memory), and all bytes are cleared. • If the page containing the byte addressed by EA is in caching-inhibited or writethrough mode, either all bytes of main memory that correspond to the addressed cache block are cleared or the alignment exception handler is invoked. The exception handler clears all bytes in main memory that corresponds to the addressed cache block. • If the cache block containing the byte addressed by EA is in coherency-required mode, and the cache block exists in the data cache(s) of any other processor(s), it is kept coherent in those caches. This instruction is treated as a store to the addressed byte with respect to address translation, memory protection, referenced and changed recording and the ordering enforced by eieio or by the combination of caching-inhibited and guarded attributes for a page. Other registers altered: • None PowerPC Architecture Level Supervisor Level VEA Motorola Optional Form X MPCxxx INSTRUCTION SET 47 divwx divwx Divide Word divw divw. divwo divwo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B 15 16 OE 20 21 22 491 Rc 30 31 dividend ← (rA) divisor ← (rB) rD ← dividend ÷ divisor The dividend is the contents of rA. The divisor is the contents of rB. The 32-bit quotient is formed and placed in rD. The remainder is not supplied as a result. Both the operands and the quotient are interpreted as signed integers. The quotient is the unique signed integer that satisfies the equation—dividend = (quotient * divisor) + r where 0 ≤ r < |divisor| (if the dividend is non-negative), and –|divisor| < r ≤ 0 (if the dividend is negative). If an attempt is made to perform any of the divisions—0x8000_0000 ÷ –1or <anything> ÷ 0—then the contents of rD are undefined, as are the contents of the LT, GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if OE = 1 then OV is set. The 32-bit signed remainder of dividing the contents of rA by the contents of rB can be computed as follows, except in the case that the contents of rA = –231 and the contents of rB = –1. divw mullw subf 48 rD,rA,rB rD,rD,rB rD,rD,rA # rD = quotient # rD = quotient ∗ divisor # rD = remainder MPCxxx INSTRUCTION SET Motorola Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO • (if Rc = 1) XER: Affected: SO, OV (if OE = 1) Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the 32-bit result. PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form XO MPCxxx INSTRUCTION SET 49 divwux divwux Divide Word Unsigned divwu divwu. divwuo divwuo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B 15 16 OE 20 21 22 459 Rc 30 31 dividend ← (rA) divisor ← (rB) rD ← dividend ÷ divisor The dividend is the contents of rA. The divisor is the contents of rB. A 32-bit quotient is formed. The 32-bit quotient is placed into rD. The remainder is not supplied as a result. Both operands and the quotient are interpreted as unsigned integers, except that if Rc = 1 the first three bits of CR0 field are set by signed comparison of the result to zero. The quotient is the unique unsigned integer that satisfies the equation—dividend = (quotient ∗ divisor) + r (where 0 ≤ r < divisor). If an attempt is made to perform the division—<anything> ÷ 0—then the contents of rD are undefined as are the contents of the LT, GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if OE = 1 then OV is set. The 32-bit unsigned remainder of dividing the contents of rA by the contents of rB can be computed as follows: divwu mullw subf 50 rD,rA,rB rD,rD,rB rD,rD,rA # rD = quotient # rD = quotient * divisor # rD = remainder MPCxxx INSTRUCTION SET Motorola Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO • (if Rc = 1) XER: Affected: SO, OV (if OE = 1) Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the 32-bit result. PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form XO MPCxxx INSTRUCTION SET 51 eciwx eciwx External Control In Word Indexed eciwx rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 310 20 21 0 30 31 The eciwx instruction allows the system designer to map special devices in an alternative way. The MMU translation of the EA is not used to select the special device, as it is used in most instructions such as loads and stores. Rather, it is used as an address operand that is passed to the device over the address bus. Four other pins (the burst and size pins on the 60x bus) are used to select the device; these four pins output the 4-bit resource ID (RID) field that is located in the EAR register. The eciwx instruction also loads a word from the data bus that is output by the special device. The eciwx instruction and the EAR register can be very efficient when mapping special devices such as graphics devices that use addresses as pointers. if rA = 0 then b ← 0 else b← (rA) EA ← b + (rB) paddr ← address translation of EA send load word request for paddr to device identified by EAR[RID] rD ← word from device EA is the sum (rA|0) + (rB). A load word request for the physical address (referred to as real address in the architecture specification) corresponding to EA is sent to the device identified by EAR[RID], bypassing the cache. The word returned by the device is placed in rD. EAR[E] must be 1. If it is not, a DSI exception is generated. EA must be a multiple of four. If it is not, one of the following occurs: • • • A system alignment exception is generated. A DSI exception is generated (possible only if EAR[E] = 0). The results are boundedly undefined. The eciwx instruction is supported for EAs that reference memory segments in which SR[T] = 1 and for EAs mapped by the DBAT registers. If the EA references a direct-store segment (SR[T] = 1), either a DSI exception occurs or the results are boundedly undefined. However, note that the direct-store facility is being phased out of the architecture and will not likely be supported in future devices. Thus, software should not depend on its effects. 52 MPCxxx INSTRUCTION SET Motorola If this instruction is executed when MSR[DR] = 0 (real addressing mode), the results are boundedly undefined. This instruction is treated as a load from the addressed byte with respect to address translation, memory protection, referenced and changed bit recording, and the ordering performed by eieio. This instruction is optional in the PowerPC architecture. Other registers altered: • None PowerPC Architecture Level Supervisor Level VEA Motorola MPCxxx INSTRUCTION SET Optional Form √ X 53 ecowx ecowx External Control Out Word Indexed ecowx rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 438 20 21 0 30 31 The ecowx instruction and the EAR register can be very efficient when mapping special devices such as graphics devices that use addresses as pointers. if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) paddr ← address translation of EA send store word request for paddr to device identified by EAR[RID] send rS to device EA is the sum (rA|0) + (rB). A store word request for the physical address corresponding to EA and the contents of rS are sent to the device identified by EAR[RID], bypassing the cache. EAR[E] must be 1, if it is not, a DSI exception is generated. EA must be a multiple of four. If it is not, one of the following occurs: • • • A system alignment exception is generated. A DSI exception is generated (possible only if EAR[E] = 0). The results are boundedly undefined. The ecowx instruction is supported for effective addresses that reference memory segments in which SR[T] = 0, and for EAs mapped by the DBAT registers. If the EA references a direct-store segment (SR[T] = 1), either a DSI exception occurs or the results are boundedly undefined. However, note that the direct-store facility is being phased out of the architecture and will not likely be supported in future devices. Thus, software should not depend on its effects. If this instruction is executed when MSR[DR] = 0 (real addressing mode), the results are boundedly undefined. This instruction is treated as a store from the addressed byte with respect to address translation, memory protection, nd referenced and changed bit recording, and the ordering performed by eieio. This instruction is optional in the PowerPC architecture. Other registers altered: • None PowerPC Architecture Level Supervisor Level VEA 54 MPCxxx INSTRUCTION SET Optional Form √ X Motorola eieio eieio Enforce In-Order Execution of I/O Reserved 31 0 00 000 5 6 0 0000 10 11 0000 0 15 16 854 20 21 0 30 31 The eieio instruction provides an ordering function for the effects of load and store instructions executed by a processor. These loads and stores are divided into two sets, which are ordered separately. The memory accesses caused by a dcbz instruction are ordered like a store. The two sets follow: 1. Loads and stores to memory that is both caching-inhibited and guarded, and stores to memory that is write-through required. The eieio instruction controls the order in which the accesses are performed in main memory. It ensures that all applicable memory accesses caused by instructions preceding the eieio instruction have completed with respect to main memory before any applicable memory accesses caused by instructions following the eieio instruction access main memory. It acts like a barrier that flows through the memory queues and to main memory, preventing the reordering of memory accesses across the barrier. No ordering is performed for dcbz if the instruction causes the system alignment error handler to be invoked. All accesses in this set are ordered as a single set—that is, there is not one order for loads and stores to caching-inhibited and guarded memory and another order for stores to write-through required memory. 2. Stores to memory that have all of the following attributes—caching-allowed, writethrough not required, and memory-coherency required. The eieio instruction controls the order in which the accesses are performed with respect to coherent memory. It ensures that all applicable stores caused by instructions preceding the eieio instruction have completed with respect to coherent memory before any applicable stores caused by instructions following the eieio instruction complete with respect to coherent memory. With the exception of dcbz, eieio does not affect the order of cache operations (whether caused explicitly by execution of a cache management instruction, or implicitly by the cache coherency mechanism). The eieio instruction does not affect the order of accesses in one set with respect to accesses in the other set. The eieio instruction may complete before memory accesses caused by instructions preceding the eieio instruction have been performed with respect to main memory or coherent memory as appropriate. The eieio instruction is intended for use in managing shared data structures, in accessing memory-mapped I/O, and in preventing load/store combining operations in main memory. For the first use, the shared data structure and the lock that protects it must be altered only by stores that are in the same set (1 or 2; see previous discussion). For the second use, eieio can be thought of as placing a barrier into the stream of memory accesses Motorola MPCxxx INSTRUCTION SET 55 issued by a processor, such that any given memory access appears to be on the same side of the barrier to both the processor and the I/O device. Because the processor performs store operations in order to memory that is designated as both caching-inhibited and guarded, the eieio instruction is needed for such memory only when loads must be ordered with respect to stores or with respect to other loads. Note that the eieio instruction does not connect hardware considerations to it such as multiprocessor implementations that send an eieio address-only broadcast (useful in some designs). For example, if a design has an external buffer that re-orders loads and stores for better bus efficiency, the eieio broadcast signals to that buffer that previous loads/stores (marked caching-inhibited, guarded, or write-through required) must complete before any following loads/stores (marked caching-inhibited, guarded, or writethrough required). Other registers altered: • None PowerPC Architecture Level Supervisor Level VEA 56 Optional Form X MPCxxx INSTRUCTION SET Motorola eqvx eqvx Equivalent eqv eqv. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 284 21 22 Rc 30 31 rA ← (rS) ≡ (rB) The contents of rS are XORed with the contents of rB and the complemented result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 57 extsbx extsbx Extend Sign Byte extsb extsb. rA,rS rA,rS (Rc = 0) (Rc = 1) Reserved 31 0 S 5 6 A 10 11 0000 0 15 16 954 20 21 Rc 30 31 S ← rS[24] rA[24-31] ← rS[24-31] rA[0–23] ← (24)S The contents of rS[24-31] are placed into rA[24-31]. Bit 24 of rS is placed into rA[0-23]. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) PowerPC Architecture Level Supervisor Level UISA 58 Optional Form X MPCxxx INSTRUCTION SET Motorola extshx extshx Extend Sign Half Word extsh extsh. rA,rS rA,rS (Rc = 0) (Rc = 1) Reserved 31 0 S 5 6 A 10 11 0000 0 15 16 922 20 21 Rc 30 31 S ← rS[16] rA[16-31] ← rS[16-31] rA[0-15] ← (16)S The contents of rS[16-31] are placed into rA[16-31]. Bit 16 of rS is placed into rA[0–15]. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 59 icbi icbi Instruction Cache Block Invalidate icbi rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 982 20 21 0 30 31 EA is the sum (rA|0) + (rB). If the block containing the byte addressed by EA is in coherency-required mode, and a block containing the byte addressed by EA is in the instruction cache of any processor, the block is made invalid in all such instruction caches, so that subsequent references cause the block to be refetched. If the block containing the byte addressed by EA is in coherency-not-required mode, and a block containing the byte addressed by EA is in the instruction cache of this processor, the block is made invalid in that instruction cache, so that subsequent references cause the block to be refetched. The function of this instruction is independent of the writethrough, write-back, and caching-inhibited/allowed modes of the block containing the byte addressed by EA. This instruction is treated as a load from the addressed byte with respect to address translation and memory protection. It may also be treated as a load for referenced and changed bit recording except that referenced and changed bit recording may not occur. Implementations with a combined data and instruction cache treat the icbi instruction as a no-op, except that they may invalidate the target block in the instruction caches of other processors if the block is in coherency-required mode. The icbi instruction invalidates the block at EA (rA|0 + rB). If the processor is a multiprocessor implementation and the block is marked coherency-required, the processor will send an address-only broadcast to other processors causing those processors to invalidate the block from their instruction caches. For faster processing, many implementations will not compare the entire EA (rA|0 + rB) with the tag in the instruction cache. Instead, they will use the bits in the EA to locate the set that the block is in, and invalidate all blocks in that set. Other registers altered: • None PowerPC Architecture Level Supervisor Level VEA 60 Optional Form X MPCxxx INSTRUCTION SET Motorola isync isync Instruction Synchronize isync Reserved 19 0 00 000 5 6 0 0000 10 11 0000 0 15 16 150 20 21 0 30 31 The isync instruction provides an ordering function for the effects of all instructions executed by a processor. Executing an isync instruction ensures that all instructions preceding the the isync instruction have completed before the isync instruction completes, except that memory accesses caused by those instructions need not have been performed with respect to other processors and mechanisms. It also ensures that no subsequent instructions are initiated by the processor until after the isync instruction completes. Finally, it causes the processor to discard any prefetched instructions, with the effect that subsequent instructions will be fetched and executed in the context established by the instructions preceding the isync instruction. The isync instruction has no effect on the other processors or on their caches. This instruction is context synchronizing. Context synchronization is necessary after certain code sequences that perform complex operations within the processor. These code sequences are usually operating system tasks that involve memory management. For example, if an instruction “A” changes the memory translation rules in the memory management unit (MMU), the isync instruction should be executed so that the instructions following instruction “A” will be discarded from the pipeline and refetched according to the new translation rules. This instruction is context synchronizing. Other registers altered: • None PowerPC Architecture Level Supervisor Level VEA Motorola Optional Form XL MPCxxx INSTRUCTION SET 61 lbz lbz Load Byte and Zero lbz rD,d(rA) 34 0 D 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) rD ← (24)0 || MEM(EA, 1) EA is the sum (rA|0) + d. The byte in memory addressed by EA is loaded into the low-order eight bits of rD. The remaining bits in rD are cleared. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 62 Optional Form D MPCxxx INSTRUCTION SET Motorola lbzu lbzu Load Byte and Zero with Update lbzu rD,d(rA) 35 0 D 5 6 A 10 11 d 15 16 31 EA ← (rA) + EXTS(d) rD ← (24)0 || MEM(EA, 1) rA ← EA EA is the sum (rA) + d. The byte in memory addressed by EA is loaded into the low-order eight bits of rD. The remaining bits in rD are cleared. EA is placed into rA. If rA = 0, or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 63 lbzux lbzux Load Byte and Zero with Update Indexed lbzux rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 119 20 21 0 30 31 EA ← (rA) + (rB) rD ← (24)0 || MEM(EA, 1) rA ← EA EA is the sum (rA) + (rB). The byte in memory addressed by EA is loaded into the loworder eight bits of rD. The remaining bits in rD are cleared. EA is placed into rA. If rA = 0 or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 64 Optional Form X MPCxxx INSTRUCTION SET Motorola lbzx lbzx Load Byte and Zero Indexed lbzx rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 87 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) rD ← (24)0 || MEM(EA, 1) EA is the sum (rA|0) + (rB). The byte in memory addressed by EA is loaded into the loworder eight bits of rD. The remaining bits in rD are cleared. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 65 lha lha Load Half Word Algebraic lha rD,d(rA) 42 D 0 5 6 if rA else EA ← rD ← A 10 11 d 15 16 31 = 0 then b ← 0 b ← (rA) b + EXTS(d) EXTS(MEM(EA, 2)) EA is the sum (rA|0) + d. The half word in memory addressed by EA is loaded into the loworder 16 bits of rD. The remaining bits in rD are filled with a copy of the most-significant bit of the loaded half word. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 66 Optional Form D MPCxxx INSTRUCTION SET Motorola lhau lhau Load Half Word Algebraic with Update lhau rD,d(rA) 43 0 D 5 6 A 10 11 d 15 16 31 EA ← (rA) + EXTS(d) rD ← EXTS(MEM(EA, 2)) rA ← EA EA is the sum (rA) + d. The half word in memory addressed by EA is loaded into the loworder 16 bits of rD. The remaining bits in rD are filled with a copy of the most-significant bit of the loaded half word. EA is placed into rA. If rA = 0 or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 67 lhaux lhaux Load Half Word Algebraic with Update Indexed lhaux rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 375 20 21 0 30 31 EA ← (rA) + (rB) rD ← EXTS(MEM(EA, 2)) rA ← EA EA is the sum (rA) + (rB). The half word in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are filled with a copy of the mostsignificant bit of the loaded half word. EA is placed into rA. If rA = 0 or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 68 Optional Form X MPCxxx INSTRUCTION SET Motorola lhax lhax Load Half Word Algebraic Indexed lhax rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 343 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) rD ← EXTS(MEM(EA, 2)) EA is the sum (rA|0) + (rB). The half word in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are filled with a copy of the mostsignificant bit of the loaded half word. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 69 lhbrx lhbrx Load Half Word Byte-Reverse Indexed lhbrx rD,rA,rB Reserved 31 D 0 5 6 if rA else EA ← rD ← A 10 11 B 15 16 790 20 21 0 30 31 = 0 then b ← 0 b ← (rA) b + (rB) (16)0 || MEM(EA + 1, 1) || MEM(EA, 1) EA is the sum (rA|0) + (rB). Bits 0–7 of the half word in memory addressed by EA are loaded into the low-order eight bits of rD. Bits 8–15 of the half word in memory addressed by EA are loaded into the subsequent low-order eight bits of rD. The remaining bits in rD are cleared. The PowerPC architecture cautions programmers that some implementations of the architecture may run the lhbrx instructions with greater latency than other types of load instructions. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 70 Optional Form X MPCxxx INSTRUCTION SET Motorola lhz lhz Load Half Word and Zero lhz rD,d(rA) 40 0 D 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) rD ← (16)0 || MEM(EA, 2) EA is the sum (rA|0) + d. The half word in memory addressed by EA is loaded into the loworder 16 bits of rD. The remaining bits in rD are cleared. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 71 lhzu lhzu Load Half Word and Zero with Update lhzu rD,d(rA) 41 0 D 5 6 A 10 11 d 15 16 31 EA ← rA + EXTS(d) rD ← (16)0 || MEM(EA, 2) rA ← EA EA is the sum (rA) + d. The half word in memory addressed by EA is loaded into the loworder 16 bits of rD. The remaining bits in rD are cleared. EA is placed into rA. If rA = 0 or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 72 Optional Form D MPCxxx INSTRUCTION SET Motorola lhzux lhzux Load Half Word and Zero with Update Indexed lhzux rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 311 20 21 0 30 31 EA ← (rA) + (rB) rD ← (16)0 || MEM(EA, 2) rA ← EA EA is the sum (rA) + (rB). The half word in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are cleared. EA is placed into rA. If rA = 0 or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 73 lhzx lhzx Load Half Word and Zero Indexed lhzx rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 279 20 21 0 30 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + (rB) rD ← (16)0 || MEM(EA, 2) EA is the sum (rA|0) + (rB). The half word in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are cleared. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 74 Optional Form X MPCxxx INSTRUCTION SET Motorola lmw lmw Load Multiple Word lmw rD,d(rA) 46 0 D 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + EXTS(d) r ← rD do while r ≤ 31 GPR(r) ← MEM(EA, 4) r←r + 1 EA ← EA + 4 EA is the sum (rA|0) + d. n = (32 – rD). n consecutive words starting at EA are loaded into GPRs rD through r31. EA must be a multiple of four. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. If rA is in the range of registers specified to be loaded, including the case in which rA = 0, the instruction form is invalid. Note that, in some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 75 lswi lswi Load String Word Immediate lswi rD,rA,NB Reserved 31 0 D 5 6 A 10 11 NB 15 16 597 20 21 0 30 31 if rA = 0 then EA ← 0 else EA ← (rA) if NB = 0 then n ← 32 elsen ← NB r ← rD – 1 i ← 32 do while n > 0 if i = 32 then r ← r + 1 (mod 32) GPR(r) ← 0 GPR(r)[i–i + 7] ← MEM(EA, 1) i← i + 8 if i = 32 then i ← 0 EA ← EA + 1 n ← n – 1 EA is (rA|0). Let n = NB if NB ≠ 0, n = 32 if NB = 0; n is the number of bytes to load. Let nr = CEIL(n ÷ 4); nr is the number of registers to be loaded with data. n consecutive bytes starting at EA are loaded into GPRs rD through rD + nr – 1. Bytes are loaded left to right in each register. The sequence of registers wraps around to r0 if required. If the 4 bytes of register rD + nr – 1 are only partially filled, the unfilled low-order byte(s) of that register are cleared. If rA is in the range of registers specified to be loaded, including the case in which rA = 0, the instruction form is invalid. Under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. 76 MPCxxx INSTRUCTION SET Motorola Note that, in some implementations, this instruction is likely to have greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 77 lswx lswx Load String Word Indexed lswx rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 533 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) n ← XER[25–31] r ← rD – 1 i ← 32 rD ← undefined do while n > 0 if i = 32 then r ← r + 1 (mod 32) GPR(r) ← 0 GPR(r)[i–i + 7] ← MEM(EA, 1) i← i + 8 if i = 32 then i ← 0 EA ← EA + 1 n ← n – 1 EA is the sum (rA|0) + (rB). Let n = XER[25–31]; n is the number of bytes to load. Let nr = CEIL(n ÷ 4); nr is the number of registers to receive data. If n > 0, n consecutive bytes starting at EA are loaded into GPRs rD through rD + nr – 1. Bytes are loaded left to right in each register. The sequence of registers wraps around through r0 if required. If the four bytes of rD + nr – 1 are only partially filled, the unfilled low-order byte(s) of that register are cleared. If n = 0, the contents of rD are undefined. If rA or rB is in the range of registers specified to be loaded, including the case in which rA = 0, either the system illegal instruction error handler is invoked or the results are boundedly undefined. If rD = rA or rD = rB, the instruction form is invalid. If rD and rA both specify GPR0, the form is invalid. 78 MPCxxx INSTRUCTION SET Motorola Under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. Note that, in some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 79 lwarx lwarx Load Word and Reserve Indexed lwarx rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 20 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) RESERVE ← 1 RESERVE_ADDR ← physical_addr(EA) rD ← MEM(EA,4) EA is the sum (rA|0) + (rB). The word in memory addressed by EA is loaded into rD. This instruction creates a reservation for use by a store word conditional indexed (stwcx.)instruction. The physical address computed from EA is associated with the reservation, and replaces any address previously associated with the reservation. EA must be a multiple of four. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. When the RESERVE bit is set, the processor enables hardware snooping for the block of memory addressed by the RESERVE address. If the processor detects that another processor writes to the block of memory it has reserved, it clears the RESERVE bit. The stwcx. instruction will only do a store if the RESERVE bit is set. The stwcx. instruction sets the CR0[EQ] bit if the store was successful and clears it if it failed. The lwarx and stwcx. combination can be used for atomic read-modify-write sequences. Note that the atomic sequence is not guaranteed, but its failure can be detected if CR0[EQ] = 0 after the stwcx. instruction. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 80 Optional Form X MPCxxx INSTRUCTION SET Motorola lwbrx lwbrx Load Word Byte-Reverse Indexed lwbrx rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 534 20 21 0 30 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + (rB) rD ← MEM(EA + 3, 1) || MEM(EA + 2, 1) || MEM(EA + 1, 1) || MEM(EA, 1) EA is the sum (rA|0) + rB. Bits 0–7 of the word in memory addressed by EA are loaded into the low-order 8 bits of rD. Bits 8–15 of the word in memory addressed by EA are loaded into the subsequent low-order 8 bits of rD. Bits 16–23 of the word in memory addressed by EA are loaded into the subsequent low-order eight bits of rD. Bits 24–31 of the word in memory addressed by EA are loaded into the subsequent low-order 8 bits of rD. The MPCxxx may run the lwbrx instructions with greater latency than other types of load instructions. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 81 lwz lwz Load Word and Zero lwz rD,d(rA) 32 0 D 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + EXTS(d) rD ← MEM(EA, 4) EA is the sum (rA|0) + d. The word in memory addressed by EA is loaded into rD. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 82 Optional Form D MPCxxx INSTRUCTION SET Motorola lwzu lwzu Load Word and Zero with Update lwzu rD,d(rA) 33 0 D 5 6 A 10 11 d 15 16 31 EA ← rA + EXTS(d) rD ← MEM(EA, 4) rA ← EA EA is the sum (rA) + d. The word in memory addressed by EA is loaded into rD. EA is placed into rA. If rA = 0, or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 83 lwzux lwzux Load Word and Zero with Update Indexed lwzux rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 55 20 21 0 30 31 EA ← (rA) + (rB) rD ← MEM(EA, 4) rA ← EA EA is the sum (rA) + (rB). The word in memory addressed by EA is loaded into rD. EA is placed into rA. If rA = 0, or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 84 Optional Form X MPCxxx INSTRUCTION SET Motorola lwzx lwzx Load Word and Zero Indexed lwzx rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 23 20 21 0 30 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + rB rD ← MEM(EA, 4) EA is the sum (rA|0) + (rB). The word in memory addressed by EA is loaded into rD. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 85 mcrf mcrf Move Condition Register Field mcrf crfD,crfS Reserved 19 0 crfD 5 6 00 crfS 8 9 10 11 00 0000 0 13 14 15 16 0000000000 20 21 0 30 31 CR[4 ∗ crfD–4 ∗ crfD + 3] ← CR[4 ∗ crfS–4 ∗ crfS + 3] The contents of condition register field crfS are copied into condition register field crfD. All other condition register fields remain unchanged. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, SO PowerPC Architecture Level Supervisor Level UISA 86 Optional Form XL MPCxxx INSTRUCTION SET Motorola mcrxr mcrxr Move to Condition Register from XER mcrxr crfD Reserved 31 0 crfD 5 6 00 0 0000 8 9 10 11 0000 0 15 16 512 20 21 0 30 31 CR[4 ∗ crfD–4 ∗ crfD + 3] ← XER[0–3] XER[0–3] ← 0b0000 The contents of XER[0–3] are copied into the condition register field designated by crfD. All other fields of the condition register remain unchanged. XER[0–3] is cleared. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, SO • XER[0–3] PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 87 mfcr mfcr Move from Condition Register mfcr rD Reserved 31 0 D 56 0 0000 10 11 0000 0 15 16 19 20 21 0 30 31 rD ← CR The contents of the condition register (CR) are placed into rD. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 89 mfmsr mfmsr Move from Machine State Register mfmsr rD Reserved 31 0 D 56 0 0000 10 11 0000 0 15 16 83 0 20 21 30 31 rD ← MSR The contents of the MSR are placed into rD. This is a supervisor-level instruction. Other registers altered: • 90 None PowerPC Architecture Level Supervisor Level OEA √ MPCxxx INSTRUCTION SET Optional Form X Motorola mfspr mfspr Move from Special-Purpose Register mfspr rD,SPR Reserved 31 0 D 56 spr* 339 10 11 20 21 0 30 31 *Note: This is a split field. n ← spr[5–9] || spr[0–4] rD ← SPR(n) In the PowerPC UISA, the SPR field denotes a special-purpose register, encoded as shown in Table 9. The contents of the designated special-purpose register are placed into rD. Table 9. PowerPC UISA SPR Encodings for mfspr SPR** Register Name Decimal spr[5–9] spr[0–4] 1 00000 00001 XER 8 00000 01000 LR 9 00000 01001 CTR ** Note that the order of the two 5-bit halves of the SPR number is reversed compared with the actual instruction coding. If the SPR field contains any value other than one of the values shown in Table 9 (and the processor is in user mode), one of the following occurs: • • • The system illegal instruction error handler is invoked. The system supervisor-level instruction error handler is invoked. The results are boundedly undefined. Other registers altered: • None Motorola MPCxxx INSTRUCTION SET 91 Simplified mnemonics: mfxer rD mflr rD mfctr rD equivalent to equivalent to equivalent to mfspr rD,1 mfspr rD,8 mfspr rD,9 In the PowerPC OEA, the SPR field denotes a special-purpose register, encoded as shown in Table 10. The contents of the designated SPR are placed into rD. SPR[0] = 1 if and only if reading the register is supervisor-level. Execution of this instruction specifying a defined and supervisor-level register when MSR[PR] = 1 will result in a priviledged instruction type program exception. If MSR[PR] = 1, the only effect of executing an instruction with an SPR number that is not shown in Table 10 and has SPR[0] = 1 is to cause a supervisor-level instruction type program exception or an illegal instruction type program exception. For all other cases, MSR[PR] = 0 or SPR[0] = 0. If the SPR field contains any value that is not shown in Table 10, either an illegal instruction type program exception occurs or the results are boundedly undefined. Other registers altered: • None Table 10. PowerPC OEA SPR Encodings for mfspr 1 SPR Decimal Access spr[5–9] spr[0–4] 1 00000 00001 XER User 8 00000 01000 LR User 9 00000 01001 CTR User 18 00000 10010 DSISR Supervisor 19 00000 10011 DAR Supervisor 22 00000 10110 DEC Supervisor 26 00000 11010 SRR0 Supervisor 27 00000 11011 SRR1 Supervisor 80 81 144 145 146 147 92 Register Name 00010 00010 00100 00100 00100 00100 10000 10001 10000 10001 10010 10011 2 EIE Supervisor 3 Supervisor EID 4 CMPA 4 CMPB 4 CMPC 4 CMPD 4 148 00100 10100 ICR 149 00100 10101 DER 4 MPCxxx INSTRUCTION SET Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Motorola Table 10. PowerPC OEA SPR Encodings for mfspr (Continued) 1 SPR Decimal 150 151 152 153 spr[0–4] 00100 10110 00100 00100 00100 10111 11000 11001 4 COUNTA 4 COUNTB 4 CMPE CMPF 00100 11010 CMPG 00100 11011 CMPH 157 158 00100 00100 00100 11100 11101 11110 Supervisor Supervisor Supervisor 4 154 Access Supervisor 4 155 156 Motorola spr[5–9] Register Name Supervisor 4 Supervisor 4 LCTRL1 4 LCTRL2 4 ICTRL 4 Supervisor Supervisor Supervisor 159 00100 11111 BAR Supervisor 272 01000 10000 SPRG0 Supervisor 273 01000 10001 SPRG1 Supervisor 274 01000 10010 SPRG2 Supervisor 275 01000 10011 SPRG3 Supervisor 287 01000 11111 PVR Supervisor 560 10001 10000 IC_CST Supervisor 561 10001 10001 IC_ADR Supervisor 562 10001 10010 IC_DAT Supervisor 568 10001 11000 DC_CST Supervisor 569 10001 11001 DC_ADR Supervisor 570 10001 11010 DC_DAT Supervisor 4 630 10011 10110 DPDR Supervisor 638 10011 11110 IMMR Supervisor 784 11000 10000 MI_CTR Supervisor 786 11000 10010 MI_AP Supervisor 787 11000 10011 MI_EPN Supervisor 789 11000 10101 MI_TWC Supervisor 790 11000 10110 MI_RPN Supervisor 792 11000 11000 MD_CTR Supervisor 793 11000 11001 M_CASID Supervisor 794 11000 11010 MD_AP Supervisor MPCxxx INSTRUCTION SET 93 Table 10. PowerPC OEA SPR Encodings for mfspr (Continued) 1 SPR Decimal Register Name Access spr[5–9] spr[0–4] 795 11000 11011 MD_EPN Supervisor 796 11000 11100 M_TWB Supervisor 797 11000 11101 MD_TWC Supervisor 798 11000 11110 MD_RPN Supervisor 799 11000 11111 M_TW Supervisor 816 11001 10000 MI_DBCAM Supervisor 817 11001 10001 MI_DBRAM0 Supervisor 818 11001 10010 MI_DBRAM1 Supervisor 824 11001 11000 MD_DBCAM Supervisor 825 11001 11001 MI_DBRAM0 Supervisor 826 11001 11010 MI_DBRAM1 Supervisor 1Note that the order of the two 5-bit halves of the SPR number is reversed compared with actual instruction coding. 2 Sets EE Bit (Bit 16) in MSR. 3Clears EE Bit (Bit 16) in MSR. 4Development Support (Debug) Register. For mtspr and mfspr instructions, the SPR number coded in assembly language does not appear directly as a 10-bit binary number in the instruction. The number coded is split into two 5-bit halves that are reversed in the instruction, with the high-order five bits appearing in bits 16–20 of the instruction and the low-order five bits in bits 11–15. PowerPC Architecture Level Supervisor Level UISA/OEA √* Optional Form XFX * Note that mfspr is supervisor-level only if SPR[0] = 1. 94 MPCxxx INSTRUCTION SET Motorola mftb mftb Move from Time Base mftb rD,TBR Reserved 31 0 D 5 6 tbr* 10 11 371 20 21 0 30 31 *Note: This is a split field. n ← tbr[5–9] || tbr[0–4] if n = 268 then rD ← TBL else if n = 269 then rD ← TBU Table 11. TBR Encodings for mftb TBR* Decimal Register Name Access tbr[5–9] tbr[0–4] 268 01000 01100 TB Read User 269 01000 01101 TBU Read User *Note that the order of the two 5-bit halves of the TBR number is reversed. If the TBR field contains any value other than one of the values shown in Table 11, then one of the following occurs: • • • The system illegal instruction error handler is invoked. The system supervisor-level instruction error handler is invoked. The results are boundedly undefined. It is important to note that some implementations may implement mftb and mfspr identically, therefore, a TBR number must not match an SPR number. Other registers altered: • None Motorola MPCxxx INSTRUCTION SET 95 Simplified mnemonics: mftb rD mftbu rD equivalent to equivalent to PowerPC Architecture Level mftb rD,268 mftb rD,269 Supervisor Level VEA 96 Optional Form XFX MPCxxx INSTRUCTION SET Motorola mtcrf mtcrf Move to Condition Register Fields mtcrf CRM,rS Reserved 31 0 S 5 6 0 CRM 10 11 12 0 144 19 20 21 0 30 31 mask ← (4)(CRM[0]) || (4)(CRM[1]) ||... (4)(CRM[7]) CR ← (rS & mask) | (CR & ¬ mask) The contents of rS are placed into the condition register under control of the field mask specified by CRM. The field mask identifies the 4-bit fields affected. Let i be an integer in the range 0–7. If CRM(i) = 1, CR field i (CR bits 4 ∗ i through 4 ∗ i + 3) is set to the contents of the corresponding field of rS. Note that updating a subset of the eight fields of the condition register may have substantially poorer performance on some implementations than updating all of the fields. Other registers altered: • CR fields selected by mask Simplified mnemonics: mtcr rS equivalent to PowerPC Architecture Level mtcrf 0xFF,rS Supervisor Level UISA Motorola Optional Form XFX MPCxxx INSTRUCTION SET 97 mtmsr mtmsr Move to Machine State Register mtmsr rS Reserved 31 0 S 5 6 0 0000 10 11 0000 0 15 16 146 20 21 0 30 31 MSR ← (rS) The contents of rS are placed into the MSR. This is a supervisor-level instruction. It is also an execution synchronizing instruction except with respect to alterations to the POW and LE bits. In addition, alterations to the MSR[EE] and MSR[RI] bits are effective as soon as the instruction completes. Thus if MSR[EE] = 0 and an external or decrementer exception is pending, executing an mtmsr instruction that sets MSR[EE] = 1 will cause the external or decrementer exception to be taken before the next instruction is executed, if no higher priority exception exists. Other registers altered: • 98 MSR PowerPC Architecture Level Supervisor Level OEA √ MPCxxx INSTRUCTION SET Optional Form X Motorola mtspr mtspr Move to Special-Purpose Register mtspr SPR,rS Reserved 31 0 S 56 spr* 10 11 467 20 21 0 30 31 *Note: This is a split field. n ← spr[5–9] || spr[0–4] SPR(n) ← rS In the PowerPC UISA, the SPR field denotes a special-purpose register, encoded as shown in Table 12. The contents of rS are placed into the designated special-purpose register. Table 12. PowerPC UISA SPR Encodings for mtspr SPR** Register Name Decimal spr[5–9] spr[0–4] 1 00000 00001 XER 8 00000 01000 LR 9 00000 01001 CTR ** Note that the order of the two 5-bit halves of the SPR number is reversed compared with actual instruction coding. If the SPR field contains any value other than one of the values shown in Table 12, and the processor is operating in user mode, one of the following occurs: • • • The system illegal instruction error handler is invoked. The system supervisor instruction error handler is invoked. The results are boundedly undefined. Other registers altered: • See Table 12. Motorola MPCxxx INSTRUCTION SET 99 Simplified mnemonics: mtxer rD mtlr rD mtctr rD equivalent to equivalent to equivalent to mtspr 1,rD mtspr 8,rD mtspr 9,rD In the PowerPC OEA, the SPR field denotes a special-purpose register, encoded as shown in Table 13. The contents of rS are placed into the designated special-purpose register. For this instruction, SPRs TBL and TBU are treated as separate 32-bit registers; setting one leaves the other unaltered. The value of SPR[0] = 1 if and only if writing the register is a supervisor-level operation. Execution of this instruction specifying a defined and supervisor-level register when MSR[PR] = 1 results in a priviledged instruction type program exception. If MSR[PR] = 1 then the only effect of executing an instruction with an SPR number that is not shown in Table 13 and has SPR[0] = 1 is to cause a priviledged instruction type program exception or an illegal instruction type program exception. For all other cases, MSR[PR] = 0 or SPR[0] = 0, if the SPR field contains any value that is not shown in Table 13, either an illegal instruction type program exception occurs or the results are boundedly undefined. Other registers altered: • See Table 13. Table 13. PowerPC OEA SPR Encodings for mtspr 1 SPR Decimal Access spr[0–4] 1 00000 00001 XER User 8 00000 01000 LR User 9 00000 01001 CTR User 18 00000 10010 DSISR Supervisor 19 00000 10011 DAR Supervisor 22 00000 10110 DEC Supervisor 26 00000 11010 SRR0 Supervisor 27 00000 11011 SRR1 Supervisor 80 81 00010 00010 10000 10001 EIE 2 Supervisor 3 EID Supervisor 4 144 00100 10000 CMPA 145 00100 10001 CMPB 146 147 100 Register Name spr[5–9] 00100 00100 10010 10011 4 4 CMPC 4 CMPD MPCxxx INSTRUCTION SET Supervisor Supervisor Supervisor Supervisor Motorola Table 13. PowerPC OEA SPR Encodings for mtspr (Continued) 1 SPR Decimal 148 149 150 151 spr[0–4] 00100 10100 00100 00100 00100 10101 10110 10111 4 ICR DER Supervisor 4 COUNTA 4 COUNTB 4 00100 11000 CMPE 153 00100 11001 CMPF 154 00100 11010 CMPG 156 157 158 00100 00100 00100 00100 11011 11100 11101 11110 Access Supervisor 4 152 155 Motorola spr[5–9] Register Name Supervisor Supervisor Supervisor 4 Supervisor 4 Supervisor 4 CMPH Supervisor 4 LCTRL1 4 LCTRL2 4 ICTRL 4 Supervisor Supervisor Supervisor 159 00100 11111 BAR Supervisor 272 01000 10000 SPRG0 Supervisor 273 01000 10001 SPRG1 Supervisor 274 01000 10010 SPRG2 Supervisor 275 01000 10011 SPRG3 Supervisor 284 01000 11100 TB Write Supervisor 285 01000 11101 TBU Write Supervisor 560 10001 10000 IC_CST Supervisor 561 10001 10001 IC_ADR Supervisor 562 10001 10010 IC_DAT Supervisor 568 10001 11000 DC_CST Supervisor 569 10001 11001 DC_ADR Supervisor 570 10001 11010 DC_DAT 630 10011 10110 DPDR Supervisor 638 10011 11110 IMMR Supervisor 784 11000 10000 MI_CTR Supervisor 786 11000 10010 MI_AP Supervisor 787 11000 10011 MI_EPN Supervisor 789 11000 10101 MI_TWC Supervisor 790 11000 10110 MI_RPN Supervisor 4 MPCxxx INSTRUCTION SET Supervisor 101 Table 13. PowerPC OEA SPR Encodings for mtspr (Continued) 1 SPR Decimal Register Name Access spr[5–9] spr[0–4] 792 11000 11000 MD_CTR Supervisor 793 11000 11001 M_CASID Supervisor 794 11000 11010 MD_AP Supervisor 795 11000 11011 MD_EPN Supervisor 796 11000 11100 M_TWB Supervisor 797 11000 11101 MD_TWC Supervisor 798 11000 11110 MD_RPN Supervisor 799 11000 11111 M_TW Supervisor 816 11001 10000 MI_DBCAM Supervisor 817 11001 10001 MI_DBRAM0 Supervisor 818 11001 10010 MI_DBRAM1 Supervisor 824 11001 11000 MD_DBCAM Supervisor 825 11001 11001 MI_DBRAM0 Supervisor 826 11001 11010 MI_DBRAM1 Supervisor 1Note that the order of the two 5-bit halves of the SPR number is reversed. For mtspr and mfspr instructions, the SPR number coded in assembly language does not appear directly as a 10-bit binary number in the instruction. The number coded is split into two 5-bit halves that are reversed in the instruction, with the high-order five bits appearing in bits 16–20 of the instruction and the low-order five bits in bits 11–15. . 2Sets EE Bit (Bit 16) in MSR. 3Clears EE Bit (Bit 16) in MSR. 4Development Support (Debug) Register. PowerPC Architecture Level Supervisor Level UISA/OEA √* Optional Form XFX * Note that mtspr is supervisor-level only if SPR[0] = 1. 102 MPCxxx INSTRUCTION SET Motorola mulhwx mulhwx Multiply High Word mulhw mulhw. rD,rA,rB rD,rA,rB (Rc = 0) (Rc = 1) Reserved 31 0 D 5 6 A 10 11 B 15 16 0 75 20 21 22 Rc 30 31 prod[0–63] ← rA ∗ rB rD ← prod[0–31] The 64 -bit product is formed from the contents of rA and rB. The high-order 32 bits of the 64-bit product of the operands are placed into rD. Both the operands and the product are interpreted as signed integers. This instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form XO MPCxxx INSTRUCTION SET 103 mulhwux mulhwux Multiply High Word Unsigned mulhwu mulhwu. rD,rA,rB rD,rA,rB (Rc = 0) (Rc = 1) Reserved 31 0 D 5 6 A 10 11 B 15 16 0 11 20 21 22 Rc 30 31 prod[0–63] ← rA ∗ rB rD ← prod[0–31] The 32-bit operands are the contents of rA and rB. The high-order 32 bits of the 64-bit product of the operands are placed into rD. Both the operands and the product are interpreted as unsigned integers, except that if Rc = 1 the first three bits of CR0 field are set by signed comparison of the result to zero. This instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level Supervisor Level UISA 104 Optional Form XO MPCxxx INSTRUCTION SET Motorola mulli mulli Multiply Low Immediate mulli rD,rA,SIMM 07 0 D 5 6 A 10 11 SIMM 15 16 31 prod[0–48] ← (rA) ∗ SIMM rD ← prod[16-48] The first operand is (rA). The 16-bit second operand is the value of the SIMM field. The low-order 32-bits of the 48-bit product of the operands are placed into rD. Both the operands and the product are interpreted as signed integers. The low-order 32 bits of the product are calculated independently of whether the operands are treated as signed or unsigned 32-bit integers. This instruction can be used with mulhdx or mulhwx to calculate a full 64-bit product. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 105 mullwx mullwx Multiply Low Word mullw mullw. mullwo mullwo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 rD ← rA (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B 15 16 OE 235 20 21 22 Rc 30 31 ∗ rB The 32-bit operands are the contents of rA and rB. The low-order 32 bits of the 64-bit product (rA) * (rB) are placed into rD. The low-order 32 bits of the product are the correct 32-bit product for 32-bit implementations. The low-order 32-bits of the product are independent of whether the operands are regarded as signed or unsigned 32-bit integers. If OE = 1, then OV is set if the product cannot be represented in 32 bits. Both the operands and the product are interpreted as signed integers. Note that this instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs (see XER below). • XER: Affected: SO, OV(if OE = 1) Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the 32-bit result. PowerPC Architecture Level Supervisor Level UISA 106 Optional Form XO MPCxxx INSTRUCTION SET Motorola nandx nandx NAND nand nand. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 476 20 21 Rc 30 31 rA ← ¬ ((rS) & (rB)) The contents of rS are ANDed with the contents of rB and the complemented result is placed into rA. nand with rS = rB can be used to obtain the one's complement. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 107 negx negx Negate neg neg. nego nego. rD,rA rD,rA rD,rA rD,rA (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) Reserved 31 0 D 5 6 A 10 11 0000 0 15 16 OE 104 20 21 22 Rc 30 31 rD ← ¬ (rA) + 1 The value 1 is added to the complement of the value in rA, and the resulting two’s complement is placed into rD. If rA contains the most negative 32-bit number (0x8000_0000), the result is the most negative number and, if OE = 1, OV is set. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) • XER: Affected: SO OV(if OE = 1) PowerPC Architecture Level Supervisor Level UISA 108 Optional Form XO MPCxxx INSTRUCTION SET Motorola norx norx NOR nor nor. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 124 20 21 Rc 30 31 rA ← ¬ ((rS) | (rB)) The contents of rS are ORed with the contents of rB and the complemented result is placed into rA. nor with rS = rB can be used to obtain the one’s complement. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: not rD,rS equivalent to PowerPC Architecture Level nor rA,rS,rS Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 109 orx orx OR or or. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 444 20 21 Rc 30 31 rA ← (rS) | (rB) The contents of rS are ORed with the contents of rB and the result is placed into rA. The simplified mnemonic mr (shown below) demonstrates the use of the or instruction to move register contents. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: mr rA,rS equivalent to PowerPC Architecture Level or rA,rS,rS Supervisor Level UISA 110 Optional Form X MPCxxx INSTRUCTION SET Motorola orcx orcx OR with Complement orc orc. rA,rS,rB rA,rS,rB 31 0 S (Rc = 0) (Rc = 1) A 5 6 10 11 B 15 16 412 20 21 Rc 30 31 rA ← (rS) | ¬ (rB) The contents of rS are ORed with the complement of the contents of rB and the result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 111 ori ori OR Immediate ori rA,rS,UIMM 24 0 S 5 6 A 10 11 UIMM 15 16 31 rA ← (rS) | ((16)0 || UIMM) The contents of rS are ORed with 0x0000|| UIMM and the result is placed into rA. The preferred no-op (an instruction that does nothing) is ori 0,0,0. Other registers altered: • None Simplified mnemonics: nop equivalent to PowerPC Architecture Level ori 0,0,0 Supervisor Level UISA 112 Optional Form D MPCxxx INSTRUCTION SET Motorola oris oris OR Immediate Shifted oris rA,rS,UIMM 25 0 S 5 6 A 10 11 UIMM 15 16 31 rA ← (rS) | (UIMM || (16)0) The contents of rS are ORed with UIMM || 0x0000 and the result is placed into rA. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 113 rfi rfi Return from Interrupt Reserved 19 0 00 000 5 6 0 0000 10 11 0000 0 15 16 50 20 21 0 30 31 MSR[16–23, 25–27, 30–31] ← SRR1[16–23, 25–27, 30–31] NIA ←iea SRR0[0–29] || 0b00 Bits SRR1[0,5-9,16-31] are placed into the corresponding bits of the MSR. If the new MSR value does not enable any pending exceptions, then the next instruction is fetched, under control of the new MSR value, from the address SRR0[0–29] || 0b00. If the new MSR value enables one or more pending exceptions, the exception associated with the highest priority pending exception is generated; in this case the value placed into SRR0 by the exception processing mechanism is the address of the instruction that would have been executed next had the exception not occurred. Note that an implementation may define addtional MSR bits, and in this case, may also cause them to be saved to SRR1 from MSR on an exception and restored to MSR from SRR1 on an rfi. This is a supervisor-level, context synchronizing instruction. Other registers altered: • 114 MSR PowerPC Architecture Level Supervisor Level OEA √ MPCxxx INSTRUCTION SET Optional Form XL Motorola rlwimix rlwimix Rotate Left Word Immediate then Mask Insert rlwimi rlwimi. rA,rS,SH,MB,ME rA,rS,SH,MB,ME 20 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 SH 15 16 MB 20 21 ME 25 26 Rc 30 31 n ← SH r ← ROTL(rS, n) m ← MASK(MB, ME) rA ← (r & m) | (rA & ¬ m) The contents of rS are rotated left the number of bits specified by operand SH. A mask is generated having 1 bits from bit MB through bit ME and 0 bits elsewhere. The rotated data is inserted into rA under control of the generated mask. Note that rlwimi can be used to insert a bit field into the contents of rA using the methods shown below: • • To insert an n-bit field, that is left-justified rS, into rA starting at bit position b, set SH = 32 – b, MB = b, and ME = (b + n) – 1. To insert an n-bit field, that is right-justified in rS, into rA starting at bit position b, set SH = 32 – (b + n), MB = b, and ME = (b + n) – 1. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: inslwi rA,rS,n,b insrwi rA,rS,n,b (n > 0) equivalent to rlwimi equivalent to rlwimi PowerPC Architecture Level rA,rS,32 – b,b,b + n – 1 rA,rS,32 – (b + n),b,(b + n) – 1 Supervisor Level UISA Motorola Optional Form M MPCxxx INSTRUCTION SET 115 rlwinmx rlwinmx Rotate Left Word Immediate then AND with Mask rlwinm rlwinm. rA,rS,SH,MB,ME rA,rS,SH,MB,ME 21 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 SH 15 16 MB 20 21 ME 25 26 Rc 30 31 n ← SH r ← ROTL(rS, n) m ← MASK(MB, ME) rA ← r & m The contents of rS are rotated left the number of bits specified by operand SH. A mask is generated having 1 bits from bit MB through bit ME and 0 bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA. Note that rlwinm can be used to extract, rotate, shift, and clear bit fields using the methods shown below: • To extract an n-bit field, that starts at bit position b in rS, right-justified into rA (clearing the remaining 32 – n bits of rA), set SH = b + n, MB = 32 – n, and ME = 31. • To extract an n-bit field, that starts at bit position b in rS, left-justified into rA (clearing the remaining 32 – n bits of rA), set SH = b, MB = 0, and ME = n – 1. • To rotate the contents of a register left (or right) by n bits, set SH = n (32 – n), MB = 0, and ME = 31. To shift the contents of a register right by n bits, by setting SH = 32 – n, MB = n, and ME = 31. It can be used to clear the high-order b bits of a register and then shift the result left by n bits by setting SH = n, MB = b – n and ME = 31 – n. To clear the low-order n bits of a register, by setting SH = 0, MB = 0, and ME = 31 – n. • • Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) 116 MPCxxx INSTRUCTION SET Motorola Simplified mnemonics: extlwi rA,rS,n,b (n > 0) extrwi rA,rS,n,b (n > 0) rotlwi rA,rS,n rotrwi rA,rS,n slwi rA,rS,n (n < 32) srwi rA,rS,n (n < 32) clrlwi rA,rS,n (n < 32) clrrwi rA,rS,n (n < 32) clrlslwi rA,rS,b,n (n ≤ b < 32) equivalent to equivalent to equivalent to equivalent to equivalent to equivalent to equivalent to equivalent to equivalent to PowerPC Architecture Level rlwinm rA,rS,b,0,n – 1 rlwinm rA,rS,b + n,32 – n,31 rlwinm rA,rS,n,0,31 rlwinm rA,rS,32 – n,0,31 rlwinm rA,rS,n,0,31–n rlwinm rA,rS,32 – n,n,31 rlwinm rA,rS,0,n,31 rlwinm rA,rS,0,0,31 – n rlwinm rA,rS,n,b – n,31 – n Supervisor Level UISA Motorola Optional Form M MPCxxx INSTRUCTION SET 117 rlwnmx rlwnmx Rotate Left Word then AND with Mask rlwnm rlwnm. rA,rS,rB,MB,ME rA,rS,rB,MB,ME 23 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 MB 20 21 ME 25 26 Rc 30 31 n ← rB[27-31] r ← ROTL(rS, n) m ← MASK(MB, ME) rA ← r & m The contents of rS are rotated left the number of bits specified by the low-order five bits of rB. A mask is generated having 1 bits from bit MB through bit ME and 0 bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA. Note that rlwnm can be used to extract and rotate bit fields using the methods shown as follows: • To extract an n-bit field, that starts at variable bit position b in rS, right-justified into rA (clearing the remaining 32 – n bits of rA), by setting the low-order five bits of rB to b + n, MB = 32 – n, and ME = 31. • To extract an n-bit field, that starts at variable bit position b in rS, left-justified into rA (clearing the remaining 32 – n bits of rA), by setting the low-order five bits of rB to b, MB = 0, and ME = n – 1. • To rotate the contents of a register left (or right) by n bits, by setting the low-order five bits of rB to n (32 – n), MB = 0, and ME = 31. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: rotlw rA,rS,rB equivalent to PowerPC Architecture Level rlwnmrA,rS,rB,0,31 Supervisor Level UISA 118 Optional Form M MPCxxx INSTRUCTION SET Motorola sc sc System Call Reserved 17 0 00 000 5 6 0 0000 10 11 0000 0000 0000 00 15 16 1 0 29 30 31 The sc instruction calls the operating system to perform a service. When control is returned to the program that executed the system call, the content of the registers depends on the register conventions used by the program providing the system service. The effective address of the instruction following the sc instruction is placed into SRR0. Bits 0, 5-9, and 16-31 of the MSR are placed into the corresponding bits of SRR1, and bits 1-4 and 10-15 of SRR1 are set to undefined values. An sc exception is generated. The exception alters the MSR. The exception causes the next instruction to be fetched from offset 0xC00 from the base real address indicated by the new setting of MSR[IP]. Other registers altered: • • • • Dependent on the system service SRR0 SRR1 MSR PowerPC Architecture Level Supervisor Level UISA/OEA Motorola Optional Form SC MPCxxx INSTRUCTION SET 119 slwx slwx Shift Left Word slw slw. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 24 20 21 Rc 30 31 n ← rB[27-31] rA ← ROTL(rS, n) If bit 26 of rB = 0, the contents of rS are shifted left the number of bits specified by rB[27–31]. Bits shifted out of position 0 are lost. Zeros are supplied to the vacated positions on the right. The 32-bit result is placed into rA. If bit 26 of rB = 1, 32 zeros are placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level Supervisor Level UISA 120 Optional Form X MPCxxx INSTRUCTION SET Motorola srawx srawx Shift Right Algebraic Word sraw sraw. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 792 20 21 Rc 30 31 n ← rB[27-31] rA ← ROTL(rS, n) If rB[26] = 0,then the contents of rS are shifted right the number of bits specified by rB[27–31]. Bits shifted out of position 31 are lost. The result is padded on the left with sign bits before being placed into rA. If rB[26] = 1, then rA is filled with 32 sign bits (bit 0) from rS. CR0 is set based on the value written into rA. XER[CA] is set if rS contains a negative number and any 1 bits are shifted out of position 31; otherwise XER[CA] is cleared. A shift amount of zero causes XER[CA] to be cleared. Note that the sraw instruction, followed by addze, can by used to divide quickly by 2n. The setting of the XER[CA] bit, by sraw, is independent of mode. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) • XER: Affected: CA Motorola MPCxxx INSTRUCTION SET 121 srawix srawix Shift Right Algebraic Word Immediate srawi srawi. rA,rS,SH rA,rS,SH 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 SH 15 16 824 20 21 Rc 30 31 n ← SH r ← ROTL(rS, 32 – n) The contents of rS are shifted right the number of bits specified by operand SH. Bits shifted out of position 31 are lost. The shifted value is sign-extended before being placed in rA. The 32-bit result is placed into rA. XER[CA] is set if rS contains a negative number and any 1 bits are shifted out of position 31; otherwise XER[CA] is cleared. A shift amount of zero causes XER[CA] to be cleared. Note that the srawi instruction, followed by addze, can be used to divide quickly by 2n. The setting of the CA bit, by srawi, is independent of mode. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) • XER: Affected: CA PowerPC Architecture Level Supervisor Level UISA 122 Optional Form X MPCxxx INSTRUCTION SET Motorola srwx srwx Shift Right Word srw srw. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 536 20 21 Rc 30 31 n ← rB[27-31] r ← ROTL(rS, 32 – n) The contents of rS are shifted right the number of bits specified by the low-order six bits of rB. Bits shifted out of position 31 are lost. Zeros are supplied to the vacated positions on the left. The result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 123 stb stb Store Byte stb rS,d(rA) 38 0 S 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + EXTS(d) MEM(EA, 1) ← rS[24-31] EA is the sum (rA|0) + d. The contents of the low-order eight bits of rS are stored into the byte in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 124 Optional Form D MPCxxx INSTRUCTION SET Motorola stbu stbu Store Byte with Update stbu rS,d(rA) 39 0 S 5 6 A 10 11 d 15 16 31 EA ← (rA) + EXTS(d) MEM(EA, 1) ← rS[24-31] rA ← EA EA is the sum (rA) + d. The contents of the low-order eight bits of rS are stored into the byte in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 125 stbux stbux Store Byte with Update Indexed stbux rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 247 21 22 0 30 31 EA ← (rA) + (rB) MEM(EA, 1) ← rS[24-31] rA ← EA EA is the sum (rA) + (rB). The contents of the low-order eight bits of rS are stored into the byte in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 126 Optional Form X MPCxxx INSTRUCTION SET Motorola stbx stbx Store Byte Indexed stbx rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 215 21 22 0 30 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + (rB) MEM(EA, 1) ← rS[24-31] EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into the byte in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 127 sth sth Store Half Word sth rS,d(rA) 44 0 S 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + EXTS(d) MEM(EA, 2) ← rS[16-31] EA is the sum (rA|0) + d. The contents of the low-order 16 bits of rS are stored into the half word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 128 Optional Form D MPCxxx INSTRUCTION SET Motorola sthbrx sthbrx Store Half Word Byte-Reverse Indexed sthbrx rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 918 20 21 0 30 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + (rB) MEM(EA, 2) ← rS[24-31] || rS[16-23] EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into bits 0–7 of the half word in memory addressed by EA. The contents of the subsequent low-order eight bits of rS are stored into bits 8–15 of the half word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 129 sthu sthu Store Half Word with Update sthu rS,d(rA) 45 0 S 5 6 A 10 11 d 15 16 31 EA ← (rA) + EXTS(d) MEM(EA, 2) ← rS[16-31] rA ← EA EA is the sum (rA) + d. The contents of the low-order 16 bits of rS are stored into the half word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 130 Optional Form D MPCxxx INSTRUCTION SET Motorola sthux sthux Store Half Word with Update Indexed sthux rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 439 20 21 0 30 31 EA ← (rA) + (rB) MEM(EA, 2) ← rS[16-31] rA ← EA EA is the sum (rA) + (rB). The contents of the low-order 16 bits of rS are stored into the half word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 131 sthx sthx Store Half Word Indexed sthx rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 407 20 21 0 30 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + (rB) MEM(EA, 2) ← rS[16-31] EA is the sum (rA|0) + (rB). The contents of the low-order 16 bits of rS are stored into the half word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 132 Optional Form X MPCxxx INSTRUCTION SET Motorola stmw stmw Store Multiple Word stmw rS,d(rA) 47 0 S 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + EXTS(d) r ← rS do while r ≤ 31 MEM(EA, 4) ← GPR(r) r← r + 1 EA ← EA + 4 EA is the sum (rA|0) + d. n = (32 – rS). n consecutive words starting at EA are stored from the GPRs rS through r31. For example, if rS = 30, 2 words are stored. EA must be a multiple of four. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. Note that this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 133 stswi stswi Store String Word Immediate stswi rS,rA,NB Reserved 31 0 S 5 6 A 10 11 NB 15 16 725 20 21 0 30 31 if rA = 0 then EA ← 0 elseEA ← (rA) if NB = 0 then n ← 32 elsen ← NB r ← rS – 1 i ← 32 do while n > 0 if i = 32 then r ← r + 1 (mod 32) MEM(EA, 1) ← GPR(r)[i–i + 7] i← i + 8 if i = 64 then i ← 32 EA ← EA + 1 n ← n– 1 EA is (rA|0). Let n = NB if NB ≠ 0, n = 32 if NB = 0; n is the number of bytes to store. Let nr = CEIL(n ÷ 4); nr is the number of registers to supply data. n consecutive bytes starting at EA are stored from GPRs rS through rS + nr – 1. Bytes are stored left to right from each register. The sequence of registers wraps around through r0 if required. Under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. Note that, in some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 134 Optional Form X MPCxxx INSTRUCTION SET Motorola stswx stswx Store String Word Indexed stswx rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 661 20 21 0 30 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + (rB) n ← XER[25–31] r ← rS – 1 i ← 32 do while n > 0 if i = 32 then r ← r + 1 (mod 32) MEM(EA, 1) ← GPR(r)[i–i + 7] i← i + 8 if i = 64 then i ← 32 EA ← EA + 1 n ←n– 1 EA is the sum (rA|0) + (rB). Let n = XER[25–31]; n is the number of bytes to store. Let nr = CEIL(n ÷ 4); nr is the number of registers to supply data. n consecutive bytes starting at EA are stored from GPRs rS through rS + nr – 1. Bytes are stored left to right from each register. The sequence of registers wraps around through r0 if required. If n = 0, no bytes are stored. Under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. Note that, in some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 135 stw stw Store Word stw rS,d(rA) 36 0 S 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + EXTS(d) MEM(EA, 4) ← rS EA is the sum (rA|0) + d. The contents of rS are stored into the word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 136 Optional Form D MPCxxx INSTRUCTION SET Motorola stwbrx stwbrx Store Word Byte-Reverse Indexed stwbrx rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 662 20 21 0 30 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + (rB) MEM(EA, 4) ← rS[24-31] || rS[16-23] || rS[8-15] || rS[0-7] EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into bits 0–7 of the word in memory addressed by EA. The contents of the subsequent eight low-order bits of rS are stored into bits 8–15 of the word in memory addressed by EA. The contents of the subsequent eight low-order bits of rS are stored into bits 16–23 of the word in memory addressed by EA. The contents of the subsequent eight low-order bits of rS are stored into bits 24–31 of the word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 137 stwcx. stwcx. Store Word Conditional Indexed stwcx. rS,rA,rB 31 0 S 5 6 A 10 11 B 15 16 150 20 21 1 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) if RESERVE then if RESERVE_ADDR = physical_addr(EA) MEM(EA, 4) ← rS CR0 ← 0b00 || 0b1 || XER[SO] else u ← undefined 1-bit value if u then MEM(EA, 4) ← rS CR0 ← 0b00 || u || XER[SO] RESERVE ← 0 else CR0 ← 0b00 || 0b0 || XER[SO] EA is the sum (rA|0) + (rB). If the reserved bit is set, the stwcx. instruction stores rS to effective address (rA + rB), clears the reserved bit, and sets CR0[EQ]. If the reserved bit is not set, the stwcx. instruction does not do a store; it leaves the reserved bit cleared and clears CR0[EQ]. Software must look at CR0[EQ] to see if the stwcx. was successful. The reserved bit is set by the lwarx instruction. The reserved bit is cleared by any stwcx. instruction to any address, and also by snooping logic if it detects that another processor does any kind of store to the block indicated in the reservation buffer when reserved is set. If a reservation exists, and the memory address specified by the stwcx. instruction is the same as that specified by the load and reserve instruction that established the reservation, the contents of rS are stored into the word in memory addressed by EA and the reservation is cleared. If a reservation exists, but the memory address specified by the stwcx. instruction is not the same as that specified by the load and reserve instruction that established the reservation, the reservation is cleared, and it is undefined whether the contents of rS are stored into the word in memory addressed by EA. If no reservation exists, the instruction completes without altering memory. CR0 field is set to reflect whether the store operation was performed as follows. CR0[LT GT EQ S0] = 0b00 || store_performed || XER[SO] 138 MPCxxx INSTRUCTION SET Motorola EA must be a multiple of four. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. The granularity with which reservations are managed is implementation-dependent. Therefore, the memory to be accessed by the load and reserve and store conditional instructions should be allocated by a system library program. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 139 stwu stwu Store Word with Update stwu rS,d(rA) 37 0 S 5 6 A 10 11 d 15 16 31 EA ← (rA) + EXTS(d) MEM(EA, 4) ← rS rA ← EA EA is the sum (rA) + d. The contents of rS are stored into the word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 140 Optional Form D MPCxxx INSTRUCTION SET Motorola stwux stwux Store Word with Update Indexed stwux rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 183 20 21 0 30 31 EA ← (rA) + (rB) MEM(EA, 4) ← rS rA ← EA EA is the sum (rA) + (rB). The contents of rS are stored into the word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 141 stwx stwx Store Word Indexed stwx rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 151 20 21 0 30 31 if rA = 0 then b ← 0 elseb ← (rA) EA ← b + (rB) MEM(EA, 4) ← rS EA is the sum (rA|0) + (rB). The contents of rS are is stored into the word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 142 Optional Form X MPCxxx INSTRUCTION SET Motorola subfx subfx Subtract From subf subf. subfo subfo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B 15 16 OE 40 20 21 22 Rc 30 31 rD ← ¬ (rA) + (rB) + 1 The sum ¬ (rA) + (rB) + 1 is placed into rD. The subf instruction is preferred for subtraction because it sets few status bits. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) • XER: Affected: SO, OV(if OE = 1) Simplified mnemonics: sub rD,rA,rB equivalent to PowerPC Architecture Level subf rD,rB,rA Supervisor Level UISA Motorola Optional Form XO MPCxxx INSTRUCTION SET 143 subfcx subfcx Subtract from Carrying subfc subfc. subfco subfco. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B 15 16 OE 8 20 21 22 Rc 30 31 rD ← ¬ (rA) + (rB) + 1 The sum ¬ (rA) + (rB) + 1 is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV (if OE = 1) Simplified mnemonics: subc rD,rA,rB equivalent to PowerPC Architecture Level subfc rD,rB,rA Supervisor Level UISA 144 Optional Form XO MPCxxx INSTRUCTION SET Motorola subfex subfex Subtract from Extended subfe subfe. subfeo subfeo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B 15 16 OE 136 20 21 22 Rc 30 31 rD ← ¬ (rA) + (rB) + XER[CA] The sum ¬ (rA) + (rB) + XER[CA] is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV(if OE = 1) PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form XO MPCxxx INSTRUCTION SET 145 subfic subfic Subtract from Immediate Carrying subfic rD,rA,SIMM 08 0 D 5 6 A 10 11 SIMM 15 16 31 rD ← ¬ (rA) + EXTS(SIMM) + 1 The sum ¬ (rA) + EXTS(SIMM) + 1 is placed into rD. Other registers altered: • XER: Affected: CA PowerPC Architecture Level Supervisor Level UISA 146 Optional Form D MPCxxx INSTRUCTION SET Motorola subfmex subfmex Subtract from Minus One Extended subfme subfme. subfmeo subfmeo. rD,rA rD,rA rD,rA rD,rA (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) Reserved 31 0 D 5 6 A 10 11 0000 0 15 16 OE 232 20 21 22 Rc 30 31 rD ← ¬ (rA) + XER[CA] – 1 The sum ¬ (rA) + XER[CA] + (32)1 is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV(if OE = 1) PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form XO MPCxxx INSTRUCTION SET 147 subfzex subfzex Subtract from Zero Extended subfze subfze. subfzeo subfzeo. rD,rA rD,rA rD,rA rD,rA (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) Reserved 31 0 D 5 6 A 10 11 0000 0 15 16 OE 200 20 21 22 Rc 30 31 rD ← ¬ (rA) + XER[CA] The sum ¬ (rA) + XER[CA] is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV(if OE = 1) PowerPC Architecture Level Supervisor Level UISA 148 Optional Form XO MPCxxx INSTRUCTION SET Motorola sync sync Synchronize Reserved 31 0 00 000 5 6 0 0000 10 11 0000 0 15 16 598 20 21 0 30 31 The sync instruction provides an ordering function for the effects of all instructions executed by a given processor. Executing a sync instruction ensures that all instructions preceding the sync instruction appear to have completed before the sync instruction completes, and that no subsequent instructions are initiated by the processor until after the sync instruction completes. When the sync instruction completes, all external accesses caused by instructions preceding the sync instruction will have been performed with respect to all other mechanisms that access memory. Multiprocessor implementations also send a sync address-only broadcast that is useful in some designs. For example, if a design has an external buffer that re-orders loads and stores for better bus efficiency, the sync broadcast signals to that buffer that previous loads/stores must be completed before any following loads/stores. The sync instruction can be used to ensure that the results of all stores into a data structure, caused by store instructions executed in a “critical section” of a program, are seen by other processors before the data structure is seen as unlocked. The functions performed by the sync instruction will normally take a significant amount of time to complete, so indiscriminate use of this instruction may adversely affect performance. In addition, the time required to execute sync may vary from one execution to another. The eieio instruction may be more appropriate than sync for many cases. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 149 tlbia tlbia Translation Lookaside Buffer Invalidate All Reserved 31 0 00 000 5 6 0 0000 10 11 0000 0 15 16 370 20 21 0 30 31 All TLB entries ← invalid The entire translation lookaside buffer (TLB) is invalidated (that is, all entries are removed). The TLB is invalidated regardless of the settings of MSR[IR] and MSR[DR]. The invalidation is done without reference to the SLB or segment table. This instruction does not cause the entries to be invalidated in other processors. This is a supervisor-level instructon. Other registers altered: • 150 None PowerPC Architecture Level Supervisor Level Optional Form OEA √ √ X MPCxxx INSTRUCTION SET Motorola tlbie tlbie Translation Lookaside Buffer Invalidate Entry tlbie rB Reserved 31 0 00 000 5 6 0 0000 10 11 B 15 16 30k6 20 21 0 30 31 VPS ← rB[4-19] Identify TLB entries corresponding to VPS Each such TLB entry ← invalid EA is the contents of rB. If the translation lookaside buffer (TLB) contains an entry corresponding to EA, that entry is made invalid (that is, removed from the TLB). Multiprocessing implementations (for example, the 601, and 604) send a tlbie addressonly broadcast over the address bus to tell other processors to invalidate the same TLB entry in their TLBs. The TLB search is done regardless of the settings of MSR[IR] and MSR[DR]. The search is done based on a portion of the logical page number within a segment. All entries matching the search criteria are invalidated. Block address translation for EA, if any, is ignored. This is a supervisor-level instruction. Other registers altered: • None Motorola PowerPC Architecture Level Supervisor Level Optional Form OEA √ √ X MPCxxx INSTRUCTION SET 151 tlbsync tlbsync TLB Synchronize Reserved 31 0 00 000 5 6 0 0000 10 11 0000 0 15 16 566 20 21 0 30 31 If an implementation sends a broadcast for tlbie then it will also send a broadcast for tlbsync. Executing a tlbsync instruction ensures that all tlbie instructions previously executed by the processor executing the tlbsync instruction have completed on all other processors. The operation performed by this instruction is treated as a caching-inhibited and guarded data access with respect to the ordering done by eieio. This instruction is supervisor-level. Other registers altered: • 152 None PowerPC Architecture Level Supervisor Level Optional Form OEA √ √ X MPCxxx INSTRUCTION SET Motorola tw tw Trap Word tw TO,rA,rB Reserved 31 0 TO 5 6 A 10 11 B 15 16 4 20 21 0 30 31 a ← EXTS(rA) b ← EXTS(rB) if (a < b) & TO[0] then TRAP if (a > b) & TO[1] then TRAP if (a = b) & TO[2] then TRAP if (a <U b) & TO[3] then TRAP if (a >U b) & TO[4] then TRAP The contents of rA are compared with the contents of rB. If any bit in the TO field is set and its corresponding condition is met by the result of the comparison, then the system trap handler is invoked. Other registers altered: • None Simplified mnemonics: tweq rA,rB twlge rA,rB trap equivalent to equivalent to equivalent to PowerPC Architecture Level tw tw tw 4,rA,rB 5,rA,rB 31,0,0 Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 153 twi twi Trap Word Immediate twi TO,rA,SIMM 03 0 TO 5 6 A 10 11 SIMM 15 16 31 a ← EXTS(rA) if (a < EXTS(SIMM)) & TO[0] then TRAP if (a > EXTS(SIMM)) & TO[1] then TRAP if (a = EXTS(SIMM)) & TO[2] then TRAP if (a <U EXTS(SIMM)) & TO[3] then TRAP if (a >U EXTS(SIMM)) & TO[4] then TRAP The contents of rA are compared with the sign-extended value of the SIMM field. If any bit in the TO field is set and its corresponding condition is met by the result of the comparison, then the system trap handler is invoked. Other registers altered: • None Simplified mnemonics: twgti rA,value twllei rA,value equivalent to equivalent to PowerPC Architecture Level twi twi 8,rA,value 6,rA,value Supervisor Level UISA 154 Optional Form D MPCxxx INSTRUCTION SET Motorola xorx xorx XOR xor xor. rA,rS,rB rA,rS,rB 31 0 S 5 6 rA ← (rS) (Rc = 0) (Rc = 1) A 10 11 B 15 16 316 20 21 Rc 30 31 ⊕ (rB) The contents of rS is XORed with the contents of rB and the result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form X MPCxxx INSTRUCTION SET 155 xori xori XOR Immediate xori rA,rS,UIMM 26 0 S 5 6 rA ← (rS) A 10 11 UIMM 15 16 31 ⊕ ((16)0 || UIMM) The contents of rS are XORed with 0x0000 || UIMM and the result is placed into rA. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA 156 Optional Form D MPCxxx INSTRUCTION SET Motorola xoris xoris XOR Immediate Shifted xoris rA,rS,UIMM 27 0 S 5 6 rA ← (rS) A 10 11 UIMM 15 16 31 ⊕ (UIMM || (16)0) The contents of rS are XORed with UIMM || 0x0000 and the result is placed into rA. Other registers altered: • None PowerPC Architecture Level Supervisor Level UISA Motorola Optional Form D MPCxxx INSTRUCTION SET 157 Appendix MPCxxx Instruction Set Listings This appendix lists the MPCxxx’s instruction set. Instructions are sorted by mnemonic, opcode, function, and form. Also included in this appendix is a quick reference table that contains general information, such as the architecture level, privilege level, and form. Note that split fields, which represent the concatenation of sequences from left to right, are shown in lowercase. Instructions Sorted by Mnemonic Table 1 lists the instructions implemented in the MPCxxx in alphabetical order by mnemonic. Key: Reserved bits Table 1. Complete Instruction List Sorted by Mnemonic Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addx 31 D A B OE 266 Rc addcx 31 D A B OE 10 Rc addex 31 D A B OE 138 Rc addi 14 D A SIMM addic 12 D A SIMM addic. 13 D A SIMM addis 15 D A SIMM addmex 31 D A 00000 OE 234 Rc addzex 31 D A 00000 OE 202 Rc andx 31 S A B 28 Rc andcx 31 S A B 60 Rc andi. 28 S A UIMM andis. 29 S A UIMM Motorola MPCxxx INSTRUCTION SET 1 Name 0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bx 18 bcx 16 BO BI bcctrx 19 BO BI 00000 528 LK bclrx 19 BO BI 00000 16 LK cmp 31 crfD 0 L A B 0 0 cmpi 11 crfD 0 L A cmpl 31 crfD 0 L A 32 0 cmpli 10 crfD 0 L A cntlzwx 31 S A 00000 26 Rc crand 19 crbD crbA crbB 257 0 crandc 19 crbD crbA crbB 129 0 creqv 19 crbD crbA crbB 289 0 crnand 19 crbD crbA crbB 225 0 crnor 19 crbD crbA crbB 33 0 cror 19 crbD crbA crbB 449 0 crorc 19 crbD crbA crbB 417 0 crxor 19 crbD crbA crbB 193 0 dcbf 31 00000 A B 86 0 1 31 00000 A B 470 0 dcbst 31 00000 A B 54 0 dcbt 31 00000 A B 278 0 dcbtst 31 00000 A B 246 0 dcbz 31 00000 A B 1014 0 divwx 31 D A B OE 491 Rc divwux 31 D A B OE 459 Rc eciwx 31 D A B 310 0 ecowx 31 S A B 438 0 eieio 31 00000 00000 00000 854 0 eqvx 31 S A B 284 Rc extsbx 31 S A 00000 954 Rc extshx 31 S A 00000 922 Rc icbi 31 00000 A B 982 0 isync 19 00000 00000 00000 150 0 dcbi 2 6 LI AA LK BD AA LK SIMM B UIMM MPCxxx INSTRUCTION SET Motorola Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lbz 34 D A d lbzu 35 D A d lbzux 31 D A B 119 0 lbzx 31 D A B 87 0 lha 42 D A d lhau 43 D A d lhaux 31 D A B 375 0 lhax 31 D A B 343 0 lhbrx 31 D A B 790 0 lhz 40 D A d lhzu 41 D A d lhzux 31 D A B 311 0 lhzx 31 D A B 279 0 lmw 3 46 D A 3 31 D A NB 597 0 lswx 3 31 D A B 533 0 lwarx 31 D A B 20 0 lwbrx 31 D A B 534 0 lwz 32 D A d lwzu 33 D A d lwzux 31 D A B 55 0 lwzx 31 D A B 23 0 mcrf 19 crfD 00 00000 0 0 mcrxr 31 crfD 00 00000 00000 512 0 mfcr 31 D 00000 00000 19 0 mfmsr 1 31 D 00000 00000 83 0 2 31 D 339 0 mfsr 1 31 D 00000 595 0 mfsrin 1 31 D B 659 0 mftb 31 D 371 0 mtcrf 31 S 144 0 mtmsr 1 31 S 146 0 mtspr 2 31 S 467 0 lswi mfspr Motorola crfS d 00 spr 0 SR 00000 tbr 0 0 CRM 00000 00000 spr MPCxxx INSTRUCTION SET 3 Name 0 6 7 8 mtsr 1 31 S mtsrin 1 31 S mulhwx 31 mulhwux 4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 00000 210 0 00000 B 242 0 D A B 0 75 Rc 31 D A B 0 11 Rc mulli 7 D A mullwx 31 D A B 235 Rc nandx 31 S A B negx 31 D A 00000 norx 31 S A B 124 Rc orx 31 S A B 444 Rc orcx 31 S A B 412 Rc ori 24 S A UIMM oris 25 S A UIMM rfi 1 19 00000 00000 00000 50 0 rlwimix 20 S A SH MB ME Rc rlwinmx 21 S A SH MB ME Rc rlwnmx 23 S A B MB ME Rc sc 17 00000 00000 slwx 31 S A B 24 Rc srawx 31 S A B 792 Rc srawix 31 S A SH 824 Rc srwx 31 S A B 536 Rc stb 38 S A d stbu 39 S A d stbux 31 S A B 247 0 stbx 31 S A B 215 0 sth 44 S A sthbrx 31 S A 918 0 sthu 45 S A sthux 31 S A B 439 0 sthx 31 S A B 407 0 stmw 3 47 S A stswi 3 31 S A 725 0 SR SIMM OE 476 OE Rc 104 00000000000000 Rc 1 0 d B d d NB MPCxxx INSTRUCTION SET Motorola Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 stswx 3 31 S A stw 36 S A stwbrx 31 S A stwcx. 31 S A stwu 37 S A stwux 31 S A stwx 31 S subfx 31 subfcx 661 0 B 662 0 B 150 1 B 183 0 A B 151 0 D A B OE 40 Rc 31 D A B OE 8 Rc subfex 31 D A B OE 136 Rc subfic 08 D A subfmex 31 D A 00000 OE 232 Rc subfzex 31 D A 00000 OE 200 Rc sync 31 00000 00000 00000 598 0 1,4 31 00000 00000 00000 370 0 tlbie 1,4 31 00000 00000 B 306 0 tlbsync1,4 31 00000 00000 00000 566 0 tw 31 TO A B 4 0 twi 03 TO A xorx 31 S A 316 Rc xori 26 S A UIMM xoris 27 S A UIMM tlbia B d d SIMM SIMM B 1 Supervisor-level instruction Supervisor- and user-level instruction 3 Load and store string or multiple instruction 4 PowerPC Optional instruction 2 Motorola MPCxxx INSTRUCTION SET 5 Instructions Sorted by Opcode Table 2 lists the instructions defined for the MPCxxx in numeric order by opcode. Key: Reserved bits Table 2. Complete Instruction List Sorted by Opcode Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 twi 000011 TO A SIMM mulli 000111 D A SIMM subfic 001000 D A SIMM cmpli 001010 crfD 0 L A UIMM cmpi 001011 crfD 0 L A SIMM addic 001100 D A SIMM addic. 001101 D A SIMM addi 001110 D A SIMM addis 001111 D A bcx 010000 BO BI BD SIMM AA LK sc 010001 00000 00000 000000000000000 1 0 bx 010010 mcrf 010011 LI 00 crfD crfS 00 AA LK 00000 0000000000 0 bclrx 010011 BO BI 00000 0000010000 LK crnor 010011 crbD crbA crbB 0000100001 0 1 010011 00000 00000 00000 0000110010 0 crandc 010011 crbD crbA crbB 0010000001 0 isync 010011 00000 00000 00000 0010010110 0 rfi crxor 010011 crbD crbA crbB 0011000001 0 crnand 010011 crbD crbA crbB 0011100001 0 crand 010011 crbD crbA crbB 0100000001 0 creqv 010011 crbD crbA crbB 0100100001 0 crorc 010011 crbD crbA crbB 0110100001 0 cror 010011 crbD crbA crbB 0111000001 0 bcctrx 010011 BO BI 00000 1000010000 LK rlwimix 010100 S A SH MB ME Rc rlwinmx 010101 S A SH MB ME Rc Motorola MPCxxx INSTRUCTION SET 6 Name 7 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rlwnmx 010111 S A ori 011000 S A UIMM oris 011001 S A UIMM B MB xori 011010 S A UIMM xoris 011011 S A UIMM andi. 011100 S A UIMM andis. 011101 S A UIMM cmp 011111 crfD 0 L A B ME 0000000000 0000000100 Rc 0 tw 011111 TO A B subfcx 011111 D A B OE 0000001000 Rc addcx 011111 D A B OE 0000001010 Rc mulhwux 011111 D A B 0 0000001011 Rc mfcr 011111 D 00000 00000 0 0000010011 0 lwarx 011111 D A B 0000010100 0 lwzx 011111 D A B 0000010111 0 slwx 011111 S A B 0000011000 Rc cntlzwx 011111 S A 00000 0000011010 Rc andx 011111 S A B 0000011100 Rc cmpl 011111 A B subfx 011111 crfD D A B dcbst 011111 00000 A B 0000110110 0 lwzux 011111 D A B 0000110111 0 andcx 011111 S A B 0000111100 Rc 0 L 0000100000 OE 0000101000 0 Rc mulhwx 011111 D A B mfmsr 1 011111 D 00000 00000 0001010011 0 dcbf 011111 00000 A B 0001010110 0 lbzx 011111 D A B 0001010111 0 negx 011111 D A 00000 lbzux 011111 D A B 0001110111 0 norx 011111 S A B 0001111100 Rc subfex 011111 D A B OE 0010001000 Rc addex 011111 D A B OE 0010001010 Rc mtcrf 011111 S 0 CRM MPCxxx INSTRUCTION SET 0 OE 0 0001001011 0001101000 0010010000 Rc Rc 0 Motorola Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 011111 S 00000 00000 0010010010 0 stwcx. 011111 S A B 0010010110 1 stwx 011111 S A B 0010010111 0 mtmsr 011111 S A B 011111 D A 00000 OE 0011001000 Rc addzex 011111 D A 00000 OE 0011001010 Rc 1 011111 S stbx 011111 S subfmex 011111 addmex 011111 mullwx 1 dcbtst mtsr mtsrin 0 0010110111 0 stwux subfzex 00000 0011010010 0 A B 0011010111 0 D A 00000 OE 0011101000 Rc D A 00000 OE 0011101010 Rc 011111 D A B OE 0011101011 Rc 011111 S 00000 B 0011110010 0 011111 00000 A B 0011110110 0 SR stbux 011111 S A B addx 011111 D A B dcbt 011111 00000 A B 0100010110 0 lhzx 011111 D A B 0100010111 0 eqvx 011111 S A B 0100011100 Rc 1,4 011111 00000 00000 B 0100110010 0 eciwx 011111 D A B 0100110110 0 lhzux 011111 D A B 0100110111 0 xorx 011111 S A B 0100111100 Rc 2 011111 D 0101010011 0 tlbie mfspr 0011110111 OE spr 0100001010 0 Rc lhax 011111 D A B 0101010111 0 tlbia 1,4 011111 00000 00000 00000 0101110010 0 mftb 011111 D 0101110011 0 lhaux 011111 D A B 0101110111 0 sthx 011111 S A B 0110010111 0 tbr orcx 011111 S A B 0110011100 Rc ecowx 011111 S A B 0110110110 0 sthux 011111 S A B 0110110111 0 orx 011111 S A B 0110111100 Rc divwux 011111 D A B Motorola MPCxxx INSTRUCTION SET OE 0111001011 Rc 8 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mtspr 2 011111 S dcbi 1 011111 00000 A nandx 011111 S A divwx 011111 mcrxr 011111 3 011111 lwbrx lfsx lswx spr D 0111010011 0 B 0111010110 0 B 0111011100 Rc A B 00000 00000 1000000000 0 D A B 1000010101 0 011111 D A B 1000010110 0 011111 D A B 1000010111 0 00 crfD OE 0111101011 Rc srwx 011111 S A B 1000011000 Rc tlbsync 1,4 011111 00000 00000 00000 1000110110 0 mfsr 1 011111 D 00000 1001010011 0 lswi 3 011111 D A NB 1001010101 0 sync 011111 00000 00000 00000 1001010110 0 SR lfdx 011111 D A B 1001010111 0 lfdux 011111 D A B 1001110111 0 mfsrin 1 011111 D 00000 B 1010010011 0 stswx 3 011111 S A B 1010010101 0 stwbrx 011111 S A B 1010010110 0 3 011111 S A NB 1011010101 0 lhbrx 011111 D A B 1100010110 0 srawx 011111 S A B 1100011000 Rc srawix 011111 S A SH 1100111000 Rc eieio 011111 00000 00000 00000 1101010110 0 stswi 9 0 sthbrx 011111 S A B 1110010110 0 extshx 011111 S A 00000 1110011010 Rc extsbx 011111 S A 00000 1110111010 Rc icbi 011111 00000 A B 1111010110 0 dcbz 011111 00000 A B 1111110110 0 lwz 100000 D A d lwzu 100001 D A d lbz 100010 D A d lbzu 100011 D A d stw 100100 S A d MPCxxx INSTRUCTION SET Motorola Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 stwu 100101 S A d stb 100110 S A d stbu 100111 S A d lhz 101000 D A d lhzu 101001 D A d lha 101010 D A d lhau 101011 D A d sth 101100 S A d sthu 101101 S A d lmw 3 101110 D A d stmw 3 101111 S A d 1 Supervisor-level instruction Supervisor- and user-level instruction 3 Load and store string or multiple instruction 4 PowerPC Optional instruction 2 Motorola MPCxxx INSTRUCTION SET 10 Instructions Grouped by Functional Categories Tables 3 through 30 list the PowerPC instructions grouped by function. Key: Reserved bits Table 3. Integer Arithmetic Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addx 31 D A B OE 266 Rc addcx 31 D A B OE 10 Rc addex 31 D A B OE 138 Rc addi 14 D A SIMM addic 12 D A SIMM addic. 13 D A SIMM addis 15 D A SIMM addmex 31 D A 00000 OE 234 Rc addzex 31 D A 00000 OE 202 Rc divwx 31 D A B OE 491 Rc divwux 31 D A B OE 459 Rc mulhwx 31 D A B 0 75 Rc mulhwux 31 D A B 0 11 Rc mulli 07 D A mullwx 31 D A B OE 235 Rc negx 31 D A 00000 OE 104 Rc subfx 31 D A B OE 40 Rc subfcx 31 D A B OE 8 Rc subficx 08 D A subfex 31 D A B OE 136 Rc subfmex 31 D A 00000 OE 232 Rc subfzex 31 D A 00000 OE 200 Rc Motorola SIMM SIMM MPCxxx INSTRUCTION SET 11 Table 4. Integer Compare Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 cmp 31 crfD 0 L A cmpi 11 crfD 0 L A cmpl 31 crfD 0 L A cmpli 10 crfD 0 L A B 0000000000 0 SIMM B 32 0 UIMM Table 5. Integer Logical Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 andx 31 S A B 28 Rc andcx 31 S A B 60 Rc andi. 28 S A UIMM andis. 29 S A UIMM cntlzwx 31 S A 00000 26 Rc eqvx 31 S A B 284 Rc extsbx 31 S A 00000 954 Rc extshx 31 S A 00000 922 Rc nandx 31 S A B 476 Rc norx 31 S A B 124 Rc orx 31 S A B 444 Rc orcx 31 S A B 412 Rc ori 24 S A UIMM oris 25 S A UIMM xorx 31 S A 316 Rc xori 26 S A UIMM xoris 27 S A UIMM B Table 6. Integer Rotate Instructions Name 12 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rlwimix 22 S A SH MB ME Rc rlwinmx 20 S A SH MB ME Rc rlwnmx 21 S A SH MB ME Rc MPCxxx INSTRUCTION SET Motorola Table 7. Integer Shift Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 slwx 31 S A B 24 Rc srawx 31 S A B 792 Rc srawix 31 S A SH 824 Rc srwx 31 S A B 536 Rc Table 8. Integer Load Instructions Name Motorola 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lbz 34 D A d lbzu 35 D A d lbzux 31 D A B 119 0 lbzx 31 D A B 87 0 lha 42 D A d lhau 43 D A d lhaux 31 D A B 375 0 lhax 31 D A B 343 0 lhz 40 D A d lhzu 41 D A d lhzux 31 D A B 311 0 lhzx 31 D A B 279 0 lwz 32 D A d lwzu 33 D A d lwzux 31 D A B 55 0 lwzx 31 D A B 23 0 MPCxxx INSTRUCTION SET 13 Table 9. Integer Store Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 stb 38 S A d stbu 39 S A d stbux 31 S A B 247 0 stbx 31 S A B 215 0 sth 44 S A d sthu 45 S A d sthux 31 S A B 439 0 sthx 31 S A B 407 0 stw 36 S A d stwu 37 S A d stwux 31 S A B 183 0 stwx 31 S A B 151 0 Table 10. Integer Load and Store with Byte Reverse Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lhbrx 31 D A B 790 0 lwbrx 31 D A B 534 0 sthbrx 31 S A B 918 0 stwbrx 31 S A B 662 0 Table 11. Integer Load and Store Multiple Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lmw 3 46 D A d stmw 3 47 S A d Table 12. Integer Load and Store String Instructions Name 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lswi 3 31 D A NB 597 0 lswx 3 31 D A B 533 0 stswi 3 31 S A NB 725 0 3 31 S A B 661 0 stswx 14 0 MPCxxx INSTRUCTION SET Motorola Table 13. Memory Synchronization Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 eieio 31 00000 00000 00000 854 0 isync 19 00000 00000 00000 150 0 lwarx 31 D A B 20 0 stwcx. 31 S A B 150 1 sync 31 00000 00000 00000 598 0 Table 14. Branch Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bx 18 bcx 16 BO BI bcctrx 19 BO BI 00000 528 LK bclrx 19 BO BI 00000 16 LK LI AA LK BD AA LK Table 15. Condition Register Logical Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 crand 19 crbD crbA crbB 257 0 crandc 19 crbD crbA crbB 129 0 creqv 19 crbD crbA crbB 289 0 crnand 19 crbD crbA crbB 225 0 crnor 19 crbD crbA crbB 33 0 cror 19 crbD crbA crbB 449 0 crorc 19 crbD crbA crbB 417 0 crxor 19 crbD crbA crbB 193 0 mcrf 19 00000 0000000000 0 crfD 00 crfS 00 Table 16. System Linkage Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rfi 1 19 00000 00000 sc 17 00000 00000 Motorola 00000 50 000000000000000 MPCxxx INSTRUCTION SET 0 1 0 15 Table 17. Trap Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tw 31 TO A twi 03 TO A B 4 0 SIMM Table 18. Processor Control Instructions Name 0 5 mcrxr 31 mfcr 31 mfmsr 1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 crfS 00 00000 00000 512 0 D 00000 00000 19 0 31 D 00000 00000 83 0 mfspr 2 31 D spr 339 0 mftb 31 D tpr 371 0 mtcrf 31 S 144 0 mtmsr 1 31 S 146 0 mtspr 2 31 D 467 0 0 0 CRM 00000 00000 spr Table 19. Cache Management Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dcbf 31 00000 A B 86 0 dcbi 1 31 00000 A B 470 0 dcbst 31 00000 A B 54 0 dcbt 31 00000 A B 278 0 dcbtst 31 00000 A B 246 0 dcbz 31 00000 A B 1014 0 icbi 31 00000 A B 982 0 Table 20. Lookaside Buffer Management Instructions Name 16 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tlbia 1,4 31 00000 00000 00000 370 0 tlbie 1,4 31 00000 00000 B 306 0 tlbsync1,4 31 00000 00000 00000 566 0 MPCxxx INSTRUCTION SET Motorola Table 21. External Control Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 eciwx 31 D A B 310 0 ecowx 31 S A B 438 0 1 Supervisor-level instruction Supervisor- and user-level instruction 3 Load and store string or multiple instruction 2 Motorola MPCxxx INSTRUCTION SET 17 Instructions Sorted by Form Tables 23 through 32 list the MPCxxx instructions grouped by form. Key: Reserved bits Table 23. I-Form OPCD LI AA LK Specific Instruction Name 0 bx 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 18 LI AA LK Table 24. B-Form OPCD BO BI BD AA LK Specific Instruction Name 0 bcx 5 6 7 16 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BO BI BD AA LK 000000000000000 1 0 Table 25. SC-Form 00000 OPCD 00000 Specific Instruction Name sc 0 5 17 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 00000 00000 000000000000000 1 0 Table 26. D-Form OPCD D A d OPCD D A SIMM OPCD S A d OPCD A UIMM OPCD crfD 0 L A SIMM OPCD crfD 0 L A UIMM A SIMM OPCD Motorola S TO MPCxxx INSTRUCTION SET 19 Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addi 14 D A SIMM addic 12 D A SIMM addic. 13 D A SIMM addis 15 D A SIMM andi. 28 S A UIMM andis. 29 S A UIMM cmpi 11 crfD 0 L A SIMM cmpli 10 crfD 0 L A UIMM lbz 34 D A d lbzu 35 D A d lha 42 D A d lhau 43 D A d lhz 40 D A d lhzu 41 D A d 3 46 D A d lwz 32 D A d lwzu 33 D A d mulli 7 D A SIMM ori 24 S A UIMM lmw oris 25 S A UIMM stb 38 S A d stbu 39 S A d sth 44 S A d sthu 45 S A d 3 47 S A d stw 36 S A d stwu 37 S A d subfic 08 D A SIMM twi 03 TO A SIMM xori 26 S A UIMM xoris 27 S A UIMM stmw Table 27 DS-Form 20 MPCxxx INSTRUCTION SET Motorola Table 28. X-Form OPCD D A B XO 0 OPCD D A NB XO 0 OPCD D 00000 B XO 0 OPCD D 00000 00000 XO 0 OPCD D 00000 XO 0 OPCD S A B XO Rc OPCD S A B XO 1 OPCD S A B XO 0 OPCD S A NB XO 0 OPCD S A 00000 XO Rc OPCD S 00000 B XO 0 OPCD S 00000 00000 XO 0 OPCD S 00000 XO 0 OPCD S A SH XO Rc 0 SR 0 SR OPCD crfD 0 L A B XO 0 OPCD crfD 00 A B XO 0 OPCD crfD 00 00000 XO 0 OPCD crfD 00 00000 00000 XO 0 OPCD crfD 00 00000 XO Rc crfS 00 IMM 0 OPCD TO A B XO 0 OPCD D 00000 B XO Rc OPCD D 00000 00000 XO Rc OPCD crbD 00000 00000 XO Rc OPCD 00000 A B XO 0 OPCD 00000 00000 B XO 0 OPCD 00000 00000 00000 XO 0 andx 31 S A B 28 Rc andcx 31 S A B 60 Rc cmp 31 crfD 0 L A B 0 0 cmpl 31 crfD 0 L A B 32 0 cntlzwx 31 S A 00000 26 Rc dcbf 31 00000 A B 86 0 Specific Instructions Motorola MPCxxx INSTRUCTION SET 21 dcbi 1 31 00000 A B 470 0 dcbst 31 00000 A B 54 0 dcbt 31 00000 A B 278 0 dcbtst 31 00000 A B 246 0 dcbz 31 00000 A B 1014 0 eciwx 31 D A B 310 0 ecowx 31 S A B 438 0 eieio 31 00000 00000 00000 854 0 eqvx 31 S A B 284 Rc extsbx 31 S A 00000 954 Rc extshx 31 S A 00000 922 Rc icbi 31 00000 A B 982 0 lbzux 31 D A B 119 0 lbzx 31 D A B 87 0 lhaux 31 D A B 375 0 lhax 31 D A B 343 0 lhbrx 31 D A B 790 0 lhzux 31 D A B 311 0 lhzx 31 D A B 279 0 lswi 3 31 D A NB 597 0 lswx 3 31 D A B 533 0 lwarx 31 D A B 20 0 lwbrx 31 D A B 534 0 lwzux 31 D A B 55 0 lwzx 31 D A B 23 0 mcrxr 31 00000 00000 512 0 mfcr 31 D 00000 00000 19 0 mfmsr 1 31 D 00000 00000 83 0 mfsr 1 31 D 00000 595 0 mfsrin 1 31 D 00000 B 659 0 mtmsr 1 31 S 00000 00000 146 0 mtsr 1 31 S 00000 210 0 1 31 S 00000 B 242 0 nandx 31 S A B 476 Rc norx 31 S A B 124 Rc mtsrin 22 crfD 00 0 0 SR SR MPCxxx INSTRUCTION SET Motorola orx 31 S A B 444 Rc orcx 31 S A B 412 Rc slwx 31 S A B 24 Rc srawx 31 S A B 792 Rc srawix 31 S A SH 824 Rc srwx 31 S A B 536 Rc stbux 31 S A B 247 0 stbx 31 S A B 215 0 sthbrx 31 S A B 918 0 sthux 31 S A B 439 0 sthx 31 S A B 407 0 stswi 3 31 S A NB 725 0 3 31 S A B 661 0 stwbrx 31 S A B 662 0 stwcx. 31 S A B 150 1 stwux 31 S A B 183 0 stwx 31 S A B 151 0 sync 31 00000 00000 00000 598 0 tlbia 1,4 31 00000 00000 00000 370 0 tlbie 1,4 31 00000 00000 B 306 0 tlbsync1,4 31 00000 00000 00000 566 0 tw 31 TO A B 4 0 xorx 31 S A B 316 Rc stswx Table 29. XL-Form OPCD BO BI 00000 XO LK OPCD crbD crbA crbB XO 0 00000 XO 0 00000 XO 0 OPCD crfD OPCD 00 00000 crfS 00 00000 Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bcctrx 19 BO BI 00000 528 LK bclrx 19 BO BI 00000 16 LK crand 19 crbD crbA crbB 257 0 Motorola MPCxxx INSTRUCTION SET 23 crandc 19 crbD crbA crbB 129 0 creqv 19 crbD crbA crbB 289 0 crnand 19 crbD crbA crbB 225 0 crnor 19 crbD crbA crbB 33 0 cror 19 crbD crbA crbB 449 0 crorc 19 crbD crbA crbB 417 0 crxor 19 crbD crbA crbB 193 0 isync 19 00000 00000 00000 150 0 mcrf 19 00000 0 0 1 19 00000 50 0 rfi 24 crfD 00 00000 crfS 00 00000 MPCxxx INSTRUCTION SET Motorola Table 30. XFX-Form OPCD D OPCD D OPCD S OPCD D spr 0 XO 0 XO 0 spr XO 0 tbr XO 0 0 CRM Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mfspr 2 31 D spr 339 0 mftb 31 D tbr 371 0 mtcrf 31 S 144 0 2 31 D 467 0 mtspr 0 0 CRM spr Table 31. XO-Form OPCD D A B OE XO Rc OPCD D A B 0 XO Rc OPCD D A 00000 OE XO Rc Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addx 31 D A B OE addcx 31 D A B addex 31 D A B addmex 31 D A addzex 31 D divwx 31 266 Rc OE 10 Rc OE 138 Rc 00000 OE 234 Rc A 00000 OE 202 Rc D A B OE 491 Rc divwux 31 D A B OE 459 Rc mulhwx 31 D A B 0 75 Rc mulhwux 31 D A B 0 11 Rc mullwx 31 D A B OE 235 Rc negx 31 D A 00000 OE 104 Rc subfx 31 D A B OE 40 Rc subfcx 31 D A B OE 8 Rc subfex 31 D A B OE 136 Rc subfmex 31 D A 00000 OE 232 Rc subfzex 31 D A 00000 OE 200 Rc Motorola MPCxxx INSTRUCTION SET 25 Table 32. M-Form OPCD S A SH MB ME Rc OPCD S A B MB ME Rc Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rlwimix 20 S A SH MB ME Rc rlwinmx 21 S A SH MB ME Rc rlwnmx 23 S A B MB ME Rc 1 Supervisor-level instruction Supervisor- and user-level instruction 3 Load and store string or multiple instruction 4 PowerPC Optional instruction 2 26 MPCxxx INSTRUCTION SET Motorola Instruction Set Legend Table 33 provides general information on the MPCxxx instruction set (such as the architectural level, privilege level, and form). Table 33. MPCxxx Instruction Set Legend UISA VEA OEA Supervisor Level Optional Form addx √ XO addcx √ XO addex √ XO addi √ D addic √ D addic. √ D addis √ D addmex √ XO addzex √ XO andx √ X andcx √ X andi. √ D andis. √ D bx √ I bcx √ B bcctrx √ XL bclrx √ XL cmp √ X cmpi √ D cmpl √ X cmpli √ D cntlzwx √ X crand √ XL crandc √ XL creqv √ XL crnand √ XL crnor √ XL Motorola MPCxxx INSTRUCTION SET 27 UISA VEA Supervisor Level Optional Form cror √ XL crorc √ XL crxor √ XL √ dcbf X √ dcbi √ X dcbst √ X dcbt √ X dcbtst √ X dcbz √ X divwx √ XO divwux √ XO eciwx √ √ X ecowx √ √ X eieio √ X eqvx √ X extsbx √ X extshx √ X UISA VEA OEA Supervisor Level Optional Form icbi √ X isync √ XL lbz √ D lbzu √ D lbzux √ X lbzx √ X UISA 28 OEA VEA OEA Supervisor Level Optional Form lha √ D lhau √ D lhaux √ X lhax √ X lhbrx √ X lhz √ D lhzu √ D MPCxxx INSTRUCTION SET Motorola lhzux √ X lhzx √ X lmw 2 √ D lswi 2 √ X lswx 2 √ X lwarx √ X lwbrx √ X lwz √ D lwzu √ D lwzux √ X lwzx √ X mcrf √ XL mcrxr √ X mfcr √ X √ √ X √ √ XFX mfsr √ √ X mfsr 3 √ √ mfsrin √ √ mfsrin 3 √ √ √ X OEA Supervisor Level Optional Form mfmsr mfspr 1 √ UISA X X √ mftb mtcrf VEA √ XFX √ XFX mtmsr √ √ mtmsr 3 √ √ √ √ XFX mtsr √ √ X mtsr 3 √ √ mtsrin √ √ mtsrin 3 √ √ mtspr 1 √ X √ √ X X X √ X mulhwx √ XO mulhwux √ XO mulli √ D mullwx √ XO Motorola MPCxxx INSTRUCTION SET 29 nandx √ X negx √ XO norx √ X orx √ X orcx √ X ori √ D oris √ D rfi √ √ rfi 3 √ √ √ XL rlwimix √ M rlwinmx √ M rlwnmx √ M UISA VEA OEA Supervisor Level Optional √ Form sc √ slwx √ X srawx √ X srawix √ X srwx √ X stb √ D stbu √ D stbux √ X stbx √ X sth √ D sthbrx √ X sthu √ D sthux √ X sthx √ X UISA VEA OEA SC Supervisor Level Optional Form stmw 2 √ D 2 √ X stswx 2 √ X stw √ D stwbrx √ X stwcx. √ X stswi 30 XL MPCxxx INSTRUCTION SET Motorola stwu √ D stwux √ X stwx √ X subfx √ XO subfcx √ XO subfex √ XO subfic √ D subfmex √ XO subfzex √ XO sync √ X tlbia √ √ √ X tlbie √ √ √ X tlbsync √ √ X tw √ X twi √ D xorx √ X xori √ D xoris √ D 1 Supervisor- and user-level instruction and store string or multiple instruction 3 PowerPC Optional instruction 2 Load Motorola MPCxxx INSTRUCTION SET 31