E DATASHEET ADDENDUM 82371AB (PIIX4) PCI ISA IDE Xcelerator Timing Specifications September 1997 Order Number: 290548-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 82371AB (PIIX4) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-4725 or call 1-800-548-4725 COPYRIGHT © INTEL CORPORATION, 1997 CG-041493 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS 82371AB (PIIX4) PCI ISA IDE XCELERATOR FEATURES Supported Kits for both Pentium and Pentium Pro Microprocessors 82430TX ISA Kit 82440LX ISA/DP Kit Multifunction PCI to ISA Bridge Supports PCI at 30 MHz and 33 MHz Supports PCI Rev 2.1 Specification Supports Full ISA or Extended I/O (EIO) Bus Supports full Positive Decode or Subtractive Decode of PCI Supports ISA/EIO at 1/4 of PCI Frequency Supports Both Mobile and Desktop Deep Green Environments 3.3V Operation With 5V Tolerant Buffers Ultra-Low Power for Mobile Environments Power-On Suspend and Soft-OFF for Desktop Environment All Registers Readable/Restorable for Proper Resume From 0V Suspend Power Management Logic Global and Local Device Management Suspend/Resume Logic Supports Thermal Alarm Support for External Microcontroller Full Support for Advanced Configuration and Power Interface (ACPI) Specification and OS Directed Power Management Integrated IDE Controller Independent Timing of Up to 4 Drives PIO Mode 4 Transfers Up to 14 Mbytes/sec PRELIMINARY Supports “Ultra DMA/33” Synchronous DMA Mode Transfers Up to 33 Mbytes/sec Integrated 8 x 32-Bit Buffer for IDE PCI Burst Transfers Supports Glue-Less “Swap-Bay” Option With Full Electrical Isolation Enhanced DMA Controller Two 82C37 DMA Controllers Supports PCI DMA With 3 PC/PCI Channels and Distributed DMA Protocols (Simultaneously) Fast Type-F DMA for Reduced PCI Bus Usage Interrupt Controller Based on Two 82C59 15 interrupt support Independently Programmable for Edge/Level Sensitivity Supports Optional I/O APIC Serial Interrupt Input Timers based on 82C54 System Timer, Refresh Request, Speaker Tone Output USB Two USB 1.0 Ports for Serial Transfers at 12 or 1.5 Mbit/sec Supports Legacy Keyboard and Mouse Software With USB-Based Keyboard and Mouse Supports UHCI Design Guide Revision 1.1 Interface SMBus Host interface Allows CPU to Communicate via SMBus Slave Interface Allows External SMBus Master to Control Resume Events Real-Time Clock 256-Byte Battery-Back CMOS SRAM Includes Date Alarm Two 8-Byte Lockout Ranges 1 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Microsoft Windows* 95 Compliant E 324 mBGA Package REFERENCE INFORMATION: The information in this document is provided as a supplement to the standard package datasheets published for the Intel 82371AB (PIIX4) PCI ISA IDE Xcelerator. Please refer to the standard package datasheet (order number 290562 for the PIIX4) for product information and specifications not found in this document. NOTICE: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. The 82371AB (PIIX4) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. 2 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS CONTENTS PAGE 1.0. INTRODUCTION............................................................................................................................... 5 2.0. ELECTRICAL CHARACTERISTICS................................................................................................... 5 2.1. Absolute Maximum Ratings ............................................................................................................ 5 2.2. D.C. Characteristics ...................................................................................................................... 6 2.3. A.C. Characteristics .................................................................................................................... 10 2.4. Clock, Reset, ISA Bus, X-Bus and Host Timing Diagrams ............................................................. 29 2.5. PCI Timing Diagrams ................................................................................................................... 48 2.6. IDE Timing Diagrams ................................................................................................................... 51 2.7. USB Timing Diagrams.................................................................................................................. 53 2.8. IOAPIC Timing Diagrams ............................................................................................................. 54 2.9. SMBus Timing Diagrams.............................................................................................................. 55 2.10. Ultra DMA/33 Timing Diagrams .................................................................................................. 56 FIGURES Figure 1. Test Load ............................................................................................................................ 29 Figure 2. Clock Timing........................................................................................................................ 29 Figure 3. Reset Inactive Timing........................................................................................................... 30 Figure 4. Reset Active Pulse Width ..................................................................................................... 30 Figure 5. SMI#, EXTSMI# and STPCLK# Timing .................................................................................. 31 Figure 6. Input to PCICLK Setup/Hold Times ....................................................................................... 31 Figure 7. HCLKIN to Output Valid Delay .............................................................................................. 32 Figure 8. 8-Bit ISA Memory Slave Timing (PIIX4 as Master)................................................................. 32 Figure 9. 16-Bit ISA Memory Slave Timing (PIIX4 as Master)............................................................... 33 Figure 10. 8-Bit ISA I/O Slave Timing (PIIX4 as Master) ...................................................................... 34 Figure 11. 16-Bit I/O Slave Timing (PIIX4 as Master) ........................................................................... 35 Figure 12. ISA Master Accessing PCI Memory Timing ......................................................................... 36 Figure 13. ISA Master Accessing PIIX4 Register Timing ...................................................................... 37 Figure 14. NMI Timing ........................................................................................................................ 37 Figure 15. Interrupt Timing.................................................................................................................. 38 Figure 16. ISA Master Miscellaneous Timing ....................................................................................... 38 Figure 17. ISA Master Data Swap Timing ............................................................................................ 39 Figure 18. DMA Compatible Timing (Memory Read)............................................................................. 40 Figure 19. DMA Compatible Timing (Memory Write)............................................................................. 41 Figure 20. DMA Compatible Timing (Data Swap).................................................................................. 42 Figure 21. DMA Type F Timing............................................................................................................ 43 Figure 22. PIIX4-Initiated Refresh Timing ............................................................................................ 44 Figure 23. ISA Master-Initiated Refresh Timing.................................................................................... 45 Figure 24. PIIX4 and ISA Master Access to X-Bus Timing.................................................................... 46 PRELIMINARY 3 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS E Figure 25. Coprocessor Error and Mouse Support Timing ..................................................................... 47 Figure 26. Real Time Clock Timing (RTCALE Generation) .................................................................... 47 Figure 27. Speaker Timing .................................................................................................................. 48 Figure 28. Propagation Delay .............................................................................................................. 48 Figure 29. Valid Delay From Rising Clock Edge ................................................................................... 49 Figure 30. Setup and Hold Times ......................................................................................................... 49 Figure 31. Float Delay ......................................................................................................................... 50 Figure 32. Pulse Width........................................................................................................................ 50 Figure 33. Output Enable Delay ........................................................................................................... 50 Figure 34. IDE PIO Mode .................................................................................................................... 51 Figure 35. IDE Multiword DMA Mode ................................................................................................... 52 Figure 36. Data Signal Rise and Fall Time............................................................................................ 53 Figure 37. Data Jitter .......................................................................................................................... 53 Figure 38. EOP Width Timing .............................................................................................................. 54 Figure 39. PIIX4 to IOAPIC Timing ...................................................................................................... 54 Figure 40. SMBus Timing .................................................................................................................... 55 Figure 41. SMBus Timeout Timing ....................................................................................................... 55 Figure 42. Ultra DMA/33 Drive Initiating a DMA Burst for a Read Command .......................................... 56 Figure 43. Ultra DMA/33 Sustained Synchronous DMA Burst................................................................ 57 Figure 44. Ultra DMA/33 Sustained Synchronous DMA Burst................................................................ 58 Figure 45. Ultra DMA/33 Host Terminating a DMA Burst During a Write Command ................................ 58 TABLES Table 1. Package Thermal Resistance...................................................................................................5 Table 2. DC Characteristics ..................................................................................................................6 Table 3. DC Characteristic Signal Association .......................................................................................8 Table 4. DC Current Characteristics ......................................................................................................9 Table 5. Clock/Reset Timings.............................................................................................................. 10 Table 6. ISA Bus and X-Bus Timings ................................................................................................... 12 Table 7. PCI Interface Timing .............................................................................................................. 23 Table 8. PCI Bus IDE Timing............................................................................................................... 24 Table 9. Universal Serial Bus Timing ................................................................................................... 26 Table 10. IOAPIC Bus Timing.............................................................................................................. 27 Table 11. SMBUS Timing .................................................................................................................... 27 Table 12. Serial IRQ Timing ................................................................................................................ 28 Table 13. Ultra DMA/33 Timing............................................................................................................ 28 Table 14. A.C. Test Loads ................................................................................................................... 29 4 PRELIMINARY E 1.0. 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS INTRODUCTION This document contains the Electrical and the Thermal Specification (ETS) for the 82371AB (PIIX4). PIIX4 is a multi-function PCI device implementing a PCI-to-ISA bridge function, a PCI IDE function, a Universal Serial Bus Host/Hub function, and a Power Management function. The contents of this document are based on simulation and parametric data. This information may be modified as more data is available. REFERENCES The ETS assumes that the reader is familiar with the following documents: • 82371AB PIIX4 External Design Specification • Universal Serial Bus Specification • Universal Host Controller Interface (UHCI) Design Guide • System Management Bus Specification • Serialized IRQ Support for PCI Systems Specification • Distributed DMA Support for PCI Systems Specification 2.0. 2.1. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Case Temperature under Bias ............................................ 0oC to +85oC Storage Temperature ......................................................... -55oC to +150oC Voltage on Any Pin with Respect to Ground ........................ -0.3 to VCC + 0.3V 3.3V Supply Voltage with Respect to Vss ............................ -0.3 to +4.6V 5.0V Supply Voltage with Respect to Vss (VREF) ................. -0.3 to +5.5V Maximum Power Dissipation .............................................. 1.0W WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operating beyond the “Operating Conditions” is not recommended and extended exposure beyond “Operating Conditions” may affect reliability. The 82371AB PIIX4 (BGA) is designed for operation at case temperatures between 0oC and 85oC. The thermal resistances of the package are given in Table 1. Table 1. Package Thermal Resistance Parameter Air Flow Meters/Second (Linear Feet per Minute) 0 (0) 1.0 (196.9) Thetaja (oC/Watt) 29 24.5 Thetajc (oC/Watt) 9.0 PRELIMINARY 5 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS 2.2. D.C. Characteristics Table 2. DC Characteristics Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Symbol Parameter Min Max Unit Notes VCC(RTC) Battery Voltage 2.0 3.6 V VCC(SUS) Standby Voltage 3.0 3.6 V VIL1 Input Low Voltage -0.5 0.3 VCC V 1 VIH1 Input High Voltage 0.5 VCC VCC + 0.5 V 1 VIL2 Input Low Voltage -0.3 0.6 V 1 VIH2 Input High Voltage 1.4 VCC + 0.3 V 1 VIL3 Input Low Voltage -0.5 0.8 V 1 VIH3 Input High Voltage 2.0 VCC5 + 0.5 V 1 VOL1 Output Low Voltage 0.4 V 1 VOH1 Output High Voltage VOL2 Output Low Voltage VOH2 Output High Voltage VOL3 Output Low Voltage VOH3 Output High Voltage VOL4 Output Low Voltage VOH4 Output High Voltage VDI Differential Input Sensitivity VCM Differential Common Mode Range 0.8 VSE Single Ended Rcvr Threshold 0.8 IOL1 Output Low Current IOH1 Output High Current IOL2 Output Low Current IOH2 Output High Current IOL3 Output Low Current IOH3 Output High Current IOL4 Output Low Current IOH4 Output High Current IOL5 Output Low Current IOH5 Output High Current 6 VCC - 0.5 V 1 0.3 V 1, 2 3.6 V 1, 2 0.5 V 1 V 1 V 1 VCC - 0.5 V 1 0.2 V |(USBPx+, USBPx-)| 2.5 V Includes VDI 2.0 V 4 mA 1, @ VOL1 mA 1, @ VOH1 mA 1, @ VOL4 mA 1, @ VOH4 mA 1, @ VOL1 mA 1, @ VOH1 mA 1, @ VOL1 mA 1, @ VOH1 mA 1, @ VOL2 mA 1, @ VOH2 2.8 VCC - 0.5 0.45 -1 10 -3 3 -2 6 -2 2 -0.25 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 2. DC Characteristics Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Symbol Parameter IOL6 Output Low Current IOH6 Output High Current IOL7 Output Low Current IOH7 Output High Current IOL8 Output Low Current IOH8 Output High Current ILI1 Input Leakage Current ILI2 Hi-Z State Data Line Leakage CIN Min Max Unit 6 mA 1, @ VOL1 mA 1, @ VOH1 mA 1, @ VOL1 mA 1, @ VOH1 mA 1, @ VOL3 mA 1, @ VOH3 -2 7 -2 11 -2 Notes ±1 µA +10 µA (0V< VIN< 3.3V) Input Capacitance 12 pF FC=1 MHz COUT Output Capacitance 12 pF FC=1 MHz CI/O I/O Capacitance 12 pF FC=1 MHz CL Crystal Load Capacitance 15 pF -10 7.5 NOTES: 1. Refer to Table 3. for the signals associated with this specification. 2. VOL2 assumes RL of 1.5 kohms to 3.6V and VOH2 assumes RL of 15 kohms to GND. PRELIMINARY 7 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS E Table 3. DC Characteristic Signal Association Symbol VIL1/VIH1 Associated Signals VREF=5.0V: (all 3.3V only inputs except SMBCLK & SMBDATA) PWROK, RSMRST#, RTCX1, TEST, BATLOW#, CONFIG[1:2], EXTSMI#, GPI[1], IRQ8#, LID, RI#, SMBALERT#, PWRBTN#, USBP[1:0]+, USBP[1:0]-, FERR# VREF=3.3V: (all inputs except SMBCLK & SMBDATA) PWROK, RSMRST#, RTCX1, TEST, BATLOW#, CONFIG[1:2], EXTSMI#, GPI[1], IRQ8#, LID, RI#, SMBALERT#, PWRBTN#, USBP[1:0]+, USBP[1:0]-, FERR#, AD[31:0], C/BE[3:0]#, CLKRUN#, DEVSEL#, FRAME#, IDSEL, IRDY#, PHLDA#, SERR#, STOP#, TRDY#, IOCHK#, IOCHRDY, IOCS16#, IOR#, IOW#, LA[23:17], MEMCS16#, MEMR#, MEMW#, REFRESH#, SA[19:0], SBHE#, SD[15:0], ZEROWS#, A20GATE, RCIN#, DREQ[0:3, 5:7], REQ[A:C]#, APICREQ#, IRQ[1, 3:7, 9:12, 14:15], PIRQ[A:D], SERIRQ, CLK48, PCICLK, OSC, PDD[15:0], PDDREQ, PIORDY, SDD[15:0], SDDREQ, SIORDY, OC[1:0]#, PCIREQ[A:D],THRM# VIL2/VIH2 SMBCLK, SMBDATA VIL3/VIH3 VREF=5.0V: (all 5V tolerant inputs) AD[31:0], C/BE[3:0]#, CLKRUN#, DEVSEL#, FRAME#, IDSEL, IRDY#, PHLDA#, SERR#, STOP#, TRDY#, IOCHK#, IOCHRDY, IOCS16#, IOR#, IOW#, LA[23:17], MEMCS16#, MEMR#, MEMW#, REFRESH#, SA[19:0], SBHE#, SD[15:0], ZEROWS#, A20GATE, RCIN#, DREQ[0:3, 5:7], REQ[A:C]#, APICREQ#, IRQ[1, 3:7, 9:12, 14:15], PIRQ[A:D], SERIRQ, CLK48, PCICLK, OSC, PDD[15:0], PDDREQ, PIORDY, SDD[15:0], SDDREQ, SIORDY, OC[1:0]#, PCIREQ[A:D],THRM# VOL1/VOH1 PDA[2:0], PDCS1#, PDCS3#, PDD[15:0], PDDACK#, PDIOR#, PDIOW#, SDA[2:0], SDCS1#, SDCS3#, SDD[15:0], SDDACK#, SDIOR#, SDIOW#, CPU_STP#, EXTSMI#, ZZ, GPO8, PCI_STP#, SMBCLK, SMBDATA, SUS[A:C]#, SUS_STAT[1:2]#, A20M#, CPURST, IGNNE#, INIT, INTR, NMI, SMI#, STPCLK#, BIOSCS#, KBCCS#, MCCS#, PCS0#, PCS1#, RTCALE, RTCCS#, XDIR#, XOE#, SUSCLK, RTCX2, SMBCLK, SMBDATA, APICACK#, APICCS#, IRQ[0, 8], SPKR, GNT[A:C], GPO[0, 8, 27, 28, 30], IRQ9OUT#, AD[31:0], C/BE[3:0]#, CLKRUN#, DEVSEL#, FRAME#, IRDY#, PAR, PCIRST#, PHOLD#, SERR#, STOP#, TRDY#, SERIRQ VOL2/VOH2 USBP[1:0]+, USBP[1:0]- VOL3/VOH3 SLP# VOL4/VOH4 ISA/EIO Output Signals: AEN, BALE, IOCHRDY, IOR#, IOW#, LA[23:17], MEMCS16#, MEMR#, MEMW#, REFRESH#, RSTDRV, SA[19:0], SBHE#, SD[15:0], SMEMR#, SMEMW#, SYSCLK, DACK[0:3, 5:7]#, TC IOL1/IOH1 IDE Output Signals: PDA[2:0], PDCS1#, PDCS3#, PDD[15:0], PDDACK#, PDIOR#, PDIOW#, SDA[2:0], SDCS1#, SDCS3#, SDD[15:0], SDDACK#, SDIOR#, SDIOW# IOL2/IOH2 ISA/EIO Output Signals: AEN, BALE, IOCHRDY, IOR#, IOW#, LA[23:17], MEMCS16#, MEMR#, MEMW#, REFRESH#, RSTDRV, SA[19:0], SBHE#, SD[15:0], SMEMR#, SMEMW#, SYSCLK, DACK[0:3, 5:7]#, TC 8 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 3. DC Characteristic Signal Association Symbol IOL3/IOH3 Associated Signals Power Management Signals: CPU_STP#, EXTSMI#, ZZ, GPO8, PCI_STP#, SMBCLK, SMBDATA, SUS[A:C]#, SUS_STAT[1:2]# CPU Interface Signals: A20M#, CPURST, IGNNE#, INTR, NMI X-Bus Interface Signals: BIOSCS#, KBCCS#, MCCS#, PCS0#, PCS1#, RTCALE, RTCCS#, XDIR#, XOE#, SUSCLK, RTCX2 Other Signals: SMBCLK, SMBDATA, APICACK#, APICCS#, IRQ[0, 8], SPKR, GNT[A:C], GPO[0, 8, 27, 28, 30], IRQ9OUT# IOL4/IOH4 PCI Bus Signals: AD[31:0], C/BE[3:0]#, CLKRUN#, DEVSEL#, FRAME#, IRDY#, PAR, PCIRST#, PHOLD#, SERR#, STOP#, TRDY#, SERIRQ IOL5/IOH5 USB Signals: USBP[1:0]+, USBP[1:0]- IOL6/IOH6 SMI#, STPCLK# IOL7/IOH7 INIT# IOL8/IOH8 SLP# Table 4. DC Current Characteristics Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Symbol Parameter Typ Max Unit 110 155 mA ICC(3V) VCC Supply Current ICC(SUS) ON Suspend Well Supply Current—Full On 3 5 mA ICC(SUS) POS/STR Suspend Well Supply Current—Power On Suspend or Suspend to RAM 30 150 µA ICC(SUS) STD/Soff Suspend Well Supply Current—Suspend to Disk or Soft Off 9 150 µA Icc(RTC) Battery Standby Current 6 8 µA PRELIMINARY Notes VCC(RTC)=3.0V Mech Off State 9 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS 2.3. A.C. Characteristics Table 5. Clock/Reset Timings Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym Parameter Min Max Units Notes Figure 30 33.3 ns 2 PCI Clock Timings PCICLK t1a Period t1b High Time 12.0 ns 2 t1c Low Time 12.0 ns 2 t1c Rise Time 3.0 ns 2 t1d Fall Time 3.0 ns 2 ISA Clock Timings SYSCLK t1f Period 120 ns 2 t1g High Time 49 133.3 ns 2 t1h Low Time 49 ns 2 t1i Rise Time 4 ns 2 t1j Fall Time 4 ns 2 70 ns 2 Oscillator Clock Timings OSC t1l OSC Period 67 t1m High Time 20 t1n Low Time 20 2 ns 2 USB Clock Timings fclk48 Operating Frequency t1p Frequency Tolerance 48 MHz t1q High Time 7 ns 2 t1r Low Time 7 ns 2 t1s Rise Time 1.2 ns 2 t1t Fall Time 1.2 ns 2 ±2500 ppm 1 2 Suspend Clock Timings fsusclk SUSCLK Operating Frequency t1v High Time 10 µs t1w Low Time 10 µs 10 32 KHz PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 5. Clock/Reset Timings Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym Parameter Min Max Units Notes Figure SMBus Clock fsmb SMCLK Operating Frequency 10 16 KHz t2b High Time 4.0 50 µs 40 t2c Low Time 4.7 µs 40 t2d Clock/Data Rise Time 1000 ns 40 t2e Clock/Data Fall Time 300 ns 40 t2f PCIRST#, RSTDRV Driven Inactive After SUS_STATx# is Driven Inactive. 1 RTCCLK 3 t2g CPURST, PCIRST#, RSTDRV Active Pulse Width. Initiated via the RC Register. ms 4 t2h CPURST Driven Inactive After PCIRST# is Driven Inactive. RTCCLK 3 t2i CPURST Valid Delay from PCICLK Rising t2j PWROK, RSMRST# Rise Time t3a Valid Delay from PCICLK 2 ns 7 t3b Active Pulse Width 3 PCICLK 5 t3c Inactive Pulse Width 4 PCICLK 5 2 PCICLK 5 RESET TIMINGS 1 1 2 25 ns 10 ns 29 3 SMI# 25 EXTSMI# t3d Active Pulse Width t3e Inactive Pulse Width 4 PCICLK 5 t3f Valid Setup to PCICLK 10 ns 6 t3g Valid Hold from PCICLK 4 ns 6 t3h Valid Delay from PCICLK 2 ns 7 t3i STPCLK# Inactive Pulse Width 5 PCICLK 5 STPCLK# 25 NOTES: 1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle. 2. The maximum high time (t2b Max) provide a simple guaranteed method for devices to detect bus idle conditions. 3. t2j is measured as a transition time through the threshold region Vol=0.8V and Voh=2.0V. PRELIMINARY 11 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 6. ISA Bus and X-Bus Timings Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym Parameter Min Max Units Type Size Notes Figure PIIX4 AS MASTER TIMINGS BALE t4a BALE Pulse Width 50 ns M,I/O 8,16 8,9,10, 11 t4b BALE Driven Active from MEMx#, Iox# Inactive 44 ns M,I/O 8,16 8,9,10, 11 LA[23:17] t5a LA[23:17] Valid Setup to BALE Inactive 150 ns M 8,16 7 8,9 t5b LA[23:17] Valid Hold from BALE Inactive 26 ns M 8,16 t5c LA[23:17] Valid Setup to MEMx# Active 150 ns M 16 9 t5d LA[23:17] Valid Setup to MEMx# Active 173 ns M 8 8 t5e LA[23:17] Invalid from MEMx# Active 39 ns M 16 9 t5f LA[23:17] Invalid from MEMx# Active 39 ns M 8 8 8,9 SA[19:0], SBHE# t6a SA[19:0], SBHE# Valid Setup to MEMx# Active 34 ns M 16 13,15 t6b SA[19:0], SBHE# Valid Setup to Iox# Active 100 ns I/O 16 11 t6c SA[19:0], SBHE# Setup to MEMx#, Iox# Active 100 ns M,I/O 8 9 t6d SA[19:0], SBHE# Valid Setup to BALE Inactive 37 ns M,I/O 8,16 t6e SA[19:0], SBHE# Valid Hold from MEMx#, Iox# Inactive 41 ns M,I/O 8,16 13,15 9 8,9,10, 11 8,9,10, 11 MEMR#, MEMW#, IOR# AND IOW# t7a MEMx# Active Pulse Width (std) 225 ns M 16 9 t7b Iox# Active Pulse Width (std) 160 ns I/O 16 11 t7c MEMx# Active Pulse Width (nws) 105 ns M 16 t7d MEMx# or Iox# Active Pulse Width (std) 520 ns M,I/O 8 t7e MEMx# or Iox# Active Pulse Width (nws) 160 ns M,I/O 8 t7f MEMx# Inactive Pulse Width 103 ns M 16 12 1 9 8,10 1 8,10 9 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 6. ISA Bus and X-Bus Timings Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym Parameter Min Max Units Type Size Notes Figure t7g MEMx# Inactive Pulse Width 163 ns M 8 t7h Iox# Inactive Pulse Width 163 ns I/O 8,16 8 10,11 t7i MEMx#, Iox# Driven Inactive from IOCHRDY Active 120 ns M,I/O 8,16 8,9,10, 11 ns M 8,16 8,9 SMEMR# and SMEMW# t8a SMEMR# & SMEMW# Propagation Delay from MEMR# and MEMW# 16 Read Data t9a Read Data Driven from MEMR#, IOR# Active 0 ns M,I/O 8,16 8,9,10, 11 t9b Read Data Valid Setup to MEMR#, IOR# 24 ns M,I/O 8,16 8,9,10, 11 t9c Read Data Valid Hold from MEMR#, IOR# Inactive 0 ns M,I/O 8,16 8,9,10, 11 t9d Read Data Tri-Stated from MEMR# and IOR# Inactive ns M,I/O 8,16 8,9,10, 11 -40 ns M,I/O 8,16 8,9,10, 11 Write Data Valid Setup to IOW# Active -40 ns M,I/O 8 Write Data Valid Setup to IOW# Active +23 ns M,I/O 16 t10b Write Data Valid Hold from MEMW#, IOW# Inactive 45 ns M,I/O 8,16 8,9,10, 11 t10c Write Data Tri-Stated from MEMW#, IOW# Inactive ns M,I/O 8,16 8,9,10, 11 t10d Write Data Driven Valid after Read MEMR#, IOR# Inactive ns M,I/O 8,16 8,9,10, 11 41 Write Data t10a Write Data Valid Setup to MEMW# Active 105 41 MEMCS16# t11a MEMCS16# Driven Active from LA[23:17] Valid 94 ns M 16 9 t11b MEMCS16# Inactive from LA[23:17] Valid 91 ns M 8 8 t11c MEMCS16# Valid Hold from LA[23:17] Invalid ns M 16 9 PRELIMINARY 0 13 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 6. ISA Bus and X-Bus Timings Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym t11d Parameter Min MEMCS16# Driven Active from SA[19:2] Valid Max Units Type Size Notes Figure 35 ns M 16 9 IOCS16# t12a IOCS16# Driven Active from Valid SA[19:0] 123 ns I/O 16 11 t12b IOCS16# Inactive from Valid SA[19:0] 91 ns I/O 8 10 t12c IOCS16# Valid Hold from SA[19:0] Invalid ns I/O 16 11 80 ns I/O 16 11 t12d 0 IOCS16# Driven Active from Iox Active ZEROWS# t13a ZEROWS# Driven Active from MEMx# Active 16 ns M 16 9 t13b ZEROWS# Driven Active from MEMx#, Iox# Active 80 ns M,I/O 8 8 t13c ZEROWS# Driven Active from LA[23:17] Valid 180 ns M 16 9 t13d ZEROWS# Driven Active from LA[23:17] Valid 300 ns M 8 8 ZEROWS# t13e ZEROWS# Driven Active from SA[19:0], SBHE# Valid 80 ns M 16 9 t13f ZEROWS# Driven Active from SA[19:0], SBHE# Valid 200 ns M,I/O 8 8,10 AEN t14a AEN Valid Setup to Iox# Driven Active 111 ns I/O 8,16 10,11 t14b AEN Valid Setup to BALE Driven Inactive 111 ns I/O 8,16 10,11 t14c AEN Valid Hold from Iox# Driven Inactive 41 ns I/O 8,16 10,11 IOCHRDY t15a IOCHRDY Driven Valid from MEMx#, Iox# Active 78 ns M,I/O 16 9,11 t15b IOCHRDY Driven Valid from MEMx#, Iox# Active 366 ns M,I/O 8 8,10 14 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 6. ISA Bus and X-Bus Timings Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym t15e Parameter IOCHRDY Inactive Pulse Width Min Max Units Type Size Notes Figure 0.12 15.6 µs M,I/O 8,16 8,9,10, 11 23 ns M 16 12 PIIX4 AS SLAVE TIMINGS LA[23:17] t16a LA[23:17] Valid Setup to MEMx# Active SA[19:0],SBHE# t17a SA[19:0],SBHE# Setup to MEMx# Active 23 ns M 16 12 t17b SA[19:0],SBHE# Setup to Iox# Active 89 ns I/O 8 13 t17c SA[19:0],SBHE# Valid Hold from MEMx#, Iox# Inactive 30 ns M,I/O 8,16 12,13 MEMR#, MEMW#, IOR#, IOW# t18a MEMx# Active Pulse Width 214 ns M 16 12 t18b Iox# Active Pulse Width 509 ns I/O 8 13 t18c MEMx# Inactive Pulse Width 92 ns M 16 12 Iox# Inactive Pulse Width 152 ns I/O 8 13 t18d Read Data t19a Read Data Valid from IOCHRDY Active 69 ns M,I/O 8,16 t19b Read Data Valid from IOR# Active 69 ns I/O 8 t19c Read Data Valid Hold from MEMR#, IOR# Inactive ns M,I/O 8,16 12,13 t19d Read Data Tri-State from MEMR#, IOR# Inactive ns M,I/O 8,16 12,13 0 55 12,13 11 13 Write Data t20a Write Data Valid Setup to MEMW#, IOW# Active -54 ns M,I/O 8,16 12,13 t20b Write Data Valid Hold from MEMW#, IOW# Inactive 14 ns M,I/O 8,16 12,13 MEMCS16# t21a MEMCS16# Driven Active from Valid LA[23:17] 65 ns M 16 12 t21b MEMCS16# Float from Valid LA[23:17] 31 ns M 16 12 PRELIMINARY 15 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 6. ISA Bus and X-Bus Timings Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym t21c Parameter MEMCS16# Valid Hold from LA[23:17] Invalid Min Max 0 Units Type Size ns M 16 Notes Figure 12 IOCHRDY t22a IOCHRDY Inactive from MEMx#, Iox# Active 50 ns M,I/O 8,16 t22b IOCHRDY Float from IOCHRDY Rising 85 ns M,I/O 8,16 t22c IOCHRDY Inactive Pulse Width 2.5 µs M,I/O 8,16 200 ns 14 100 ns 15 240 ns 16 ns 16 ns 16 0.12 12,13 4 12,13 12,13 INTERRUPT AND NMI TIMINGS NMI Timing t23a SERR#, IOCHK# Active to NMI Driven Active Interrupt Timing t24a IRQx Inactive Pulse Width ISA BUS MASTER TIMINGS DACK# t26a DACK#, Inactive from DREQ Inactive Tri-Stating and Driving the Bus t27a PIIX4 Tri-States Address, Data, and Control Signals from DACK#, Active t27b PIIX4 Drives Address, Data, and Control Signals from DACK#, Inactive 30 71 SMEMR# and SMEMW# t28a SMEMR# and SMEMW# Active (falling edge) from MEMR# and MEMW# Active (falling edge) 25 ns 16 t28b SMEMR# and SMEMW# Inactive (rising edge) from MEMR# and MEMW# Inactive (rising edge) 35 ns 16 DATA SWAP LOGIC TIMING (ISA MASTER TO ISA SLAVE) t29a SD[7:0] to SD[15:8] Propagation Delay 26 ns 17 t29b SD[15:8] to SD[7:0] Propagation Delay 26 ns 17 16 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 6. ISA Bus and X-Bus Timings Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym Parameter Min Max Units Type Size Notes Figure 26 ns 2 17 t29c PIIX4 Drives Data Bus from IOR#, IOW#, MEMR# or MEMW# Active t29d PIIX4 Tri-States Bus from IOR#, MEMR#, or SMEMR# Inactive 2 55 ns 2,3 17 t29e PIIX4 Tri-States Bus from IOW#, MEMW#, or SMEMW# Inactive 2 60 ns 2,3 17 DMA COMPATIBLE TIMINGS DREQ t30a DREQ Active Hold from IOR# Active 558 ns 5 19 t30b DREQ Active Hold from IOW# Active 315 ns 5 18 DACK# t31a DACK# Active to IOR# Active 73 ns 19 t31b DACK# Active to IOW# Active 312 ns 18 t31c DACK# Active Hold from IOR# Inactive 100 ns 19 t31d DACK# Active Hold from IOW# Inactive 155 ns 18 AEN and BALE t32a AEN Active to Iox# Active 111 ns 18,19 t32b AEN and BALE Inactive from Iox# Inactive 41 ns 18,19 LA[23:19], SA[19:0], SBHE# t33a LA[23:19],SA[19:0], SBHE# Valid Setup to MEMx# Active 99 ns 18,19 t33b LA[23:19],SA[19:0], SBHE# Valid Hold from MEMx# Inactive 51 ns 18,19 MEMR#, MEMW#, IOR#, IOW# t34a IOW# and MEMW# Active Pulse Width 465 ns 18,19 t34b MEMR# Active Pulse Width 495 ns 18 t34c IOR# Active Pulse Width 760 ns 19 t34d IOW# Inactive Pulse Width (continuous) 465 ns 18 t34e IOR# Inactive Pulse Width (continuous) 160 ns 19 t34f IOR# Active to MEMW# Active 230 ns 19 t34g MEMR# Active to IOW# Active -26 ns 18 PRELIMINARY 17 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 6. ISA Bus and X-Bus Timings Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym Parameter Min Max Units Type Size Notes Figure t34h MEMR# Active Hold from IOW# Inactive 40 ns 18 t34i IOR# Active Hold from MEMW# Inactive 40 ns 19 t34j MEMx# Active Hold from IOCHRDY Active 120 ns 18,19 15 ns 18,19 237 ns 19 ns 19 ns 19 SMEMR# & SMEMW# t35a SMEMR# & SMEMW# Valid from MEMR# and MEMW# Valid Read Data t36a Read Data Valid from IOR# Active t36b Read Data Valid Hold from IOR# Inactive t36c Read Data Float from IOR# Inactive 0 61 Write Data t37a Write Data Valid Setup to IOW# Inactive 225 ns 18 t37b Write Data Valid Hold from IOW# Inactive 36 ns 18 20 DATA SWAP LOGIC TIMING (ISA TO ISA TRANSACTION) t38a SD[7:0] to SD[15:8] Propagation Delay 26 ns t38b SD[15:8] to SD[7:0] Propagation Delay 26 ns t38c PIIX4 Drives Data Bus from IOR# or MEMR# Active 26 ns 2 20 t38d PIIX4 Tri-States Bus from IOR# or MEMR# Inactive 55 ns 2 20 20 TC t39a TC Active Setup to Iox# Inactive 511 ns 6 18,19 t39b TC Active Hold from Iox# Inactive 71 ns 6 18,19 t39h TC Pulse Width 700 ns 18,19 ns 18,19 ns 18,19 IOCHRDY t40b IOCHRDY Valid from MEMx# Active t40c IOCHRDY Inactive Pulse Width 18 315 125 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 6. ISA Bus and X-Bus Timings Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym Parameter Min Max Units Type Size Notes Figure DMA TYPE “F” TIMINGS DREQ t55a DREQ Active Hold from IOR# Active 82 ns 5,16 21 t55b DREQ Active Hold from IOW# Active 82 ns 5,16 21 DACK# t56a DACK# Active to IOR# Active 77 ns 16 21 t56b DACK# Active to IOW# Active 77 ns 16 21 t56c DACK# Active Hold from IOR# Inactive 30 ns 16 21 t56d DACK# Active Hold from IOW# Inactive 30 ns 16 21 AEN and BALE t57a AEN Active to Iox# Active 111 ns 21 t57b AEN and BALE Inactive from Iox# Inactive 41 ns 21 IOR# and IOW# t58a IOR# Active Pulse Width 110 ns 21 t58b IOW# Active Pulse Width 110 ns 21 t58c IOR# Inactive Pulse Width (Continuous) 115 ns 21 t58d IOW# Inactive Pulse Width (Continuous) 115 ns 21 READ DATA t59a Read Data Valid from IOR# Active t59b Read Data Valid Hold from IOR# Inactive t59c 96 2 Read Data Float from IOR# Inactive 61 ns 21 ns 21 ns 21 WRITE DATA t60a Write Data Valid Setup to IOW# Inactive 70 ns 21 t60b Write Data Valid Hold from IOW# Inactive 31 ns 21 40 ns TC t61a TC Active Setup to IOR# Inactive PRELIMINARY 6 21 19 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 6. ISA Bus and X-Bus Timings Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym Parameter Min Max Units Type Size Notes Figure t61b TC Active Setup to IOW# Inactive 40 ns 6 21 t61c TC Active Hold from Iox# Inactive 0 ns 6 21 ns 22,23 ns 22,23 ISA REFRESH TIMINGS REFRESH# t62a REFRESH# Active Setup to MEMR# Active 120 t62b REFRESH# Active Hold from MEMR# Inactive 31 t62c REFRESH# Driven Active to SA[15:0] Valid 11 ns 22,23 t62d REFRESH# Active Hold from SA[15:0] Invalid 11 ns 22,23 260 AEN t63a AEN Driven Active to MEMR# Active 11 ns 22,23 t63b AEN Hold from MEMR# Inactive 11 ns 22,23 SA[15:0] t64a SA[15:0] Valid Setup to MEMR# Active 72 ns 22,23 t64b SA[15:0] Valid Hold from MEMR# Inactive 35 ns 22,23 t64c SA[15:0] Valid Float from MEMR# Inactive 46 120 ns 8 23 MEMR#, SMEMR# t65a MEMR# Active Pulse Width 225 t65b MEMR# Tri-State from MEMR# Inactive 36 t65c MEMR# Driven Inactive from IOCHRDY Active 120 t65d SMEMR# Propagation Delay from MEMR# ns 22,23 ns 22,23 ns 22,23 25 ns 22,23 76 ns 22,23 76 ns 22,23 ns 22,23 120 IOCHRDY t66a IOCHRDY Inactive from MEMR# Active t66b IOCHRDY Valid from MEMR# Active t66c IOCHRDY Inactive Pulse Width 20 120 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 6. ISA Bus and X-Bus Timings Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym Parameter Min Max Units Type Size Notes Figure PIIX4 Driving Bus From REFRESH# t67a PIIX4 Drives Control and Address from REFRESH# Active 5 ns 8 23 PIIX4 AND ISA MASTER ACCESSES TO THE X-BUS BIOSCS#, KBCCS#, RTCCS#, AND PCS0#, PCS1#, MCCS# t68a CS# Driven Active from SA[19:0], LA[23:17] Valid (except BIOSCS#) 35 ns 24 t68b CS# Driven Inactive from SA[16:0], LA[23:17] Invalid (except BIOSCS#) 35 ns 24 XDIR# and XOE# t69a XDIR# Active from IOR#, MEMR# Active 24 —PCI-Initiated Access 25 ns —ISA-Initiated Access 30 ns 29 ns 24 24 t69b BIOSCS#, XOE# Active from Iox#, MEMx# Active t69c XDIR# Active Setup to XOE# Active 2 12 ns t69d BIOSCS#, XOE# Inactive from Iox#, MEMx# Inactive 35 60 ns 9 24 t69f BIOSCS#, XOE# Setup to XDIR# Inactive 2 15 ns 9 24 t69g XOE# Inactive from IOR#, MEMR# Inactive 2 140 ns 10 24 t69i XOE# Inactive Setup to XDIR# Inactive 2 12 ns 10 24 MISCELLANEOUS X-BUS TIMINGS Mouse Timing Support t71a IRQ12/M and IRQ1 Minimum Active Pulse Width (for Mouse Function and Keyboard) 180 ns 25 ns 25 Coprocessor Error Support t73a IGNNE# Active from IOW# Active from Port F0H Access PRELIMINARY 220 21 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 6. ISA Bus and X-Bus Timings Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym t73b Parameter Min IGNNE# Inactive from FERR# Inactive Max Units Type Size Notes Figure 230 ns 25 300 ns 26 Real Time Clock Timing (RTCALE) t75a RTCALE Pulse Width t75b RTCALE Active from IOW# Active 200 26 —PCI-Initiated Access 85 ns —ISA-Initiated Access 156 ns 200 ns Speaker Timing t76a SPKR Valid Delay from OSC Rising 27 NOTES: 1. No-wait-state (ZEROWS#) asserted. 2. This applies to the byte lane that the data has been swapped to. 3. Data is tri-stated from the standard memory commands (SMEMR# or SMEMW#), when they are generated. 4. This specification includes both the time the PIIX4 drives IOCHRDY active and the time it takes thePIIX4 to float IOCHRDY. 5. This applies to the last cycle of a demand mode DMA transfer. 6. Output from PIIX4. 7. 36 ns has been added to the ISA spec to meet ZEROWS# setup requirements. 8. This applies to ISA Master initiated refresh only. 9. PIIX4 as a master cycles only. 10. ISA master cycles only. 11. This applies to the PIIX4 cycles that IOCHRDY is not driven low. 12. This applies to all DACK# signals. 13. 56 ns has been added to the ISA spec to meet MEMCS16# setup requirements. ISA devices are not suppose to use the SA address as part of their MEMCS16# decode. However, some devices do use SA as part of MEMCS16# decode. 14. X-Bus read. 15. For back-to-back “sub cycles” generated as a result of byte assembly or disassembly, this spec is 34 ns. 16. Type F transfers are selected via the MBDMAX Register. 22 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 7. PCI Interface Timing Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym Parameter Min Max Units Notes 11 ns Min: 0 pF Max: 50 pF Figure t77 AD[31:0] Valid Delay 2 t78 AD[31:0] Setup Time 7 ns 30 t79 AD[31:0] Hold Time 0 ns 30 t80 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR, SERR#, IDSEL, DEVSEL# CLOCKRUN#, GNT[A:C]# Valid Delay from PCICLK Rising 2 t81 C/Bes[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR, SERR#, IDSEL, DEVSEL# CLOCKRUN#, GNT[A:C]# Output Enable Delay from PCICLK Rising 2 t82 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, IDSEL, DEVSEL# CLOCKRUN#, Float Delay from PCICLK Rising 2 t83 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, IDSEL, DEVSEL# CLOCKRUN#, REQ[A:C]# Setup Time to PCICLK Rising t84 11 ns Min: 0 pF Max: 50 pF 29 29 ns 33 ns 31 7 ns 30 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, IDSEL, DEVSEL# CLOCKRUN#, REQ[A:C]#, Hold Time from PCLKIN Rising 0 ns 30 t85 PHLD# Valid Delay from PCICLK Rising 2 t86 PHLDA# Setup Time to PCICLK Rising 10 ns 30 t87 PHLDA# Hold Time from PCICLK Rising 0 ns 30 t91 PIRQ[D:A]# Setup Time to PCICLK Rising 1 30 t92 PIRQ[D:A]# Hold Time from PCICLK Rising 1 30 t96 RST# Low Pulse Width 1 28 12 ns ms 0 pF 29 32 NOTES: 1. This signal is internally synchronized. PRELIMINARY 23 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 8. PCI Bus IDE Timing Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym Parameter Min Max Units Notes Figure Primary IDE Timing t102 PDIOW# Active from PCICLK Rising 2 20 ns 34,35 t103 PDIOW# Inactive from PCICLK Rising 2 20 ns 34,35 t104 PDIOR# Active from PCICLK Rising 2 20 ns 34,35 t105 PDIOR# Inactive from PCICLK Rising 2 20 ns 34,35 t106 PDA[2:0] Valid Delay from PCICLK Rising 2 30 ns 34 t107 PDCS1#, PDCS3# Active from PCICLK Rising 2 30 ns 34 t108 PDCS1#, PDCS3# Inactive from PCICLK Rising 2 30 ns 34 t113 PDDACK# Active from PCICLK Rising 2 20 ns 35 t114 PDDACK# Inactive from PCICLK Rising 2 20 ns t114a PDDREQ Setup Time to PCICLK Rising 7 ns 35 t114b PDDREQ Hold from PCICLK Rising 7 ns 35 t115 PDD[15:0] Valid Delay from PCICLK Rising 2 ns 34,35 t115a PDD[15:0] Setup Time to PCICLK Rising 10 ns 34,35 t115b PDD[15:0] Hold from PCICLK Rising 8 ns 34,35 t116 PIORDY Setup Time to PCICLK Rising 7 ns 1 34 t117 PIORDY Hold from PCICLK Rising 7 ns 1 34 t117a PIORDY Inactive Pulse Width 48 ns t118 PIORDY Sample Point from DIOx# Assertion PCICLK 2,3 34 t119 PDIOx# Active Pulse Width PCICLK 2,3 34,35 t120 PDIOx# Inactive Pulse Width PCICLK 3,4 34,35 30 34 Secondary IDE Timing t102 SDIOW# Active from PCICLK Rising 2 20 ns 34,35 t103 SDIOW# Inactive from PCICLK Rising 2 20 ns 34,35 t104 SDIOR# Active from PCICLK Rising 2 20 ns 34,35 t105 SDIOR# Inactive from PCICLK Rising 2 20 ns 34,35 t106 SDA[2:0] Valid Delay from PCICLK Rising 2 30 ns 34 t107 SDCS1#, PDCS3# Active from PCICLK Rising 2 30 ns 34 t108 SDCS1#, PDCS3# Inactive from PCICLK Rising 2 30 ns 34 24 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 8. PCI Bus IDE Timing Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym Parameter Min Max Units Notes Figure t113 SDDACK# Active from PCICLK Rising 2 20 ns t114 SDDACK# Inactive from PCICLK Rising 2 20 ns t114a SDDREQ Setup Time to PCICLK Rising 7 ns 35 t114b SDDREQ Hold from PCICLK Rising 7 ns 35 t115 SDD[15:0] Valid Delay from PCICLK Rising 2 ns 34,35 t115a SDD[15:0] Setup Time to PCICLK Rising 10 ns 34,35 t115b SDD[15:0] Hold from PCICLK Rising 8 ns t116 SIORDY Setup Time to PCICLK Rising 7 ns 1 34 t117 SIORDY Hold from PCICLK Rising 7 ns 1 34 t117a PIORDY Inactive Pulse Width 48 ns t118 SIORDY Sample Point from DIOx# Assertion PCICLK 2,3 34 t119 SDIOx# Active Pulse Width PCICLK 2,3 34,35 t120 SDIOx# Inactive Pulse Width PCICLK 3,4 34,35 30 35 34,35 34 NOTES: 1. IORDY is internally synchronized. This timing is to guarantee recognition on the next clock. 2. This parameter is programmable from 2–5 PCI clocks when the drive mode is Mode 2 or greater. Refer to the ISP field in the IDE Timing Register. 3. The cycle time is the compatible timing when the drive mode is Mode 0/1. Refer to the TIM0/1 field in the IDE timing register. 4. This parameter is programmable from 1–4 PCI clocks when the drive mode is Mode 2 or greater. Refer to the RCT field in the IDE Timing Register. PRELIMINARY 25 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS E Table 9. Universal Serial Bus Timing Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V, TCASE=0°C to +85°C) Sym Parameter Min Max Units Notes Fig Full Speed Source (Note 7) t122 USBPx+, USBPx- Driver Rise Time 4 20 ns 1, CL=50 pF 36 t123 USBPx+, USBPx- Driver Fall Time 4 20 ns 1, CL=50 pF 36 t124 Source Differential Driver Jitter 2,3 37 38 —To Next Transition —For Paired Transitions ns -1 1 ns 175 ns 4 -2 5 ns 5 —To Next Transition -20 20 ns —For Paired Transitions -10 10 ns Source EOP Width t126 Differential to SE0 Transition Skew t127 Receiver Data Jitter Tolerance t126 2 160 t125 t128 -2 EOP Width —Must reject as EOP 40 —Must accept as EOP 85 Differential to SE0 Transition Skew -2 3 37 4 38 ns ns 5 ns 5 ns ns 1,6=50 pF CL=350 pF 36 300 300 1,6 CL=50 pF CL=350 pF 36 ns ns 2,3 37 38 Low Speed Source (Note 8) t127 t128 USBPx+, USBPx- Driver Rise Time 75 USBPx+, USBPx- Driver Fall Time 75 t129 Source Differential Driver Jitter —To Next Transition -2 2 ns —For Paired Transitions -1 1 ns 160 175 ns 4 -2 5 ns 5 —To Next Transition -20 20 ns —For Paired Transitions -10 10 ns t130 Source EOP Width t131 Differential to SE0 Transition Skew t132 Receiver Data Jitter Tolerance t133 t134 26 EOP Width —Must reject as EOP 40 —Must accept as EOP 85 Differential to SE0 Transition Skew -2 3 37 4 38 ns ns 5 ns 5 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS NOTES: 1. Driver output resistance under steady state drive is spec’ed at 28 ohms at minimum and 43 ohms at maximum. 2. Timing difference between the differential data signals. 3. Measured at crossover point of differential data signals. 4. Measured at 50% swing point of data signals. 5. Measured from last crossover point to 50% swing point of data line at leading edge of EOP. 6. Measured from 10% to 90% of the data signal. 7. Full Speed Data Rate has minimum of 11.97 Mbps and maximum of 12.03 Mbps. 8. Low Speed Data Rate has a minimum of 1.48 Mbps and a maximum of 1.52 Mbps. Table 10. IOAPIC Bus Timing Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V TCASE=0°C to +85°C) Sym Parameter Min Max Units Notes Fig t136 APICCS# Setup to MEMx# 2 PCICLK 1 39 t137 SA[19:0] Setup to APICCS# 2 PCICLK 1 39 t138 APICACK# Valid Delay from PCICLK 2.0 t139 APICREQ# Valid Setup to PCICLK t140 APICREQ# Valid Hold from PCICLK 12.0 ns 29 10.0 ns 30 0.0 ns 30 NOTES: 1. With these exceptions, the APIC configuration cycles conform to the 8-bit ISA Memory Slave Timing where PIIX4 is the master. Table 11. SMBUS Timing Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V TCASE=0°C to +85°C) Sym Parameter Min Max Units Notes Fig t141 Bus free time between Stop and Start Condition 4.7 µs 40 t142 Hold time after (repeated) Start Condition. After this period, the first clock is generated 4.0 µs 40 t143 Repeated Start Condition setup time 4.7 µs 40 t144 Stop Condition setup time 4.0 µs 40 t145 Data hold time 300 ns 40 t146 Data setup time 250 t147 Device time out 25 t148 t149 ns 40 35 ms 1 Cumulative clock low extend time (slave device) 25 ms 2 41 Cumulative clock low extend time (master device) 10 ms 3 41 PRELIMINARY 27 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS E NOTES: 1. A device will timeout when any clock low exceeds this value. 2. t148 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. 3. t149 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack, or ack-to-stop. Table 12. Serial IRQ Timing Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V TCASE=0°C to +85°C) Sym Parameter Min Max Units Notes Fig t151 SERIRQ Setup Time to PCICLK Rising 7 ns 30 t152 SERIRQ Hold Time from PCICLK Rising 0 ns 30 Table 13. Ultra DMA/33 Timing Functional Operating Range (VREF=5V ± 5%, VCC=3.3V ± 0.3V TCASE=0°C to +85°C) Sym Parameter(1) Mode 0 (ns) Mode 1 (ns) Mode 2 (ns) Min Min Min Max Max Max Figure t154 Cycle Time (Tcyc)(2) 114 75 55 43 t155 Two Cycle Time (T2cyc) 235 156 117 43 t156 Data Setup Time (Tds) 15 10 7 43 t157 Data Hold Time (Tdh) 5 5 5 43 t158 Data Valid Setup Time (Tdvs) 70 48 34 43 t159 Data Valid Hold Time (Tdvh) 6 6 6 43 t160 Limited Interlock Time (Tli) 0 t161 Interlock Time w/Minimum (Tmli) 20 t162 Envelope Time (Tenv) 20 t163 Ready to pause Time (Trp) 160 125 100 44 t164 DMACK setup/hold Time (Tack) 20 20 20 42,45 150 0 150 20 70 20 0 150 20 70 20 45 45 70 42 NOTES: 1. The specification symbols in parenthesis correspond to the Ultra DMA/33 specification name. 2. These cycle timings are based on the STROBE period as indicated in Figure 44. However, Table 13 in the PIIX4 datasheet refers to cycle time strobe periods as 120 ns, 90 ns and 60 ns for mode 0, 1, and 2 respectively. The datasheet timings are different because they are based on the number of PCI clocks per cycle, not the actual period between the rise and fall of STROBE. 28 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Table 14. A.C. Test Loads Capacitive Load Signals 120 pf REFRESH#, TC, SD[15:0], SA[19:0], SBHE#, LA[23:17], I0CS16#, MEMCS16#, MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW#, AEN, BALE, IOCHRDY, ZEROWS#, RSTDRV, SYSCLK 50 pf DACK#[7:5,3:0], SPKR, INTR, NMI, BIOSCS#, KBCCS#, RTCCS#, PCS[1:0]#, MCCS#, RTCALE, XDIR#, XOE#, IGNNE#, PDD[15:0], SDD[15:0], , APICCS#, DIOR#, DIOW#, PDDACK#, SDDACK#, PDCS1# PDCS3#, SDCS1#, SDCS3CC, PDA[2:0], SDA[2:0]. Output CL CL Includes all Parasitic Capacitance TESTLOAD Figure 1. Test Load 2.4. Clock, Reset, ISA Bus, X-Bus and Host Timing Diagrams Period High Time PCICLK, SYSCLK, OSC 2.0V 0.8V Low Time Fall Time Rise Time CLK_TM Figure 2. Clock Timing PRELIMINARY 29 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS E SUS_STAT[1:2]# t2f PCIRST#, RSTDRV Active Inactive t2h CPURST Active Inactive reset2.vsd Figure 3. Reset Inactive Timing t2g CPURST, PCIRST#, RSTDRV (Write to RC Register) Active 048821_2.vsd Figure 4. Reset Active Pulse Width 30 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS PCICLK t3c t3b S MI# PCICLK t3e t3 d EXTSM I# PCICLK t3i STP CLK# 048823.drw (M) Figure 5. SMI#, EXTSMI# and STPCLK# Timing PC ICL K t3 f t3g EXTSMI# 0 4 8 8 2 4 . d rw (M ) Figure 6. Input to PCICLK Setup/Hold Times PRELIMINARY 31 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS E P C IC L K t 3a,t3h SMI#, EXTSMI#, STPCLK# 04 88 25. drw (M ) Figure 7. HCLKIN to Output Valid Delay t4a BALE t5a t5b LA[23:17] t5f t6d t5d SA[19:0], SBHE# t4b t6c t6e t7d, t7e MEMR#, MEMW# t7g t8a t8a SMEMx# t11b MEMCS16# t13f t13d ZEROWS# t13b t15b t15e t7i IOCHRDY t9a t9b t9c, t9d SD[7:0] R t10d t10a t10b,t10c SD[7:0] W 0488 26_2.vsd Figure 8. 8-Bit ISA Memory Slave Timing (PIIX4 as Master) 32 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS t4a BALE t5a t5b LA[23:17] t6d t6e SA[15:0],SBHE# t5e t7a, t7c t5c MEMR#, MEMW# t4b t6a SMEMW#, SMEMR# t7f t8a t11d t8a t11a MEMCS16# t11c t13e t13c t13a ZEROWS# t7i t15a IOCHRDY t15e t9b t9c, t9d SD[15:0] R t10a t10b, t10c SD[15:0] W t10d 048827_2.vsd Figure 9. 16-Bit ISA Memory Slave Timing (PIIX4 as Master) PRELIMINARY 33 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS AEN t14a t14c t14b t4a BALE t6d t6e SA[19:0], SBHE# t6c t4b t7d, t7e IOR#, IOW# t7h t12b IOCS16# t13f ZEROWS# t13b t15b t15e t7i IOCHRDY t9a t9b t9c,t9d SD[7:0] R t10d t10a t10b, c SD[7:0] W 048828_2.vsd Figure 10. 8-Bit ISA I/O Slave Timing (PIIX4 as Master) 34 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS AEN t14a t14c t14b t4a BALE t6d t6e SA[19:0], SBHE# t6b t7b t4b IOR#, IOW# t7h t12a t12d t12c IOCS16# t15a t15e t7i IOCHRDY t9a t9d, t9c SD[15:0] R t10a t10d t10b, c SD[15:0] W 048829_2.vsd Figure 11. 16-Bit I/O Slave Timing (PIIX4 as Master) PRELIMINARY 35 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS E BALE LA[23:17] t17a SA[19:0], SBHE# t17c t18a t16a t18c MEMR#, MEMW# t22a t22c t22b IOCHRDY t19a t21a MEMCS16# t21b, t21c t19c, t19d SD[7:0] R t20a t20b SD[7:0] W 048830_2.vsd Figure 12. ISA Master Accessing PCI Memory Timing 36 PRELIMINARY E AEN 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Low High BALE SA[19:0], SBHE# t17b t17c t18b IOR#, IOW# t18d t22a t22c IOCHRDY t22b t19a t19b t19c, t19d SD[7:0] R t20b t20a SD[7:0] W 048831.drw Figure 13. ISA Master Accessing PIIX4 Register Timing SERR#, IOCHK# t23a NMI 048832.vsd Figure 14. NMI Timing PRELIMINARY 37 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS IRQx t24a 048833.vsd Figure 15. Interrupt Timing DREQ t 2 6a DACK# AEN t2 7a t 27b S D [1 5: 0] S A [1 5: 0] L A [2 3: 19] BHE# M E M R #, M E M W # IO R# , IO W # MEMR#, M EMW# t 28 a t2 8b SMEMR#, SM EMW# 0 4 88 3 4_2.vsd Figure 16. ISA Master Miscellaneous Timing 38 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS SD[7:0] t29a t29b SD[15:8] IOR#, IOW# MEMR#, MEMW# t29c SD[7:0] or SD[15:8] IOR#, MEMR#, OR SMEMR# t29d SD[7:0] or SD[15:8] IOW#, MEMW#, OR SMEMW# t29e SD[7:0] or SD[15:8] 048835_2.vsd Figure 17. ISA Master Data Swap Timing PRELIMINARY 39 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS DREQ t32a t30b AEN t32b t31b DACK# t31d LA[23:17] SA[15:0] t34j t40b t34a t33b t34g IOW# t33a MEMR# t40c t34d IOCHRDY t34b t35a t34h t35a SMEMR# t37b t37a SD[15:0] t39b t39a TC t39h 048836_2.vsd Figure 18. DMA Compatible Timing (Memory Read) 40 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS DREQ t32a t30a AEN t32b t31a t31c DACK# LA[23:17] SA[19:0] t40b t40c t34j IOCHR DY t34e t34c t34f t34i IOR# t33a t34a t33b MEMW# t35a t35a SMEMW# t36b, t36c t36a SD[15:0] t39a TC t39b t39h 04 8837 Figure 19. DMA Compatible Timing (Memory Write) PRELIMINARY 41 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS E SD[7:0] t38a t38b SD[15:8] IOR#, MEMR# t38d t38c SD[7:0], or SD[15:8] 048838.vsd Figure 20. DMA Compatible Timing (Data Swap) 42 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS DREQ t57a t57b t55b AEN t57b t56d t56b DACK# t56c t58b IOW# t58d MEMR# t60a t60b SD[15:0] t56a t55a IOR# t58a t58c t57a MEMW# t59a t59c, t59b t61b t61c SD[15:0] t61a t61c TC dma_f2.vsd Figure 21. DMA Type F Timing PRELIMINARY 43 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS AEN t63b BALE t62b REFRESH# t62d t64a t62c SA[15:0] t63a t64b t65a t62a MEMR# t65b t65d t65d SMEMR# t66a,b t66c t65c IOCHRDY 048839_2.vsd Figure 22. PIIX4-Initiated Refresh Timing 44 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS AEN t63a BALE t63b High t62a t62b REFRESH# t62d t62c SA[15:0] t65a t64a t64b MEMR# t64c t67a t65b t65d t65d SMEMR# t66a,b t66c t65c IOCHRDY 048840_2.vsd Figure 23. ISA Master-Initiated Refresh Timing PRELIMINARY 45 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS BALE LA[23:17] SA[16:0] t68a t68b PCCS[1:4]#, KBCS#, MCCS#, RTCCS# t69b MEMR#, MEMW#, IOR#, IOW# t69d PIIX4 as Master BIOSCS#, XOE# t69a t69f t69c XDIR# SA[16:0] SA[16:0] ISA Master XOE# t69b t69a t69g t69c t69i XDIR# 048841.vsd Figure 24. PIIX4 and ISA Master Access to X-Bus Timing 46 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS FERR# IRQ13 IOW# (Write to F0h) t73a t73b IGNNE# IRQ12/M, IRQ1 t71a 048844.vsd Figure 25. Coprocessor Error and Mouse Support Timing IOW# t75b t75a RTCALE 048845.vsd Figure 26. Real Time Clock Timing (RTCALE Generation) PRELIMINARY 47 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS E OSC t76a SPKR 048846.vsd Figure 27. Speaker Timing 2.5. PCI Timing Diagrams Input VT Propagation Delay VT Output prop_del.vsd Figure 28. Propagation Delay 48 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Clock 1.5V Valid Delay Output VT val_del.vsd Figure 29. Valid Delay From Rising Clock Edge 1.5V Clock Setup Time Input VT Hold Time VT sethold.vsd Figure 30. Setup and Hold Times PRELIMINARY 49 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS Input VT Float Delay Output floatdel.vsd Figure 31. Float Delay Pulse Width VT VT pulsewid.vsd Figure 32. Pulse Width Clock 1.5V Output Enable Delay Output VT outendel.vsd Figure 33. Output Enable Delay 50 PRELIMINARY E 2.6. 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS IDE Timing Diagrams PCICLK t103,t105 t119 t103,t105 t120 t118 DIOx# t115 t115 DD[15:0] Write write data t115b t115a DD[15:0] Read read data t117 t116 IORDY sample point t117a t106,t107 t106,t107 DA[2:0], CS1#, CS3# idepio_2.vsd Figure 34. IDE PIO Mode PRELIMINARY 51 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS E PCICLK t114b t114a DDREQ[1:0] t113 DDACK[1:0] t102,t104 t103,t105 t119 t120 DIOx# t115b t115a DD[15:0] Read Read Data t115 DD[15:0] Write Read Data t115 Write Data Write Data idedma.vsd Figure 35. IDE Multiword DMA Mode 52 PRELIMINARY E 2.7. 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS USB Timing Diagrams Rise Time 90% CL Fall Time 90% Differential Data Lines 10% 10% CL Full Speed: 4 to 20 ns at CL=50 pF tR tF Los Speed: 75 ns at CL=50 pF, 300 ns at CL=350 pF USB_1.vsd Figure 36. Data Signal Rise and Fall Time Tperiod Crossover Points Differential Data Lines Consecutive Transitions Paired Transitions USB_2.vsd Figure 37. Data Jitter PRELIMINARY 53 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS E Tperiod Data Crossover Level Differential Data Lines EOP Width USB_3.vsd Figure 38. EOP Width Timing 2.8. IOAPIC Timing Diagrams SA[19:0] t137 t136 APICCS# MEMx# apic_01.vsd Figure 39. PIIX4 to IOAPIC Timing 54 PRELIMINARY E 2.9. 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS SMBus Timing Diagrams t2e t2c t2d CLK t142 t145 t143 t146 t2b t144 Data smbtm_2.vsd t141 Figure 40. SMBus Timing Start Stop t148 CLKack t149 CLKack t149 SMB CLK SMB smbusto.vsd Figure 41. SMBus Timeout Timing PRELIMINARY 55 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS 2.10. E Ultra DMA/33 Timing Diagrams DMARQ (drive) t164 DMACK# (host) t162 STOP (host) t162 DMARDY# (host) STROBE (drive) t164 DD[15:0] DA[2:0], CS[1:0] udma1.vsd Figure 42. Ultra DMA/33 Drive Initiating a DMA Burst for a Read Command 56 PRELIMINARY E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS t155 t154 t154 t158 t158 STROBE @ sender t159 t159 t159 Data @ sender t156 t156 STROBE @ receiver t157 t157 t157 Data @ receiver udma2.vsd Figure 43. Ultra DMA/33 Sustained Synchronous DMA Burst PRELIMINARY 57 E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS t163 STOP (host) DMARDY# STROBE DATA udma3.vsd Figure 44. Ultra DMA/33 Sustained Synchronous DMA Burst DMARQ (drive) t161 t164 DMACK# (host) DMARDY# (host) t160 STROBE (drive) DATA (drive) CRC udma4.vsd Figure 45. Ultra DMA/33 Host Terminating a DMA Burst During a Write Command 58 PRELIMINARY UNITED STATES, Intel Corporation 2200 Mission College Blvd., P.O. Box 58119, Santa Clara, CA 95052-8119 Tel: +1 408 765-8080 JAPAN, Intel Japan K.K. 5-6 Tokodai, Tsukuba-shi, Ibaraki-ken 300-26 Tel: + 81-29847-8522 FRANCE, Intel Corporation S.A.R.L. 1, Quai de Grenelle, 75015 Paris Tel: +33 1-45717171 UNITED KINGDOM, Intel Corporation (U.K.) Ltd. Pipers Way, Swindon, Wiltshire, England SN3 1RJ Tel: +44 1-793-641440 GERMANY, Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/ Muenchen Tel: +49 89/99143-0 HONG KONG, Intel Semiconductor Ltd. 32/F Two Pacific Place, 88 Queensway, Central Tel: +852 2844-4555 CANADA, Intel Semiconductor of Canada, Ltd. 190 Attwell Drive, Suite 500 Rexdale, Ontario M9W 6H8 Tel: +416 675-2438