APA2037 3W Stereo Fully Differential Audio Power Amplifier Features to 5V and is available in a TQFN5x5-20A package. The built-in feedback resistors can minimize the external High PSRR and Excellent RF Rectification Immunity Low Crosstalk component counts and save the PCB space. High PSRR and fully differential architecture increase immunity to 3W Per Channel Output Power into 3Ω Load at VDD=5V noise and RF rectification. In addition to these features, a short startup time and small package size make the Thermal and Over-Current Protections APA2037 is an ideal choice for LCD TVs and notebook PCs and Portable devices. Built-in Feedback Resistors Eliminate The APA2037 also integrates the de-pop circuitry that reduces the pops and click noises during power on/off and External Components Counts • Space Saving Package – TQFN5x5-20A shutdown mode operation. Both Thermal and over-current protections are integrated to avoid the IC to be de- Lead Free and Green Devices Available (RoHS Compliant) stroyed by over temperature and short-circuit. The APA2037 is capable of driving 3W at 5V into 3Ω speaker. Applications LCD TVs Pin Configuration Notebook, PCs Portable Devices 15 RBYPASS • • • Simplified Application Circuit 11 LBYPASS • 12 LINP • • The APA2037 is a stereo, fully differential Class-AB audio amplifier which can operate with supply voltage from 2.4V Fully Differential Class-AB Amplifier 13 LINN • • Operating Voltage: 2.4V~5.5V 14 RSD • • • General Description 10 NC RINP 16 LOUTN NC 18 RINN ROUTP 7 LVDD NC 20 Right Channel Speaker 6 LOUTN ROUTP 1 ROUTN RINP 8 NC RVDD 19 APA2037 Right Channel Input TQFN5x5-20A Top View GND 5 LINP 9 LSD RINN 17 Left Channel Speaker LOUTP 4 LOUTP ROUTN 3 LINN GND 2 Left Channel Input =Thermal Pad (connected the Thermal Pad to GND plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 1 www.anpec.com.tw APA2037 Ordering and Marking Information Package Code QB : TQFN5x5-20A Operating Ambient Temperature Range I : -40 to 85 ° C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APA2037 Assembly Material Handling Code Temperature Range Package Code APA2037 QB : XXXXX - Date Code APA2037 XXXXX Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol Parameter VDD Supply Voltage (LVDD, RVDD to GND) VIN Input Voltage (LINN, LINP, RINN, RINP, LSD, RSD to GND) TJ Maximum Junction Temperature TSTG TSDR PD Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds Power Dissipation Rating Unit -0.3 to 6 V -0.3 to VDD+0.3 V 150 ο -65 to +150 ο 260 ο C C C Internally Limited W Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter θJA Thermal Resistance -Junction to Ambient θJC Thermal Resistance -Junction to Case Typical Value Unit TQFN5x5-20A (Note 2) 40 ο TQFN5x5-20A (Note 3) 8 ο C/W C/W Note 2: Please refer to “ Layout Recommendation”, the Thermal Pad on the bottom of the IC should soldered directly to the PCB’s ThermalPad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz copper thickness. Note 3: The case temperature is measured at the center of the Thermal Pad on the underside of the TQFN5X5-32A package. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 2 www.anpec.com.tw APA2037 Recommended Operating Conditions Symbol Parameter Range Unit 2.4 ~ 5.5 V VDD Supply Voltage VIH High Level Threshold Voltage LSD, RSD 1.8 ~VDD V VIL Low Level Threshold Voltage LSD, RSD 0 ~ 0.35 V VIC Common Mode Input Voltage 0.5 ~ VDD-0.5 Operating Ambient Temperature Range -40 ~ 85 ο Operating Junction Temperature Range -40 ~ 125 ο Speaker Resistance C C Ω 3~ Electrical Characteristics o VDD=5V, Gnd=0V, TA= 25 C (unless otherwise noted) Symbol Parameter IDD Supply Current ISD Shutdown Current II Input Current Gain TSTART-UP RSD Test Conditions APA2037 Typ. Max. 6 12 Unit mA LSD = RSD = 0V - 1 5 µA LSD, RSD - 0.1 - µA 36kΩ Ri 40kΩ Ri 44kΩ Ri V/V RL=4Ω Start-Up Time from End of Shutdown Min. - - 65 - ms 90 100 110 kΩ RL = 3Ω - 2.4 - RL = 4Ω - 2.1 - RL = 8Ω 1 1.3 - RL = 3Ω - 3 - RL = 4Ω - 2.6 - RL = 8Ω - 1.6 - - 0.05 - - 0.035 - - 105 - - 80 - - 60 - - 105 - dB Cb1=Cb2 = 0.22µF Resistance from Shutdown to GND VDD=5V, TA=25° C THD+N = 1% PO Output Power THD+N = 10% fin = 1kHz THD+N Crosstalk Total Harmonic Distortion Pulse Noise Channel separation PSRR Power Supply Rejection Ratio CMRR Common-Mode Rejection Ratio fin = 1kHz RL = 4Ω PO= 1.5W RL = 8Ω PO= 0.9W PO=130mW, RL =8Ω, fin = 1kHz Cb1 = Cb2= 0.22µF, RL = 8Ω, VRR=0.2VPP, fin = 217Hz Cb1 = Cb2= 0.22µF, RL = 8Ω, VIC=0.2VPP, fin = 217Hz With A-weighting Filter PO = 1.3W, RL = 8Ω W % dB S/N Signal to Noise Ratio VOS Output Offset Voltage RL = 8Ω - 5 20 mV Vn Noise Output Voltage Cb1 = Cb2= 0.22µF, With A-weighting Filter - 15 - µV (rms) Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 3 www.anpec.com.tw APA2037 Electrical Characteristics (Cont.) o VDD=5V, GND=0V, TA= 25 C (unless otherwise noted) Symbol Parameter APA2037 Test Conditions Unit Min. Typ. Max. RL = 3Ω - 1.2 - RL = 4Ω - 1 - RL = 8Ω - 0.65 - RL = 3Ω - 1.5 - THD+N = 10% fin = 1kHz RL = 4Ω - 1.3 - RL = 8Ω - 0.8 - Total Harmonic Distortion Pulse Noise - 0.07 - fin = 1kHz RL = 4Ω PO = 0.7W RL = 8Ω PO= 0.45W - 0.05 - Channel separation PO=65mW, RL=8Ω, fin=1kHz - 105 - - 78 - - 60 - - 103 - VDD=3.6V, TA=25° C THD+N = 1% PO THD+N Crosstalk Output Power PSRR Power Supply Rejection Ratio CMRR Common-Mode Rejection Ratio Cb1 = Cb2= 0.22µF, RL = 8Ω, VRR=0.2VPP, fin = 217Hz Cb1 = Cb2= 0.22µF, RL = 8Ω, VIC=0.2VPP, fin = 217Hz With A-weighting Filter PO = 0.65W, RL = 8Ω W % dB S/N Signal to Noise Ratio VOS Output Offset Voltage RL = 8Ω - 5 20 mV Noise Output Voltage Cb1 = Cb2= 0.22µF, With A-weighting Filter - 15 - µV (rms) RL = 3Ω - 0. 5 - RL = 4Ω - 0.45 - RL = 8Ω - 0.3 - RL = 3Ω - 0.7 - RL = 4Ω - 0.6 - - 0.35 - - 0.1 - - 0.08 - - 105 - - 75 - - 60 - - 100 - - 5 20 mV - 15 - µV (rms) Vn VDD=2.4V, TA=25° C THD+N = 1% PO Output Power THD+N = 10% fin = 1kHz THD+N Crosstalk Total Harmonic Distortion Pulse Noise Channel Separation PSRR Power Supply Rejection Ratio CMRR Common-Mode Rejection Ratio S/N Signal to Noise Ratio VOS Output Offset Voltage Vn Noise Output Voltage Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 RL = 8Ω PO = 0.3W, RL = 4Ω fin = 1kHz PO = 0.2W, RL = 8Ω PO=30mW, RL=8Ω, fin=1kHz Cb1 = Cb2= 0.22µF, RL = 8Ω, VRR=0.2VPP, fin = 217Hz Cb1 = Cb2= 0.22µF, RL = 8Ω, VIC=0.2VPP, fin = 217Hz With A-weighting Filter PO = 0.3W, RL = 8Ω RL = 8Ω Cb1 = Cb2= 0.22µF, With A-weighting Filter 4 W % dB www.anpec.com.tw APA2037 Pin Description PIN NO. NAME I/O/P FUNCTION 1 ROUTP O The right channel positive output terminal of speaker amplifier. 2,5 GND P Ground connection for circuitry. 3 ROUTN O The right channel negative output terminal of speaker amplifier 4 LOUTP O The left channel positive output terminal of speaker amplifier. 6 LOUTN O The left channel negative output terminal of speaker amplifier. 7 LVDD P Left channel supply voltage input pin. 8,10,18,20 NC - No connection. I Left channel shutdown mode control signal input pin, place left channel speaker amplifier in shutdown mode when held low. 9 LSD 11 LBYPASS P Left channel bypass voltage input pin. 12 LINP I The non-inverting input of left channel amplifier. LINP is connected to ground (Gnd node) via a capacitor for single-end (SE) input signal. 13 LINN I The inverting input of left channel amplifier. LINN is used as audio input terminal, typically. 14 RSD I Right channel shutdown mode control signal input pin, place left channel speaker amplifier in shutdown mode when held low. 15 RBYPASS P Right channel bypass voltage input pin. 16 RINP I The non-inverting input of right channel amplifier. RINP is connected to ground (Gnd node) via a capacitor for single-end (SE) input signal. 17 RINN I The inverting input of right channel amplifier. RINN is used as audio input terminal, typically. 19 RVDD P Right channel supply voltage input pin Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 5 www.anpec.com.tw APA2037 Typical Operating Characteristics THD+N vs. Output Power 10 THD+N vs. Output Power 10 RL=3Ω fin=1kHz Ci=0.22µF AV=12dB BW<80kHz 1 THD+N (%) THD+N (%) 1 RL=4Ω fin=1kHz Ci=0.22µF AV=12dB BW<80kHz VDD=2.4V 0.1 VDD=2.4V 0.1 VDD=3.6V VDD=3.6V VDD=5.0V 0.01 10m 100m 1 0.01 10m 5 Output Power (W) 5 THD+N vs. Frequency 1 VDD=2.4V 0.1 VDD=3.6V 0.01 10m VDD=5.0V RL=3Ω Ci=0.22µF AV=12dB BW<80kHz 1 PO=1W 0.1 PO=1.7W VDD=5.0V 100m 1 0.01 3 20 100 Output Power (W) THD+N vs. Frequency THD+N vs. Frequency THD+N (%) PO=1W 0.1 VDD=5.0V RL=8Ω Ci=0.22µF AV=12dB BW<80kHz 1 PO=0.5W 0.1 PO=1.5W 20 100 10k 20k 10 VDD=5.0V RL=4Ω Ci=0.22µF AV=12dB BW<80kHz 1 1k Frequency (Hz) 10 THD+N (%) 1 10 RL=8Ω fin=1kHz Ci=0.22µF AV=12dB BW<80kHz THD+N (%) THD+N (%) 100m Output Power (W) THD+N vs. Output Power 10 0.01 VDD=5.0V 1k PO=0.9W 0.01 10k 20k 20 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 100 1k 10k 20k Frequency (Hz) 6 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Frequency 10 VDD=3.6V RL=4Ω Ci=0.22µF AV=12dB BW<80kHz 1 PO=0.1W PO=0.5W 0.1 PO=0.7W VDD=3.6V RL=8Ω Ci=0.22µF AV=12dB BW<80kHz 1 THD+N (%) THD+N (%) 10 PO=0.1W PO=0.25W 0.1 PO=0.45W 0.01 20 100 1k 0.01 10k 20k 20 100 Frequency (Hz) THD+N vs. Frequency PO=0.1W THD+N (%) THD+N (%) 0.01 10 VDD=2.4V RL=4Ω Ci=0.22µF AV=12dB BW<80kHz 0.1 PO=0.3W VDD=2.4V RL=8Ω Ci=0.22µF AV=12dB BW<80kHz 1 PO=0.1W 0.1 20 100 1k 0.01 10k 20k Frequency (Hz) 20 VDD=5V,THD+N=1% RL=4Ω,THD+N=1% 1.5 1.0 0.5 0.0 RL=8Ω,THD+N=1% 3.0 3.5 4.0 4.5 VDD=3.6V,THD+N=10% VDD=3.6V,THD+N=1% 2.0 VDD=2.4V,THD+N=10% 1.5 VDD=2.4V,THD+N=1% 1.0 0.0 3 5.0 8 13 18 23 28 32 Load Resistance (Ω) Supply Volume (V) Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 2.5 0.5 RL=8Ω,THD+N=10% 2.4 fin=1kHz AV=12dB Mono VDD=5V,THD+N=10% 3.0 RL=3Ω,THD+N=1% 2.0 10k 20k Output Power vs. Load Resistance Output Power (W) Output Power (W) 2.5 1k 3.5 fin=1kHz RL=3Ω,THD+N=10% AV=12dB Mono RL=4Ω,THD+N=10% 3.0 100 PO=0.2W Frequency (Hz) Output Power vs. Supply Voltage 3.5 10k 20k THD+N vs. Frequency 10 1 1k Frequency (Hz) 7 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) Power Dissipation vs. Output Power Power Dissipation vs. Output Power 1.0 1.5 RL=3Ω RL=4Ω 1.0 0.5 VDD=5V fin=1kHz AV=12dB Mono RL=8Ω 0.0 0.0 0.8 Power Dissipation (W) Power Dissipation (W) 2.0 RL=3Ω 0.6 RL=4Ω 0.4 RL=8Ω 0.0 0.5 1.0 1.5 2.0 VDD=3.6V fin=1kHz AV=12dB Mono 0.2 2.5 3.0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 Output Power (W) Output Power (W) Supply Current vs. Output Power Supply Current vs. Output Power 0.8 1.0 RL=3Ω RL=3Ω 0.6 Supply Current (A) Supply Current (A) 0.8 0.6 RL=4Ω 0.4 RL=8Ω VDD=5V fin=1kHz AV=12dB Mono 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 RL=4Ω 0.4 RL=8Ω 0.2 VDD=3.6V fin=1kHz Av=12dB Mono 0.0 0.0 3.0 0.3 Output Power (W) Crosstalk vs. Frequency -20 Crosstalk (dB) -40 -20 -40 -60 -80 Right to Left 1.2 1.5 1.8 TT VDD=5.0V RL=4Ω AV=12dB Ci=0.22µF PO=210mW -60 -80 Right to Left -100 -100 Left to Right -120 -140 20 0.9 Crosstalk vs. Frequency +0 TT VTDDT=5.0V RL=3Ω AV=12dB Ci=0.22µF PO=240mW Crosstalk (dB) +0 0.6 Output Power (W) -140 100 1k 10k 20k 20 100 1k 10k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 Left to Right -120 8 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) Crosstalk vs. Frequency -20 Crosstalk (dB) -40 -60 -80 Right to Left -100 -120 100 1k TTT TT VDD=3.6V -20 RL=4Ω AV=12dB Ci=0.22µF -40 P =100mW O -60 -80 Right to Left -100 Left to Right -140 20 Crosstalk vs. Frequency +0 T VDD=5.0V RL=8Ω AV=12dB Ci=0.22µF PO=130mW Crosstalk (dB) +0 Left to Right -120 -140 20 10k 20k 100 Frequency (Hz) Crosstalk (dB) Crosstalk (dB) -60 -80 Right to Left +0 TTTTT T T VDD=2.4V RL=4Ω -20 AV=12dB Ci=0.22µF -40 PO=45mW -60 -80 Right to Left -100 -100 Left to Right Left to Right -120 20 100 1k -120 -140 10k 20k 20 100 Crosstalk vs. Frequency Output Noise Voltage vs. Frequency +0 TTTTT TT VDD=2.4V -20 RL=8Ω AV=12dB Ci=0.22µF -40 PO=30mW Output Noise Voltage (Vrms) 50u -60 -80 Right to Left -100 Left to Right -120 -140 20 100 10k 20k 1k Frequency (Hz) Frequency (Hz) Crosstalk (dB) 10k 20k Crosstalk vs. Frequency Crosstalk vs. Frequency +0 TTTTT VDD=3.6V RL=8Ω -20 AV=12dB Ci=0.22µF -40 PO=65mW -140 1k Frequency (Hz) 1k Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 Right channel 10u 1u 20 10k 20k Frequency (Hz) Left channel 20u VDD=5.0V RL=8Ω AV=12dB Ci=0.22µF A-Weighting 100 10k 20k 1k Frequency (Hz) 9 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency 50u 20u Output Noise Voltage (Vrms) Output Noise Voltage (Vrms) 50u Right channel Left channel 10u VDD=3.6V RL=8Ω AV=12dB Ci=0.22µF A-Weighting 1u 20 100 1k 20u Right channel 10u Left channel VDD=2.4V RL=8Ω AV=12dB Ci=0.22µF A-Weighting 1u 10k 20k 20 100 Frequency (Hz) PSRR vs. Frequency -30 +0 RL=8Ω AV=12dB Cb=0.22µF Ci=0.22µF Vrr=0.2Vrms Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) -20 -40 -50 -60 -70 VDD=2.4V -80 -90 -100 20 VDD=3.6V VDD=5.0V 100 1k -10 -20 -30 -40 -50 Cb=0.01µF Cb=0.1µF -60 -70 Cb=0.47µF -80 Cb=1µF -90 -100 20 10k 20k VDD=3.6V RL=8Ω AV=12dB Ci=0.22µF Vrr=0.2Vrms 100 Frequency (Hz) Common Mode Rejection Ratio (dB) Common Mode Rejection Ratio (dB) RL=8Ω AV=12dB Vin=0.2V PP Ci=0.22µF -30 -40 -50 VDD=2.4V -60 -70 -80 20 VDD=3.6V VDD=5.0V 100 1k +0 -10 -20 RL=8Ω AV=12dB fin=1kHz Ci=0.22µF -30 -40 -50 VDD=2.4V VDD=3.6V -60 VDD=5.0V -70 -80 -90 -100 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 10k 20k CMRR vs. Common Mode Input Voltage CMRR vs. Frequency -20 1k Frequency (Hz) +0 -10 10k 20k PSRR vs. Frequency +0 -10 1k Frequency (Hz) 1 2 3 4 5 Common Mode Input Voltage (Vrms) 10 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) Frequency Response Frequency Response +14 +220 +12 +140 +8 VDD=5.0V AV=12dB RL=8Ω Ci=0.22µF +6 +4 100 1k 10k 200k +220 +10 +180 Phase +8 +140 VDD=3.6V AV=12dB RL=8Ω Ci=0.22µF +100 +6 +60 +4 10 100 Frequency Response Supply Current vs. Supply Voltage +14 10 +260 AV=12dB No Load Gain 8 +10 +180 Phase +8 +140 VDD=2.4V AV=12dB RL=8Ω Ci=0.22µF +6 100 1k 10k 200k Supply Current (mA) +220 Phase (deg) Gain (dB) +12 10 6 4 +100 2 +60 0 2.4 3.5 4.0 4.5 5.0 Frequency (Hz) Start-up Time vs. Bypass Capacitor GSM Power Supply Rejection vs. Frequency VDD=5.0V AV=12dB No Load 5.5 +0 -40 -80 -120 Output Voltage (dBV) Start-up Time (ms) 3.0 Supply Voltage (V) 200 150 +60 200k 10k Frequency (Hz) Frequency (Hz) +4 1k +100 100 50 -160 +0 Supply Voltage (dBV) 10 +260 Phase (deg) +180 Phase Gain (dB) +10 Phase (deg) Gain (dB) +14 Gain Gain +12 +260 -40 -80 -120 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -160 0 Bypass Capacitor (µF) Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 400 800 1.2k 1.6k 2k Frequency (Hz) 11 www.anpec.com.tw APA2037 Operating Waveforms GSM Power Supply Rejection vs. Time Power On VDD 1 VDD 1 2 VROUT VROUT 2 CH1: VDD, 2V/Div, DC CH1: VDD, 100mV/Div, DC Voltage Offset = 5.0V CH2: VROUT, 20mV/Div, DC CH2: VROUT, 50mV/Div, DC TIME: 20ms/Div TIME: 2ms/Div Shutdown Release Power Off VRSD VDD 1 1 2 VROUT VROUTN 2 CH1: VRSD, 2V/Div, DC CH2: VROUTN, 2V/Div, DC CH1: VDD, 2V/Div, DC CH2: VROUT, 50mV/Div, DC TIME: 20ms/Div TIME: 50ms/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 12 www.anpec.com.tw APA2037 Operating Waveforms (Cont.) Shutdown VRSD 1 VROUTN 2 CH1: VRSD, 2V/Div, DC CH2: VROUTN, 2V/Div, DC TIME: 20ms/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 13 www.anpec.com.tw APA2037 Block Diagram LINN LOUTP LOUTN LINP LBYPASS LSD RSD Bias and Control Circuitrys RINP RBYPASS ROUTN ROUTP RINN Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 14 www.anpec.com.tw APA2037 Typical Application Circuits Single-ended input mode VDD Cs2 Cs1 0.1µF Gnd 10µF 7 LVDD 19 RVDD 40kΩ Rf1 Left Channel Input Ci1 0.22µF Ci2 0.22µF Ri1 LINN 13 4 LOUTP 10kΩ Ri2 6 LOUTN LINP 12 4Ω 10kΩ 40kΩ Rf2 11 LBYPASS LSD 9 SHUTDOWN Control Bias and Control Circuitrys RSD 14 RLSD 100kΩ RRSD Right Channel Input Ci3 Ri3 0.22µF 10kW Ci4 Ri4 0.22µF Cb1 Cb2 40kΩ Rf3 100kΩ RINP 16 13 RBYPASS GND 3 ROUTN 1 ROUTP RINN 17 4Ω 10kW 40kΩ Rf4 2 GND 5 GND Gnd Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 15 www.anpec.com.tw APA2037 Typical Application Circuits (Cont.) Differential input mode VDD Cs2 Cs1 0.1µF Gnd 10µF 7 LVDD 19 RVDD 40kΩ Rf1 Ci1 Left Channel Input 0.22µF Ci2 0.22µF Ri1 LINN 13 4 LOUTP 10kΩ Ri2 6 LOUTN LINP 12 4Ω 10kΩ 40kΩ Rf2 11 LBYPASS LSD 9 SHUTDOWN Control Bias and Control Circuitrys RSD 14 RLSD 100kΩ RRSD Right Channel Input Ci3 Ri3 0.22µF 10kΩ Ci4 Ri4 0.22µF Cb1 Cb2 40kΩ Rf3 100kΩ RINP 16 13 RBYPASS GND 3 ROUTN 1 ROUTP RINN 17 4Ω 10kΩ 40kΩ Rf4 2 GND 5 GND Gnd Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 16 www.anpec.com.tw APA2037 Function Description Application Information Fully Differential Amplifier The power amplifiers are fully differential amplifiers with Input Resistance (Ri) The gain for the APA2037 is set by the external input resistors (Ri) and internal feedback resistors (Rf). differential inputs and outputs. The fully differential amplifier has some advantages versus traditional amplifiers. AV = First, don’t need the input coupling capacitors because the common-mode feedback compensates the input bias. Rf Ri (1) The internal feedback resistors are 40kΩ typical. For the The inputs can be biased from 0.5V~VDD-0.5V, and the outputs are still biased at mid-supply of the power performance of a fully differential amplifier, it’s better to select matching input resistors R i1 , Ri2 , Ri3 ,and R i4 . amplifier. If the inputs are biased at out of the input range, the coupling capacitors are required. Second, the fully Therefore, 1% tolerance resistors are recommended. If the input resistors are not matched, the CMRR and PSRR differential amplifier has outstanding immunity against supply voltage ripple (217Hz) cuased by the GSM RF trans- performance are worse than using matching devices. mitters’ signal which is better than the typical audio amplifier. Input Capacitor (Ci) When the APA2037 is driven by a differential input source, Mono Operation the input capacitor may not be required. The APA2037 has independent shutdown to control each channel’s power amplifier, this allows user switching au- In the single-ended input application, an input capacitor, Ci, is required to allow the amplifier to bias the input sig- dio amplifier to stereo or mono operation and giving flexible control at design. nal to the proper DC level for optimum operation. In this case, Ci and the input resistance Ri form a high-pass filter with the corner frequency determined in the following equation: 1 FC(highpass) = (2) 2πR iCi The value of Ci must be considered carefully because it Thermal Protection The over-temperature circuit limits the junction temperature of the APA2037. When the junction temperature exceeds T J = +150 oC, a thermal sensor turns off the amplifiers, allowing the device to cool. The thermal sensor allows the amplifiers to start-up after the junction tem- directly affects the low frequency performance of the circuit. Consider the example where Ri is 10kΩ and the specifi- o perature cools down to about 125 C. The thermal protection is designed with a 25 oC hysteresis to lower the aver- cation that calls for a flat bass response down to 100Hz. The equation is reconfigured below: age TJ during continuous thermal overload conditions, increasing lifetime of the IC. Ci = 1 2πRiFc (3) Over-Current Protection The APA2037 monitors the output buffers’current. When the over current occurs, the output buffers’current will be Consider the input resistance variation, the Ci should be 0.16µF. Therefore, one would likely choose a value in the reduced and limited to a fold-back current level. The power amplifier will go back to normal operation until range of 0.22µF to 0.47µF. A further consideration for this capacitor is the leakage path from the input source through the over-current situation has been removed. In addition, if the over-current period is long enough and the IC’s the input network (Ri + Rf, Ci) to the load. junction temperature reaches the thermal protection threshold, the IC enters thermal protection mode. input of the amplifier. The offset reduces useful headroom, especially in high gain applications. For this Shutdown Function reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the This leakage current creates a DC offset voltage at the The APA2037 has separated shutdown control for each channel. User can shutdown left channel amplifier by positive side of the capacitor should face the amplifier input in most applications because the DC level of the LSD, or shutdown right channel amplifier by RSD. If all the amplifiers are shutdown, APA2037 only consumes amplifiers’ inputs are held at VDD/2. Please note that it is important to confirm the capacitor polarity in the application. 1µA typical.. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 17 www.anpec.com.tw APA2037 Application Information (Cont.) Effective Bypass Capacitor (CBYPASS) The optimum decoupling is achieved by using two different types of capacitors that target on different types of The BYPASS pin sets the VDD/2 for internal reference by voltage divider. Adding capacitors at this pin to filter the noises on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low noise and regulator the mid-supply rail will increase the PSRR and noise performance. equivalent-series- resistance (ESR) ceramic capacitor, typically 0.1µF, is placed as close as possible to the device The capacitors should be as close to the device as possible. The effect of a larger bypass capacitor will im- VDD lead works best. For filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 10µF prove PSRR due to increased supply stability. or greater placed near the audio power amplifier is recommended. The bypass capacitance also affects to the start time. The large capacitors will increase the start time when device Fully Differential Amplifier Efficiency exist shutdown. The traditional class AB power amplifier efficiency can be calculated starts out as being equal to the ratio of power from the power supply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency. P (4) Efficiency (η) = O PSUP Optimizing Depop Circuitry Circuitry has been included in the APA2037 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the de- where: 2 PO = The value of Ci will also affect turn-on pops. The bypass VOrms = voltage ramp up should be slower than input bias voltage. 2 VOrms V = P RL 2RL vice or the shutdown function will cause the click and pop circuitry. VP 2 2VDD VPP πRL Although the BYPASS pin current source cannot be PSUP = VDD XIDD（AVG）＝ modified, the size of CBYPASS can be changed to alter the device turn-on time and the amount of clicks and pops. IDD（AVG) = 2VP πRL By increasing the value of CBYPASS, turn-on pop can be reduced. However, the tradeoff for using a larger bypass So the Efficiency (η) is: capacitor is to increase the turn-on time for this device. There is a linear relationship between the size of CBYPASS Efficiency ( η) = and the turn-on time. A high gain amplifier intensifies the problem as the small (5) πVP π 2PORL ＝ 4VDD 4VDD (6) Table 1 calculates efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8Ω loads and a 5V supply, the maximum draw on the power supply is almost 1.63W. delta in voltage is multiplied by the gain. Hence, it is advantageous to use low-gain configurations. Power Supply Decoupling Capacitor (Cs) The APA2037 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also prevents the oscillations caused by long lead length between the amplifier and the speaker. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 18 www.anpec.com.tw APA2037 Application Information (Cont.) Fully Differential Amplifier Efficiency (Cont.) R L (Ω) 8 4 3 P O (W) Efficiency (%) IDD(A) 0.25 0.50 1 1.6 0.4 1.2 2 2.6 0.5 1 2 3 30.1 43.1 61.5 77.7 27.5 48.1 62.4 74.1 27.5 38.7 55.1 66.8 0.17 0.23 0.33 0.43 0.29 0.51 0.66 0.70 0.37 0.52 0.74 0.92 1. All components should be placed close to the APA2037. For example, the input capacitor (Ci) should be close to APA2037’s input pins to avoid causing noise cou- P D (W) P SUP (W) 0.58 0.66 0.63 0.46 1.06 1.30 1.21 0.91 1.32 1.58 1.63 1.49 pling to APA2037’s high impedance inputs; the decoupling capacitor (Cs ) should be placed by the 0.83 1.16 1.63 2.06 1.46 2.50 3.21 3.51 1.82 2.58 3.63 4.49 APA2037’s power pin to decouple the power rail noise. 2. The output traces should be short, wide ( >50mil), and symmetric. 3. The input trace should be short and symmetric. 4. The power trace width should greater than 50mil. 5. The TQFN5X5-20A Thermal PAD should be soldered on PCB, and the ground plane needs soldered mask (to avoid short circuit) except the Thermal PAD area. Table 1: Efficiency vs. Output Power in 5-V Differential Amplifier Syetems A final point to remember about linear amplifiers (either SE or Differential) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equation, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. Layout Recommendation ThermalVi a diameter 0.3mm X 9 1mm 4.8mm 5.8mm 0.49mm 0.65mm 3.1mm Solder Mask to Prevent Short Circuit Ground plane for Thermal PAD Figure 5. TQFN5x5-20A Land Pattern Recommendation Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 19 www.anpec.com.tw APA2037 Package Information TQFN5x5-20A A E D b Pin 1 D2 A1 A3 L k E2 Pin 1 Corner e S Y M B O L TQFN5x5-20A INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.25 0.35 0.010 0.014 D 4.90 5.10 0.193 0.201 D2 3.00 3.40 0.118 0.134 E 4.90 5.10 0.193 0.201 E2 3.00 3.40 0.118 0.134 e 0.65 BSC L 0.45 K 0.20 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 0.026 BSC 0.018 0.65 0.026 0.008 20 www.anpec.com.tw APA2037 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TQFN5x5-20A A H T1 C 12.4+2.00 13.0+0.50 -0.00 -0.20 d D 1.5 MIN. 20.2 MIN. W E1 12.0±0.30 1.75±0.10 F 330.0±2.00 50 MIN. 5.5±0.10 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 5.30±0.20 5.30±0.20 1.30±0.20 (mm) Devices Per Unit Package Type TQFN5x5-20A Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 Quantity 2500 21 www.anpec.com.tw APA2037 Taping Direction Information TQFN5x5-20A USER DIRECTION OF FEED Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 22 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA www.anpec.com.tw APA2037 Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Note: All temperatures refer to topside of the package. Measured on the body surface. Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures 3 3 Volume mm ≥350 225 +0/-5°C 225 +0/-5°C Volume mm <350 <2.5 mm 240 +0/-5°C ≥2.5 mm 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures Package Thickness 3 3 3 Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Package Thickness Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 23 www.anpec.com.tw