APA2037 3W Stereo Fully Differential Audio Power Amplifier Features • • • • • • • • • General Description The APA2037 is a stereo, fully differential Class-AB audio amplifier which can operate with supply voltage from 2.4V Operating Voltage: 2.4V~5.5V Fully Differential Class-AB Amplifier to 5V and is available in a TQFN5x5-20A package. The built-in feedback resistors can minimize the external High PSRR and Excellent RF Rectification Immunity component counts and save the PCB space. High PSRR and fully differential architecture increase immunity to Low Crosstalk 3W Per Channel Output Power into 3Ω noise and RF rectification. In addition to these features, a short start-up time and small package size make the Load at VDD=5V Thermal and Over-Current Protections APA2037 is an ideal choice for LCD TVs and notebook PCs and Portable devices. Built-In Feedback Resistors Eliminate The APA2037 also integrates the de-pop circuitry that reduces the pops and click noises during power on/off and External Components Counts Space Saving Package shutdown mode operation. Both Thermal and over-current protections are integrated to avoid the IC being de- – TQFN5x5-20A Lead Free and Green Devices Available stroyed by over temperature and short-circuit. The APA2037 is capable of driving 3W at 5V into 3Ω (RoHS Compliant) speaker. Applications Simplified Application Circuit 11 LBYPASS 12 LINP Portable Devices 13 LINN Notebook, PCs 14 RSD LCD TVs 15 RBYPASS • • • Pin Configuration 10 NC RINP 16 9 LSD RINN 17 TQFN5x5-20A Top View NC 18 LOUTN ROUTN RINP RINN ROUTP 6 LOUTN ROUTP 1 APA2037 Right Channel Input 7 LVDD NC 20 Right Channel Speaker GND 5 LINP 8 NC RVDD 19 Left Channel Speaker LOUTP 4 LOUTP ROUTN 3 LINN GND 2 Left Channel Input =Thermal Pad (connected the Thermal Pad to GND plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 1 www.anpec.com.tw APA2037 Ordering and Marking Information Package Code QB : TQFN5x5-20A Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA2037 Assembly Material Handling Code Temperature Range Package Code APA2037 QB : XXXXX - Date Code APA2037 XXXXX Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol Parameter VDD Supply Voltage (LVDD, RVDD to GND) VIN Input Voltage (LINN, LINP, RINN, RINP, LSD, RSD to GND) TJ Maximum Junction Temperature TSTG TSDR PD Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds Power Dissipation Rating Unit -0.3 to 6 V -0.3 to VDD+0.3 V 150 ο -65 to +150 ο 260 ο C C C Internally Limited W Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter Typical Value (Note 2) θJA Thermal Resistance -Junction to Ambient θJC Thermal Resistance -Junction to Case (Note 3) TQFN5x5-20A TQFN5x5-20A 40 8 Unit ο C/W ο C/W Note 2: Please refer to “ Layout Recommendation”, the Thermal Pad on the bottom of the IC should soldered directly to the PCB’s ThermalPad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz copper thickness. Note 3: The case temperature is measured at the center of the Thermal Pad on the underside of the TQFN5X5-20A package. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 2 www.anpec.com.tw APA2037 Recommended Operating Conditions Symbol Parameter VDD Supply Voltage VIH High Level Threshold Voltage LSD, RSD VIL Low Level Threshold Voltage LSD, RSD VIC Common Mode Input Voltage Range Unit 2.4 ~ 5.5 V 1.8 ~VDD V 0 ~ 0.35 V 0.5 ~ VDD-0.5 V Operating Ambient Temperature Range Operating Junction Temperature Range Speaker Resistance -40 ~ 85 ο -40 ~ 125 ο C C Ω 3~ Electrical Characteristics o VDD=5V, Gnd=0V, TA= 25 C (unless otherwise noted) Symbol Parameter APA2037 Test Conditions Unit Min. Typ. Max. IDD Supply Current - 6 12 ISD Shutdown Current LSD = RSD = 0V - 1 5 µA LSD, RSD - 0.1 - µA 36kΩ Ri 40kΩ Ri 44kΩ Ri V/V II Input Current Gain TSTART-UP RSD RL=4Ω Start-Up Time from End of Shutdown mA - 65 - ms 90 100 110 kΩ RL = 3Ω - 2.4 - RL = 4Ω - 2.1 - RL = 8Ω 1 1.3 - RL = 3Ω - 3 - RL = 4Ω - 2.6 - RL = 8Ω - 1.6 - RL = 4Ω PO= 1.5W - 0.05 - RL = 8Ω PO= 0.9W - 0.035 - Cb1=Cb2 = 0.22µF Resistance from Shutdown to GND VDD=5V, TA=25° C THD+N = 1% PO Output Power THD+N = 10% fin = 1kHz THD+N Crosstalk Total Harmonic Distortion Pulse Noise fin = 1kHz W % Channel Separation PO=130mW, RL =8Ω, fin = 1kHz - 105 - PSRR Power Supply Rejection Ratio Cb1 = Cb2= 0.22µF, RL = 8Ω, VRR=0.2VPP, fin = 217Hz - 80 - CMRR Common-Mode Rejection Ratio Cb1 = Cb2= 0.22µF, RL = 8Ω, VIC=0.2VPP, fin = 217Hz - 60 - S/N Signal to Noise Ratio With A-weighting Filter PO = 1.3W, RL = 8Ω - 105 - dB VOS Output Offset Voltage RL = 8Ω - 5 20 mV Vn Noise Output Voltage Cb1 = Cb2= 0.22µF, With A-weighting Filter - 15 - µV (rms) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 3 dB www.anpec.com.tw APA2037 Electrical Characteristics (Cont.) o VDD=5V, GND=0V, TA= 25 C (unless otherwise noted) Symbol Parameter APA2037 Test Conditions Unit Min. Typ. Max. RL = 3Ω - 1.2 - RL = 4Ω - 1 - RL = 8Ω - 0.65 - RL = 3Ω - 1.5 - THD+N = 10% fin = 1kHz RL = 4Ω - 1.3 - RL = 8Ω - 0.8 - Total Harmonic Distortion Pulse Noise - 0.07 - fin = 1kHz RL = 4Ω PO = 0.7W RL = 8Ω PO= 0.45W - 0.05 - Channel Separation PO=65mW, RL=8Ω, fin=1kHz - 105 - - 78 - - 60 - - 103 - VDD=3.6V, TA=25° C THD+N = 1% PO THD+N Crosstalk Output Power PSRR Power Supply Rejection Ratio CMRR Common-Mode Rejection Ratio Cb1 = Cb2= 0.22µF, RL = 8Ω, VRR=0.2VPP, fin = 217Hz Cb1 = Cb2= 0.22µF, RL = 8Ω, VIC=0.2VPP, fin = 217Hz With A-weighting Filter PO = 0.65W, RL = 8Ω W % dB S/N Signal to Noise Ratio VOS Output Offset Voltage RL = 8Ω - 5 20 mV Noise Output Voltage Cb1 = Cb2= 0.22µF, With A-weighting Filter - 15 - µV (rms) RL = 3Ω - 0. 5 - RL = 4Ω - 0.45 - RL = 8Ω - 0.3 - RL = 3Ω - 0.7 - RL = 4Ω - 0.6 - - 0.35 - - 0.1 - - 0.08 - - 105 - - 75 - - 60 - - 100 - - 5 20 mV - 15 - µV (rms) Vn VDD=2.4V, TA=25° C THD+N = 1% PO Output Power THD+N = 10% fin = 1kHz THD+N Crosstalk Total Harmonic Distortion Pulse Noise Channel Separation PSRR Power Supply Rejection Ratio CMRR Common-Mode Rejection Ratio S/N Signal to Noise Ratio VOS Output Offset Voltage Vn Noise Output Voltage Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 RL = 8Ω RL = 4Ω, PO = 0.3W fin = 1kHz RL = 8Ω, PO = 0.2W PO=30mW, RL=8Ω, fin=1kHz Cb1 = Cb2= 0.22µF, RL = 8Ω, VRR=0.2VPP, fin = 217Hz Cb1 = Cb2= 0.22µF, RL = 8Ω, VIC=0.2VPP, fin = 217Hz With A-weighting Filter PO = 0.3W, RL = 8Ω RL = 8Ω Cb1 = Cb2= 0.22µF, With A-weighting Filter 4 W % dB www.anpec.com.tw APA2037 Typical Operating Characteristics THD+N vs. Output Power 10 THD+N vs. Output Power 10 RL=3Ω fin=1kHz Ci=0.22µF AV=12dB BW<80kHz 1 THD+N (%) THD+N (%) 1 RL=4Ω fin=1kHz Ci=0.22µF AV=12dB BW<80kHz VDD=2.4V 0.1 VDD=2.4V 0.1 VDD=3.6V VDD=3.6V VDD=5.0V 0.01 10m 100m 1 0.01 10m 5 Output Power (W) 5 THD+N vs. Frequency 1 VDD=2.4V 0.1 VDD=3.6V 0.01 10m VDD=5.0V RL=3Ω Ci=0.22µF AV=12dB BW<80kHz 1 PO=1W 0.1 PO=1.7W VDD=5.0V 100m 1 0.01 3 20 100 Output Power (W) THD+N vs. Frequency THD+N vs. Frequency THD+N (%) PO=1W 0.1 VDD=5.0V RL=8Ω Ci=0.22µF AV=12dB BW<80kHz 1 PO=0.5W 0.1 PO=1.5W 20 100 10k 20k 10 VDD=5.0V RL=4Ω Ci=0.22µF AV=12dB BW<80kHz 1 1k Frequency (Hz) 10 THD+N (%) 1 10 RL=8Ω fin=1kHz Ci=0.22µF AV=12dB BW<80kHz THD+N (%) THD+N (%) 100m Output Power (W) THD+N vs. Output Power 10 0.01 VDD=5.0V 1k PO=0.9W 0.01 10k 20k 20 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 100 1k 10k 20k Frequency (Hz) 5 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Frequency 10 VDD=3.6V RL=4Ω Ci=0.22µF AV=12dB BW<80kHz 1 PO=0.1W PO=0.5W 0.1 PO=0.7W VDD=3.6V RL=8Ω Ci=0.22µF AV=12dB BW<80kHz 1 THD+N (%) THD+N (%) 10 PO=0.1W PO=0.25W 0.1 PO=0.45W 0.01 20 100 1k 0.01 10k 20k 20 100 Frequency (Hz) THD+N vs. Frequency PO=0.1W THD+N (%) THD+N (%) 0.01 10 VDD=2.4V RL=4Ω Ci=0.22µF AV=12dB BW<80kHz 0.1 PO=0.3W VDD=2.4V RL=8Ω Ci=0.22µF AV=12dB BW<80kHz 1 PO=0.1W 0.1 20 100 1k 0.01 10k 20k Frequency (Hz) 20 1k 10k 20k Output Power vs. Load Resistance 3.5 fin=1kHz AV=12dB Mono 3.0 3.0 VDD=5V,THD+N=1% RL=4Ω,THD+N=10% 2.5 RL=3Ω,THD+N=1% 2.0 RL=4Ω,THD+N=1% 1.5 1.0 0.5 RL=8Ω,THD+N=1% 3.0 3.5 4.0 4.5 VDD=3.6V,THD+N=10% VDD=3.6V,THD+N=1% 2.0 VDD=2.4V,THD+N=10% 1.5 VDD=2.4V,THD+N=1% 1.0 0.0 3 5.0 8 13 18 23 28 32 Load Resistance (Ω) Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 2.5 0.5 RL=8Ω,THD+N=10% 2.4 fin=1kHz AV=12dB Mono VDD=5V,THD+N=10% RL=3Ω,THD+N=10% Output Power (W) Output Power (W) 100 PO=0.2W Frequency (Hz) Output Power vs. Supply Voltage 3.5 0.0 10k 20k THD+N vs. Frequency 10 1 1k Frequency (Hz) 6 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) Power Dissipation vs. Output Power Power Dissipation vs. Output Power 1.0 1.5 RL=3Ω RL=4Ω 1.0 0.5 VDD=5V fin=1kHz AV=12dB Mono RL=8Ω 0.0 0.0 0.8 Power Dissipation (W) Power Dissipation (W) 2.0 RL=3Ω 0.6 RL=4Ω 0.4 RL=8Ω 0.0 0.5 1.0 1.5 2.0 VDD=3.6V fin=1kHz AV=12dB Mono 0.2 2.5 3.0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 Output Power (W) Output Power (W) Supply Current vs. Output Power Supply Current vs. Output Power 0.8 1.0 RL=3Ω RL=3Ω 0.6 Supply Current (A) Supply Current (A) 0.8 0.6 RL=4Ω 0.4 RL=8Ω VDD=5V fin=1kHz AV=12dB Mono 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 RL=4Ω 0.4 RL=8Ω 0.2 VDD=3.6V fin=1kHz Av=12dB Mono 0.0 0.0 3.0 0.3 Output Power (W) Crosstalk vs. Frequency -20 Crosstalk (dB) -40 -20 -40 -60 -80 Right to Left 1.2 1.5 1.8 TT VDD=5.0V RL=4Ω AV=12dB Ci=0.22µF PO=210mW -60 -80 Right to Left -100 -100 Left to Right -120 -140 20 0.9 Crosstalk vs. Frequency +0 TT VTDDT=5.0V RL=3Ω AV=12dB Ci=0.22µF PO=240mW Crosstalk (dB) +0 0.6 Output Power (W) -140 100 1k 10k 20k 20 100 1k 10k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 Left to Right -120 7 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) Crosstalk vs. Frequency -20 Crosstalk (dB) -40 -60 -80 Right to Left -100 -120 100 1k TTT TT VDD=3.6V -20 RL=4Ω AV=12dB Ci=0.22µF -40 P =100mW O -60 -80 Right to Left -100 Left to Right -140 20 Crosstalk vs. Frequency +0 T VDD=5.0V RL=8Ω AV=12dB Ci=0.22µF PO=130mW Crosstalk (dB) +0 Left to Right -120 -140 20 10k 20k 100 Frequency (Hz) Crosstalk (dB) Crosstalk (dB) -60 -80 Right to Left +0 TTTTT T T VDD=2.4V RL=4Ω -20 AV=12dB Ci=0.22µF -40 PO=45mW -60 -80 Right to Left -100 -100 Left to Right Left to Right -120 20 100 1k -120 -140 10k 20k 20 100 Output Noise Voltage vs. Frequency Crosstalk vs. Frequency +0 50µ Output Noise Voltage (Vrms) TTTTT TT VDD=2.4V -20 RL=8Ω AV=12dB Ci=0.22µF -40 PO=30mW -60 -80 Right to Left -100 Left to Right -120 -140 20 100 10k 20k 1k Frequency (Hz) Frequency (Hz) Crosstalk (dB) 10k 20k Crosstalk vs. Frequency Crosstalk vs. Frequency +0 TTTTT VDD=3.6V RL=8Ω -20 AV=12dB Ci=0.22µF -40 PO=65mW -140 1k Frequency (Hz) 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 Right channel 10µ 1µ 20 10k 20k Left channel 20µ VDD=5.0V RL=8Ω AV=12dB Ci=0.22µF A-Weighting 100 1k 10k 20k Frequency (Hz) 8 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency 50µ 20u Output Noise Voltage (Vrms) Output Noise Voltage (Vrms) 50u Right channel Left channel 10u VDD=3.6V RL=8Ω AV=12dB Ci=0.22µF A-Weighting 1u 20 100 1k 20µ Right channel 10µ Left channel VDD=2.4V RL=8Ω AV=12dB Ci=0.22µF A-Weighting 1µ 10k 20k 20 100 Frequency (Hz) PSRR vs. Frequency -30 +0 RL=8Ω AV=12dB Cb=0.22µF Ci=0.22µF Vrr=0.2Vrms Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) -20 -40 -50 -60 -70 VDD=2.4V -80 -90 -100 20 VDD=3.6V VDD=5.0V 100 1k -10 -20 -30 -40 -50 Cb=0.01µF Cb=0.1µF -60 -70 Cb=0.47µF -80 Cb=1µF -90 -100 20 10k 20k VDD=3.6V RL=8Ω AV=12dB Ci=0.22µF Vrr=0.2Vrms 100 Frequency (Hz) Common Mode Rejection Ratio (dB) Common Mode Rejection Ratio (dB) RL=8Ω AV=12dB Vin=0.2V PP Ci=0.22µF -30 -40 -50 VDD=2.4V -60 -70 -80 20 VDD=3.6V VDD=5.0V 100 1k +0 -10 -20 RL=8Ω AV=12dB fin=1kHz Ci=0.22µF -30 -40 -50 VDD=2.4V VDD=3.6V -60 VDD=5.0V -70 -80 -90 -100 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 10k 20k CMRR vs. Common Mode Input Voltage CMRR vs. Frequency -20 1k Frequency (Hz) +0 -10 10k 20k PSRR vs. Frequency +0 -10 1k Frequency (Hz) 1 2 3 4 5 Common Mode Input Voltage (Vrms) 9 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) Frequency Response Frequency Response +14 +220 +12 +140 +8 VDD=5.0V AV=12dB RL=8Ω Ci=0.22µF +6 +4 100 1k 10k 200k +220 +10 +180 Phase +8 +140 VDD=3.6V AV=12dB RL=8Ω Ci=0.22µF +100 +6 +60 +4 10 100 Frequency Response Supply Current vs. Supply Voltage +14 10 +260 AV=12dB No Load Gain 8 +10 +180 Phase +8 +140 VDD=2.4V AV=12dB RL=8Ω Ci=0.22µF +6 100 1k 10k 200k Supply Current (mA) +220 Phase (deg) Gain (dB) +12 10 6 4 +100 2 +60 0 2.4 3.5 4.0 4.5 5.0 Frequency (Hz) Start-up Time vs. Bypass Capacitor GSM Power Supply Rejection vs. Frequency VDD=5.0V AV=12dB No Load 5.5 +0 -40 -80 -120 Output Voltage (dBV) Start-up Time (ms) 3.0 Supply Voltage (V) 200 150 +60 200k 10k Frequency (Hz) Frequency (Hz) +4 1k +100 100 50 -160 +0 Supply Voltage (dBV) 10 +260 Phase (deg) +180 Phase Gain (dB) +10 Phase (deg) Gain (dB) +14 Gain Gain +12 +260 -40 -80 -120 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -160 0 Bypass Capacitor (µF) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 400 800 1.2k 1.6k 2k Frequency (Hz) 10 www.anpec.com.tw APA2037 Operating Waveforms GSM Power Supply Rejection vs. Time Power On VDD 1 VDD 1 2 VROUT VROUT 2 CH1: VDD, 2V/Div, DC CH1: VDD, 100mV/Div, DC Voltage Offset = 5.0V CH2: VROUT, 20mV/Div, DC CH2: VROUT, 50mV/Div, DC TIME: 20ms/Div TIME: 2ms/Div Shutdown Release Power Off VRSD VDD 1 1 2 VROUT VROUTN 2 CH1: VRSD, 2V/Div, DC CH2: VROUTN, 2V/Div, DC CH1: VDD, 2V/Div, DC CH2: VROUT, 50mV/Div, DC TIME: 20ms/Div TIME: 50ms/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 11 www.anpec.com.tw APA2037 Operating Waveforms (Cont.) Shutdown VRSD 1 VROUTN 2 CH1: VRSD, 2V/Div, DC CH2: VROUTN, 2V/Div, DC TIME: 20ms/Div Pin Description PIN NO. NAME 1 ROUTP I/O/P FUNCTION O The right channel positive output terminal of speaker amplifier. 2,5 GND P Ground connection for circuitry. 3 ROUTN O The right channel negative output terminal of speaker amplifier 4 LOUTP O The left channel positive output terminal of speaker amplifier. 6 LOUTN O The left channel negative output terminal of speaker amplifier. 7 LVDD P Left channel supply voltage input pin. 8,10,18,20 NC - No connection. I Left channel shutdown mode control signal input pin, place left channel speaker amplifier in shutdown mode when held low. 9 LSD 11 LBYPASS P Left channel bypass voltage input pin. 12 LINP I The non-inverting input of left channel amplifier. LINP is connected to ground (Gnd node) via a capacitor for single-end (SE) input signal. 13 LINN I The inverting input of left channel amplifier. LINN is used as audio input terminal, typically. 14 RSD I Right channel shutdown mode control signal input pin, place left channel speaker amplifier in shutdown mode when held low. 15 RBYPASS P Right channel bypass voltage input pin. 16 RINP I The non-inverting input of right channel amplifier. RINP is connected to ground (Gnd node) via a capacitor for single-end (SE) input signal. 17 RINN I The inverting input of right channel amplifier. RINN is used as audio input terminal, typically. 19 RVDD P Right channel supply voltage input pin Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 12 www.anpec.com.tw APA2037 Block Diagram LINN LOUTP LOUTN LINP LBYPASS LSD RSD Bias and Control Circuitrys RINP RBYPASS ROUTN ROUTP RINN Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 13 www.anpec.com.tw APA2037 Typical Application Circuits Single-ended input mode VDD Cs2 Cs1 0.1µF Gnd 10µF 7 LVDD 19 RVDD 40kΩ Rf1 Left Channel Input Ci1 0.22µF Ci2 0.22µF Ri1 LINN 13 4 LOUTP 10kΩ Ri2 6 LOUTN LINP 12 4Ω 10kΩ 40kΩ Rf2 11 LBYPASS LSD 9 SHUTDOWN Control Bias and Control Circuitrys RSD 14 RLSD 100kΩ RRSD Right Channel Input Ci3 Ri3 0.22µF 10kΩ Ci4 Ri4 0.22µF Cb1 0.22µF Cb2 0.22µF 40kΩ Rf3 100kΩ RINP 16 15 RBYPASS GND 3 ROUTN 1 ROUTP RINN 17 4Ω 10kΩ 40kΩ Rf4 2 GND 5 GND Gnd Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 14 www.anpec.com.tw APA2037 Typical Application Circuits (Cont.) Differential input mode VDD Cs2 Cs1 0.1µF Gnd 10µF 7 LVDD 19 RVDD 40kΩ Rf1 Ci1 Left Channel Input 0.22µF Ci2 0.22µF Ri1 LINN 13 4 LOUTP 10kΩ Ri2 6 LOUTN LINP 12 4Ω 10kΩ 40kΩ Rf2 11 LBYPASS LSD 9 SHUTDOWN Control Bias and Control Circuitrys RSD 14 RLSD 100kΩ RRSD Right Channel Input Ci3 Ri3 0.22µF 10kΩ Ci4 Ri4 0.22µF Cb1 0.22µF Cb2 0.22µF 40kΩ Rf3 100kΩ RINP 16 15 RBYPASS GND 3 ROUTN 1 ROUTP RINN 17 4Ω 10kΩ 40kΩ Rf4 2 GND 5 GND Gnd Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 15 www.anpec.com.tw APA2037 Function Description Fully Differential Amplifier Shutdown Function The power amplifiers are fully differential amplifiers with differential inputs and outputs. The fully differential ampli- The APA2037 has separated shutdown control for each channel. User can shutdown left channel amplifier by fier has some advantages versus traditional amplifiers. First, don’t need the input coupling capacitors because LSD, or shutdown right channel amplifier by RSD. If all the amplifiers are shutdown, APA2037 only consumes the common-mode feedback compensates the input bias. The inputs can be biased from 0.5V to VDD-0.5V, and the 1µA typical. outputs are still biased at mid-supply of the power amplifier. If the inputs are biased at out of the input range, the coupling capacitors are required. Second, the fully differential amplifier has outstanding immunity against supply voltage ripple (217Hz) cuased by the GSM RF transmitters’ signal which is better than the typical audio amplifier. Mono Operation The APA2037 has independent shutdown to control each channel’s power amplifier, this allows user switching audio amplifier to stereo or mono operation and giving flexible control at design. Thermal Protection The over-temperature circuit limits the junction temperature of the APA2037. When the junction temperature exceeds T J = +150 oC, a thermal sensor turns off the amplifiers, allowing the device to cool. The thermal sensor allows the amplifiers to start-up after the junction temperature cools down to about 125 oC. The thermal protection is designed with a 25 oC hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the IC. Over-Current Protection The APA2037 monitors the output buffers’current. When the over current occurs, the output buffers’current will be reduced and limited to a fold-back current level. The power amplifier will go back to normal operation until the over-current situation has been removed. In addition, if the over-current period is long enough and the IC’s junction temperature reaches the thermal protection threshold, the IC enters thermal protection mode. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 16 www.anpec.com.tw APA2037 Application Information Input Resistance (Ri) important to confirm the capacitor polarity in the application. The gain for the APA2037 is set by the external input resistors (Ri) and internal feedback resistors (Rf). Effective Bypass Capacitor (CBYPASS) AV R = f Ri The BYPASS pin sets the VDD/2 for internal reference by voltage divider. Adding capacitors at this pin to filter the noise and regulator the mid-supply rail will increase the (1) The internal feedback resistors are 40kΩ typical. For the PSRR and noise performance. performance of a fully differential amplifier, it’s better to select matching input resistors R i1 , Ri2 , Ri3 ,and R i4 . The capacitors should be as close to the device as possible. The effect of a larger bypass capacitor will im- Therefore, 1% tolerance resistors are recommended. If the input resistors are not matched, the CMRR and PSRR prove PSRR due to increased supply stability. The bypass capacitance also affects to the start time. The performance are worse than using matching devices. large capacitors will increase the start time when device exists shutdown. Input Capacitor (Ci) When the APA2037 is driven by a differential input source, Optimizing Depop Circuitry the input capacitor may not be required. In the single-ended input application, an input capacitor, Circuitry has been included in the APA2037 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully dis- case, Ci and the input resistance Ri form a high-pass filter with the corner frequency determined in the following charged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop equation: FC(highpass ) = 1 2πRiCi circuitry. (2) The value of Ci will also affect turn-on pops. The bypass The value of Ci must be considered carefully because it directly affects the low frequency performance of the circuit. voltage ramp up should be slower than input bias voltage. Consider the example where Ri is 10kΩ and the specification that calls for a flat bass response down to 100Hz. modified, the size of CBYPASS can be changed to alter the device turn-on time and the amount of clicks and pops. The equation is reconfigured below: By increasing the value of CBYPASS, turn-on pop can be reduced. However, the tradeoff for using a larger bypass 1 Ci = 2πRiFc Although the BYPASS pin current source cannot be (3) capacitor is to increase the turn-on time for this device. There is a linear relationship between the size of CBYPASS Consider the input resistance variation, the Ci should be 0.16µF. Therefore, a value in the range of 0.22µF to and the turn-on time. 0.47µF would be chosen. A further consideration for this capacitor is the leakage path from the input source through A high gain amplifier intensifies the problem as the small the input network (Ri + Rf, Ci) to the load. This leakage current creates a DC offset voltage at the vantageous to use low-gain configurations. input of the amplifier. The offset reduces useful headroom, especially in high gain applications. For this Power Supply Decoupling Capacitor (Cs) delta in voltage is multiplied by the gain. Hence, it is ad- The APA2037 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the ensure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also pre- positive side of the capacitor should face the amplifier input in most applications because the DC level of the vents the oscillations caused by long lead length between the amplifier and the speaker. amplifiers’ inputs are held at VDD/2. Please note that it is Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 17 www.anpec.com.tw APA2037 Application Information (Cont.) Table 1: Efficiency vs. Output Power in 5-V Differential Amplifier Syetems Power Supply Decoupling Capacitor (Cs) (Cont.) The optimum decoupling is achieved by using two different types of capacitors that target on different types of RL (Ω) noises on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low 8 equivalent-series- resistance (ESR) ceramic capacitor, typically 0.1µF, is placed as close as possible to the de- PO (W) Efficiency (%) IDD(A) PD (W) PSUP (W) 0.25 30.1 0.17 0.58 0.83 0.50 43.1 0.23 0.66 1.16 1 61.5 0.33 0.63 1.63 1.6 77.7 0.43 0.46 2.06 0.4 27.5 0.29 1.06 1.46 1.2 48.1 0.51 1.30 2.50 vice VDD lead works best. For filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near the audio power amplifier is recommended. 4 Fully Differential Amplifier Efficiency The traditional class AB power amplifier efficiency can be 3 calculated starts out as being equal to the ratio of power from the power supply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency. P (4) Efficiency (η) = O PSUP 3.21 0.91 3.51 0.5 27.5 0.37 1.32 1.82 1 38.7 0.52 1.58 2.58 2 55.1 0.74 1.63 3.63 3 66.8 0.92 1.49 4.49 possible. Note that in equation, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. 2 In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the VP application. 2 PSUP = VDD XIDD（AVG）＝ IDD（AVG) = 1.21 SE or Differential) is how to manipulate the terms in the efficiency equation to the utmost advantage when VOrms V = P RL 2RL VOrms = 0.66 0.70 2VDD VPP πRL Layout Recommendation (5) 2VP πRL 1mm So the Efficiency (η) is: Efficiency ( η) = πVP π 2PORL ＝ 4VDD 4VDD 0.49mm (6) 4.8mm Table 1 calculates efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as 0.65mm power to the load is increased resulting in nearly flat internal power dissipation over the normal operating range. 3.1mm Note that the internal dissipation at full output power is less than in the half power range. Calculating the effi- Solder Mask to Prevent Short Circuit ciency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8Ω Ground plane for Thermal PAD Figure 1. TQFN5x5-20A Land Pattern Recommendation loads and a 5V supply, the maximum draw on the power supply is almost 1.63W. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 ThermalVi a diameter 0.3mm X 9 5.8mm PO = 62.4 74.1 A final point to remember about linear amplifiers (either where: 2 2 2.6 18 www.anpec.com.tw APA2037 Application Information (Cont.) Layout Recommendation (Cont.) 1. All components should be placed close to the APA2037. For example, the input capacitor (Ci) should be close to APA2037’s input pins to avoid causing noise coupling to APA2037’s high impedance inputs; the decoupling capacitor (Cs) should be placed by the APA2037’s power pin to decouple the power rail noise. 2. The output traces should be short, wide ( >50mil), and symmetric. 3. The input trace should be short and symmetric. 4. The power trace width should greater than 50mil. 5. The TQFN5X5-20A Thermal PAD should be soldered on PCB, and the ground plane needs soldered mask (to avoid short circuit) except the Thermal PAD area. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 19 www.anpec.com.tw APA2037 Package Information TQFN5x5-20A A E D b Pin 1 D2 A1 A3 L k E2 Pin 1 Corner e S Y M B O L TQFN5x5-20A INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.25 0.35 0.010 0.014 D 4.90 5.10 0.193 0.201 D2 3.00 3.40 0.118 0.134 E 4.90 5.10 0.193 0.201 E2 3.00 3.40 0.118 0.134 e 0.65 BSC L 0.45 K 0.20 Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 0.026 BSC 0.018 0.65 0.026 0.008 20 www.anpec.com.tw APA2037 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TQFN5x5-20A A H 330.0±2.00 50 MIN. P0 P1 4.0±0.10 T1 C 12.4+2.00 13.0+0.50 -0.00 -0.20 8.0±0.10 P2 D0 2.0±0.05 1.5+0.10 -0.00 d D W E1 F 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.10 D1 T A0 B0 K0 1.5 MIN. 0.6+0.00 -0.40 5.30±0.20 5.30±0.20 1.30±0.20 (mm) Devices Per Unit Package Type TQFN5x5-20A Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 Quantity 2500 21 www.anpec.com.tw APA2037 Taping Direction Information TQFN5x5-20A USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 22 www.anpec.com.tw APA2037 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 23 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA2037 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 24 www.anpec.com.tw