ETC DMA2271

MICRONAS
INTERMETALL
DMA 2271,
DMA 2280,
DMA 2281
C/D/D2–MAC Decoder
MICRONAS
Edition August 5, 1991
6251–331–1E
DMA 2271, DMA 2280, DMA 2281
Contents
Page
Section
Title
3
3
3
1.
1.1.
1.2.
Introduction
General Information
Environment
5
5
5
6
8
9
9
9
11
12
15
17
20
2.
2.1.
2.2.
2.3.
2.4.
2.5.
2.5.1.
2.5.2.
2.5.3.
2.5.4.
2.5.5.
2.5.6.
2.5.7.
Specifications
Outline Dimensions
Pin Connections
Pin Descriptions
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Recommended Crystal Characteristics
Characteristics
DRAM Interface Characteristics
Waveforms
Frequency Responses
21
21
21
21
21
21
21
21
22
22
22
22
22
22
22
22
23
23
23
23
24
24
3.
3.1.
3.1.1.
3.1.2.
3.1.3.
3.1.4.
3.2.
3.2.1.
3.2.2.
3.2.3.
3.2.4.
3.2.5.
3.2.6.
3.2.7.
3.2.8.
3.3.
3.3.1.
3.3.2.
3.3.3.
3.3.4.
3.3.5.
3.3.6.
Functional Description
Clock and Data Recovery
The Code Converter
The Video Clamping Circuit and the AGC Circuit
The Phase Comparator and the PLL Filter
The Data Slicer and the Synchronization Circuit
Video Processing
The Luminance Store
The Luminance Interpolating Filter
The Contrast Multiplier
The Chrominance Store
The Line Interpolating Filter
The Chrominance Interpolating filter
The Color Saturation Multiplier
The Color Multiplier
Sound/Data Processing
The Golay and PT Byte Decoder
The Address Comparator
The Sound Decoder
The Sound Multiplex
The ΦA Audio Clock
The Buffer for Packet 0
25
25
25
25
25
25
26
4.
4.1.
4.2.
4.2.1.
4.2.2.
4.3.
4.3.1.
The Three Serial Interfaces
The S Bus Interface and the S Bus
The IM Bus Interface and the IM Bus
The IM Bus
IM Bus Addresses and Instructions
The Burst Bus
Control and Status Registers
2
DMA 2271, DMA 2280, DMA 2281
The DMA 2271, DMA 2280, and DMA 2281 C/D/
D2–MAC Decoders
1. Introduction
1.1. General Information
Digital real–time signal processor for processing C/D/
D2–MAC video, sound, and data signals digitized by the
VCU 2133 Video Codec in digital CTV receivers according to INTERMETALL's DIGIT 2000 system of or in analog CTV receivers or in stand–alone C/D/D2–MAC decoders (see Figs. 1–1 to 1–3).
1.2. Environment
Fig. 1–1 shows the block diagram of a digital CTV receiver system DIGIT 2000, equipped with C/D/D2–MAC and
Teletext, and suited for the PAL and SECAM standards.
Stand–alone C/D/D2–MAC decoders are shown in Figs.
1–2 and 1–3. These two versions can either be integrated into analog CTV receivers, or can serve as
stand–alone C/D/D2–MAC decoders.
DPU 2553
CCU 3000
Defl.
DRAM
NVM 3060
In order to receive TV channels transmitted via satellite
or cable network using the newly established C/D/
D2–MAC standards instead of PAL or SECAM, decoders are required for decoding the TV video and sound
signals. The DMA 2271, DMA 2280, and DMA 2281 are
suitable for this purpose, in conjunction with the DIGIT
2000 digital TV system and also for stand–alone solutions.
TPU 2735
Video 1/2
VCU 2136
– code converter
– circuitry for clamping, AGC and PLL
1/2
VCU 2136
R
G
B
PVPU 2204
The DMA 2271 is only able to decode D2–MAC/packet
signals, in contrast to the DMA 2280 which decodes D–
MAC/packet signals and the DMA 2281 which decodes
D2, D or C–MAC/packet signals.
The DMA 2271, DMA 2280, and DMA 2281 are a programmable circuits, produced in CMOS technology and
housed in a 68–pin PLCC package. These decoders
contain on a single silicon chip the following functions
(see Fig. 1–4):
SPU 2243
MCU 2600
DMA 2281
AMU 2481
DRAM
Sound
ACP 2371
S1
S2
S3
S4
Fig. 1–1: Block diagram for a multistandard CTV receiver according to the DIGIT 2000 system and
equipped with D2–MAC
– chroma and luma store for expansion of the MAC signal
– chroma and luma interpolating filter
CCU 3000
DRAM
TPU 2735
– contrast multiplier with limiter for the luminance signal
– color saturation multiplier with multiplexer
Defl.
Video VCU 2133
A/D Part
DMA 2281
VCU 2133
D/A Part
R
G
B
AMU 2481
S1
S2
S3
S4
– duobinary decoder (data slicer)
– synchronization
DRAM
– descrambler and de–interleaver
– packet linker
MCU 2600
– packet 0 buffer
– sound decoder and sound multiplexer
– IM bus interface circuit for communicating with the
CCU
Fig. 1–2: Block diagram for a stand–alone C/D/
D2–MAC decoder, equipped with the VCU 2133 Video
Codec for A/D and D/A conversion (reduced chroma
bandwidth)
3
DMA 2271, DMA 2280, DMA 2281
CCU 3000
DRAM
TPU 2735
R
HDAA
Video 1/2
UVC 3130
R
G
B
switch
G
DMA 2281
B
DRAM
S1
S2
S3
S4
AMU 2481
MCU 2600
Fig. 1–3: Block diagram for a stand–alone C/D/
D2–MAC decoder, equipped with the UVC 3130 for
A/D and HDAA or D/A conversion (full chroma bandwidth)
31–38
18
8
ODI
21–24, 27–30
DMA 2271, DMA 2280, DMA 2281
39–46
48
49
Luma
Store
Clamping
AGC
Chroma
Store
Line
Interpolating
Filter
8
Contrast
Multiplier
Color
Multiplexer
Chroma
Interpolating
Filter
Color
Saturation
Multiplier
Phase
Comparator,
PLL Filter
25
26
50–53
Gray
Converter
Luma
Interpolating
Filter
4
Data
Slicers,
Synchronization
57
58
60
69
Descrambler,
Deinterleaver
12
IM–Bus
Interface
13
62
RESET
15
63
Buffer
for
Packet 0
55
56
Fig. 1–4: Block diagram of the DMA 2271, DMA 2280, DMA 2281 C/D/D2–MAC decoders
4
Memory
2–6
9–1
1
8
68
Control
7
64
VSUP
61
8
1
Address
Comparator
14
ΦM
Linker
Golay,
PT byte
and TG
Decoder
T0
54
Packet
Error
Correction,
Expansion,
Error
Concealment
Sound
Multiplex
66
Audio
Clock
Generator
65
16
17
67
DMA 2271, DMA 2280, DMA 2281
2. Specifications
19
leave vacant
20
leave vacant
21
Chroma Output 7 (MSB)
CO7
22
Chroma Output 6
CO6
23
Chroma Output 5
CO5
24
Chroma Output 4
CO4
25
PLL Tuning Data Output
PLLD
26
PLL Tuning Clock Output
PLLC
27
Chroma Output 3
CO3
Fig. 2–1: DMA 2271, DMA 2280, DMA 2281 in 68–pin
PLCC package
28
Chroma Output 2
CO2
29
Chroma Output 1
CO1
Weight approx. 4.5 g,
30
Chroma Output 0 (LSB)
CO0
31
Luma Output 0
LO0
32
Luma Output 1
LO1
33
Luma Output 2
LO2
34
Luma Output 3
LO3
35
Luma Output 4
LO4
36
Luma Output 5
LO5
37
Luma Output 6
LO6
38
Luma Output 7 (MSB)
LO7
39
Baseband Input 7 (MSB)
BI7
40
Baseband Input 6
BI6
41
Baseband Input 5
BI5
42
Baseband Input 4
BI4
43
Baseband Input 3
BI3
44
Baseband Input 2
BI2
45
Baseband Input 1
BI1
46
Baseband Input 0 (LSB)
BI0
47
leave vacant
48
Clamping Output
CLMP
49
AGC Output
AGC
50
Combined Output for Horizontal Blanking and Key
KEY
2.1. Outline Dimensions
Dimensions in mm
2.2. Pin Connections
Pin Nr.
Signal Name
Symbol
1
RAM Data Input/Output
RDAT
2
RAM Address Output 0 (LSB)
RA0
3
RAM Address Output 1
RA1
4
RAM Address Output 2
RA2
5
RAM Address Output 3
RA3
6
RAM Address Output 4
RA4
7
RAM Read/Write Output
R/WQ
8
Row Address Select Output
RASQ
9
RAM Address Output 5
RA5
10
RAM Address Output 6
RA6
11
RAM Address Output 7 (MSB)
RA7
12
IM Bus Clock Input
IMC
13
IM Bus Ident Input
IMI
14
IM Bus Data Input/Output
IMD
15
Reset Input
RESQ
16
18.432 MHz Output
XTAL1
17
18.432 MHz Input
XTAL2
18
Output Disable Input
ODI
5
DMA 2271, DMA 2280, DMA 2281
Central Control unit. The data transferred via the IM bus
are listed in tables 4–1 to 4–4.
51
Combined Output for Horizontal and Vertical Blanking
CBL
52
Data Burst Window Output
DBW
53
Composite Sync Output
CSYNC
54
Test Input/Output
T0
55
Packet Data Output
PDAT
56
Descrambled Packet Data Input
DPDAT
57
Teletext Sync Output
TSYNC
58
Burst Sync Output
BSYNC
59
Burst Data Input/Output
BDAT
60
Burst Clock Output
BCLK
61
Ground
GND
62
Main Clock Input
MCLK
63
Supply Voltage
VSUP
Pin 20 – leave vacant
64
Sound Bus Ident Output
SBI
65
Audio Clock Output
ACLK
66
Sound Bus Data Output
SBD
67
Sound Bus Clock Output
SBC
Pins 21 to 24 and 27 to 30 – Chroma Outputs C7 to C0
(Fig. 2–8)
Via these pins, the DMA 2271, DMA 2280, and DMA
2281 deliver the digital chrominance signal (R–Y, B–Y)
in multiplexed operation to the VCU 2133 Video Codec
Unit, where it is converted to an analog signal.
68
Column Address Select Output
CASQ
2.3. Pin Descriptions
Pin 1 – RAM Data Input/Output RDAT (Fig. 2–7)
serves as an output for writing data into the external
RAM and as an input for reading data from the external
RAM.
Pins 2 to 6 and 9 to 11 – RAM Address Outputs RA0 to
RA7 (Fig. 2–10)
These pins are used for addressing the external RAM.
Pin 7 – RAM Read/Write Output R/WQ (Fig. 2–10)
By means of this output the external RAM is switched to
read or write mode.
Pin 8 – Row Address Select Output RASQ (Fig. 2–10)
This pin supplies the Row Address Select signal to the
external RAM.
Pin 15 – Reset Input RESQ (Fig. 2–5)
Pin 15 is used for hardware reset. Reset is actuated at
Low level, at High level the DMA 2271, DMA 2280, and
DMA 2281 are ready for operation.
Pins 16 and 17 – XTAL 1 Output and XTAL 2 Input (Fig.
2–11)
These oscillator pins are used to connect an 18.432
MHz crystal, which determines the ACLK audio clock
signal supplied by pin 65. Alternatively, an 18.432 MHz
clock may be fed to pin 17.
Pin 18 – Output Disable Input ODI
This input serves for fast switchover of the luma and
chroma outputs (L0 to L7 and C0 to C7) to high impedance, which is required if the TV receiver is equipped
with Picture–in–picture. Low means outputs active, High
means outputs are disabled.
Pin 19 – leave vacant
Pin 25 – PLL Tuning Data Output PLLD (Fig. 2–8)
This pin supplies the 12–bit data word containing the
PLL tuning information from the PLL filter of the DMA
2271, DMA 2280, and DMA 2281. This information is
needed by the voltage controlled oscillator (VCO) contained on the MCU 2600 Clock Generator IC and closes
the PLL which determines the main clock signal.
Pin 26 – PLL Tuning Clock Output PLLC (Fig. 2–8)
This pin supplies the data clock signal needed for the serial data transfer of the 12–bit PLL tuning information.
Pins 31 to 38 – Luma Outputs L0 to L7 (Fig. 2–8)
Via these pins, the DMA 2271, DMA 2280 and DMA
2281 deliver the digital luminance signal to the VCU
2133 Video Codec Unit, where it is converted to an analog signal.
Pins 39 to 46 – Baseband Input BI7 to BI0 (Fig. 2–3)
Via these inputs, the DMA 2271, DMA 2280, and DMA
2281 receive the digitized baseband signal from the
VCU 2133 Video Codec.
Pin 47 – leave vacant
Pins 12 to 14 – IM Bus Connection IMC, IMI,IMD (Figs.
2–2 and 2–6)
These pins connect the DMA 2271, DMA 2280 and DMA
2281 to the IM bus. Via the IM bus the DMA 2271, DMA
2280 and DMA 2281 communicate with the CCU 3000
6
Pin 48 – Clamping Output CLMP (Fig. 2–9)
This pin supplies a PDM (Pulse Density Modulated) signal for clamping the analog baseband signal at the input
of the analog to digital converter.
DMA 2271, DMA 2280, DMA 2281
Pin 49 – AGC Output AGC (Fig. 2–9)
This tristate–controlled output allows automatic gain
control (AGC) with a three–level signal. High level
means that the input level of the baseband signal is too
low, low level means that the input level of the baseband
signal is too high. In the high impedance state the level
of the baseband signal is in the proper range.
Pin 50 – Combined Output for Horizontal Blanking and
Color KEY (Fig. 2–9)
This output is a tristate–controlled output. In conjunction
with the input load represented by the VCU 2133 Video
codec, the three level blanking and key is produced.
High level means active line, high impedance state
means horizontal blank and low level means color key.
Pin 51 – Combined Output for Horizontal Blanking and
Vertical Blanking CBL (Fig. 2–9)
In conjunction with the input load represented by the
VCU 2133 Video Codec, the three level combined blanking pulse is produced. High level means active line, high
impedance means horizontal blanking and low level
means vertical blanking.
Pin 52 – Data Burst Window DBW (Fig. 2–9)
This output supplies the data burst window signal which
can be used to switch an external de–emphasis network. This signal is active high in line 625 and during the
data burst in each line.
Pin 53 – Composite Sync Output CSYNC (Fig. 2–8)
This output supplies a composite synchronization signal
as it may be used by the DPU 25xx Deflection Processor
or by other units which need a composite synchronization signal which is not contained in the MAC baseband
signal.
Pin 54 – Test Input/Output T0 (Fig. 2–8)
This pin is used for testing the DMA 2271, DMA 2280,
and DMA 2281 during production.
Pin 55 – Packet Data Output PDAT (Fig. 2–10)
PDAT is used to put out each received packet, de–interleaved, with Golay corrected header and with error–corrected BT Byte. This pin used to connect the DMA 2275,
DMA 2285 or DMA 2286 Descrambler IC.
Pin 56 – Descrambled Packet Data Input DPDAT (Fig.
2–2)
This pin is used in conjunction with PDAT, if conditional
access signals must be descrambled, DPDAT receives
the descrambled packet data from the DMA 2275, DMA
2285 or DMA 2286 Descrambler IC.
Pin 57 – Teletext Sync Output TSYNC (Fig. 2–9)
This pin supplies a signal which marks the part of the VBI
lines containing Teletext data.
Pin 58 – Burst Sync Output BSYNC (Fig. 2–4)
This connection supplies a synchronization signal for
the Burst Data Output. The Sync Pulse marks the Line
Synchronization Word LWS of each, and the Clock Run
In CRI and Frame Sync Word FSW in line 625.
Pin 59 – Burst Data Output BDAT (Fig. 2–4)
This output supplies the recovered an decoded duobinary data contained in a MAC signal. This signal may serve
as an input signal for the TPU 27xx Teletext Processor
or the DMA 2275, DMA 2285, DMA 2286 MAC Descrambler processor or for other purposes.
Pin 60 – Burst Clock Output BCLK (Fig. 2–9)
This pin supplies the data clock signal required for the
serial data transfer of the Burst Data signal. The frequency of this signal is equal MCLK or MCLK/2 controlled by parameter Data Rate Select DRS via IM Bus.
Pin 61 – Ground GND
Pin 62 – Main Clock Input MCLK (Fig. 2–4)
By means of this input, the DMA 2271, DMA 2280 and
DMA 2281 receive the required main clock signal from
the MCU 2600 Clock Generator IC.
Pin 63 – Supply VSUP
Pin 64, 66, and 67 – Sound Bus Ident SBI (Fig. 2–9)
Data SBD and Clock SBC (Fig. 2–8)
These pins supply the Clock, Data and Ident signals to
the AMU 2481 Mixing Unit via the serial three–line
Sound Bus.
Pin 65 – Audio Clock Output ACLK (Fig. NO TAG)
This pin supplies the ACLK Audio Clock signal for the
AMU 2481.
Pin 68 – Column Address Select CASQ (Fig. 2–10)
This pin supplies the Column Address Select signal for
the external RAM.
7
DMA 2271, DMA 2280, DMA 2281
2.4. Pin Circuits
VSUP
P
The following figures schematically show the circuitry at
the various pins. The integrated protection structures
are not shown. The letter “P” means P–channel, the letter “N” N–channel.
N
N
GND
Fig. 2–6:
Input/Output Pin 14
VSUP
P
VSUP
Fig. 2–2:
Input Pins 12, 13, 18 and
56
N
GND
P
P
N
N
GND
Fig. 2–7:
Input/Output Pin 1
VSUP
VSUP
P
P
N
N
BIAS
GND
Fig. 2–3:
Input Pins 39 to 46
N
GND
VSUP
Fig. 2–8:
Output Pins 21 to 38, 48,
52 to 54, 66 and 67
VSUP
P
P
N
P
N
GND
Fig. 2–4:
Input Pin 62
GND
Fig. 2–9:
Output Pins 48 to 52, 57
to 60 and 64
VSUP
VSUP
P
N
N
P
P
N
N
P
GND
8
Fig. 2–5:
Input Pin 15
N
GND
Fig. 2–10:
Output Pins 2 to 11, 55
and 68
DMA 2271, DMA 2280, DMA 2281
VSUP
VSUP
P
16
N
P
0.5M
17
N
f ECLK
N
P
GND
Fig. 2–12:
Output Pin 65
GND
Fig. 2–11:
Crystal Oscillator Pins 16 and 17
2.5. Electrical Characteristics
All voltages are referred to ground.
2.5.1. Absolute Maximum Ratings
Symbol
Parameter
Pin No.
Min.
Max.
Unit
TA
Ambient Operating Temperature
–
0
65
°C
TS
Storage Temperature
–
–40
+25
°C
VSUP
Supply Voltage
19, 47, 63
–
6
V
VI
Input Voltage, all Inputs
–
–0.3 V
VSUP
–
VO
Output Voltage, all Outputs
–
–0.3 V
VSUP
–
IO
Output Current, all Outputs
–
–10
+10
mA
2.5.2. Recommended Operating Conditions at TA = 0 to 65 °C, fΦM = 20.25 MHz
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
VSUP
Supply Voltage
19, 47, 63
4.75
5.0
5.25
V
VΦMIDC
ΦM Clock Input D.C. Voltage
62
1.5
–
3.5
V
VΦMIAC
ΦM Clock Input
A.C. Voltage (p–p)
0.8
–
2.5
V
tΦMIH
tΦMIL
ΦM Clock Input High/Low
Ratio
0.9
1.0
1.1
–
tΦMIHL
ΦM Clock Input High to Low
Transition Time
–
–
0.15
fΦM
–
VREIL
Reset Input Low Voltage
–
–
0.8
V
VREIH
Reset Input High Voltage
2.4
–
–
V
tREIL
Reset Input Low Time
2
–
–
µs
VVIL
Video Input Low Voltage
–
–
2.2
V
VVIH
Video Input High Voltage
2.8
–
–
V
15
39 to 46
9
DMA 2271, DMA 2280, DMA 2281
Recommended Operating Conditions, continued
10
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
VΦVIH
Video Input Hold Time after
ΦM Clock Input
39 to 46,
62
14
–
–
ns
VVISΦ
Video Input Setup Time before ΦM Clock Input
4
–
–
ns
VODIL
Outputs Disable Inputs
Low Voltage
–
–
0.8
V
VODIH
Outputs Disable Inputs
High Voltage
2.4
–
–
V
VDSIL
Descrambled Data Input
Low Voltage
–
–
0.8
V
VDSIH
Descrambled Data Input
High Voltage
2.4
–
–
V
VΦAL
ΦA Clock Input Low Voltage
–
–
0.8
V
VΦAH
ΦA Clock Input High Voltage
VSUP
–0.8V
–
–
–
tΦAH
tΦAL
ΦA Clock Input
High/Low Ratio
0.9
1.0
1.1
–
tΦAHL
ΦA Clock Input High to Low
Transition Time
–
–
0.15
fΦA
–
tΦALH
ΦA Clock Input Low to High
Transition Time
–
–
0.15
fΦA
–
fΦA
ΦA Clock Input Frequency
–
18.432
–
MHz
VIMIL
IM Bus Input Low Voltage
–
–
0.8
V
VIMIH
IM Bus Input High Voltage
2.4
–
–
V
fΦI
ΦI IM Bus Clock Frequency
0.05
–
1000
kHz
tIM1
ΦI Clock Input Delay Time
after IM Bus Ident Input
0
–
–
–
tIM2
ΦI Clock Input
Low Pulse Time
3.0
–
–
µs
tIM3
ΦI Clock Input
High Pulse Time
3.0
–
–
µs
tIM4
ΦI Clock Input Setup Time
before Ident Input High
0
–
–
–
tIM5
ΦI Clock Input Hold Time
after Ident Input High
1.5
–
–
µs
tIM6
ΦI Clock Input Setup Time
before Ident End–Pulse
Input
6.0
–
–
µs
18
56
17
12 to 14
DMA 2271, DMA 2280, DMA 2281
Recommended Operating Conditions, continued
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
tIM7
IM Bus Data Input Delay
Time after ΦI Clock Input
12 to 14
0
–
–
–
tIM8
IM Bus Data Input Setup
Time before ΦI Clock Input
0
–
–
–
tIM9
IM Bus Data Input Hold Time
after ΦI Clock Input
0
–
–
–
tIM10
IM Bus Ident End–Pulse
Low Time
3.0
–
–
µs
2.5.3. Recommended Crystal Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
TA
Ambient Operating Temperature
–20
–
+85
°C
fp
Parallel Resonance Frequency
–
18.432*)
–
MHz
∆fp
fp
Accuracy of Adjustment
–
–
±40
ppm
∆fp
fp
Frequency Deviation versus Temperature
–
–
±40
ppm
Rr
Series Resistance
–
–
50
Ω
C0
Shunt Capacitance
5.5
–
7.5
pF
C1
Motional Capacitance
15
–
20
fF
P
Rated Drive Level
–
0.02
–
mW
fp
fH
Spurious Frequency Attenuation
20
–
–
dB
*) at CL = 10 pF. This frequency applies for a certain application. For other applications, an appropriate frequency must
be chosen.
11
DMA 2271, DMA 2280, DMA 2281
2.5.4. Characteristics at TA = 0 to 65 °C, VSUP = 4.75 to 5.25 V, fΦM = 20.25 MHz
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
ISUP
Supply Current
63
–
100
130
mA
VΦAOL
ΦA Audio Clock Output
Low Voltage
65
–
–
2.0
V
IΦAO = 0.5 mA
VΦAOH
ΦA Audio Clock Output
High Voltage
3.0
–
–
V
–IΦAO = 0.5 m A
tΦAHL
ΦA Audio Clock Output
High to Low Transition Time
–
–
10
ns
fΦA
ΦA Audio Clock Output
Frequency
–
18.432
–
MHz
VLCOL
Luma/Chroma Output
Low Voltage
–
–
0.3
V
ILCO = 6 mA
ILCOH
Luma/Chroma Output
High Current
–
–
10
µA
VLCO = 5 V
tLCOT
Luma/Chroma Output
Transition Time
–
–
10
ns
tΦLCOH
Luma/Chroma Output Hold
Time after ΦM Clock Input
21 to 24,
27 to 38,
12
–
–
ns
tΦLCOS
Luma/Chroma Output Setup
Time after ΦM Clock Input
62
–
–
30
ns
tLD
Luma Output Delay Time after
–194
–
+839
µs
VPOL
PLL Bus Output Low Voltage
–
–
0.2
V
IPO = 2 mA
IPOH
PLL Bus Output High Current
–
–
10
µA
VPO = 5 V
fΦP
ΦP Clock Frequency
–
fΦM
4
–
–
tΦPOH
tΦPOL
ΦP Clock Output
High/Low Ratio
0.8
1
1.25
–
tPDOSΦ
PLL Data Output Setup
Time before ΦP Clock Output
20
–
–
ns
tΦPDOH
PLL Data Output Hold
Time after ΦP Clock Output
80
–
–
ns
VSOL
S Bus Output Low Voltage
–
–
0.2
V
ISO = 2 mA
ISOH
S Bus Output High Current
–
–
10
µA
VSO = 5 V
tSOT
S Bus Output Transition Time
–
–
10
ns
fΦS
ΦS S Clock Output Frequency
–
fΦA
4
–
–
tS2
tS1
ΦS S Clock Output
High/Low Ratio
0.9
1
1.1
–
tS3
ΦS S Clock Output Setup Time
before Ident End–Pulse Output
160
220
–
ns
12
21 to 24,
27 to 38
25, 26
26
25, 26
64, 66, 67
67
64, 67
Test Conditions
DMA 2271, DMA 2280, DMA 2281
Characteristics, continued
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
tS4
S Bus Data Output Setup Time
before ΦS S Clock Output
66, 67
100
–
–
ns
tS5
S Bus Data Output Hold Time
after ΦS S Clock Output
100
–
–
ns
tS6
S Bus Ident End–Pulse
Output Low Time
64
300
400
–
ns
VBOL
Burst Bus Output Low Voltage
58 to 60
–
–
0.4
V
IDMO = 1.6 mA
VBOH
Burst Bus Output High Voltage
2.8
–
–
V
–IDMO = 0.1 mA
tBT
Burst Bus Output
Transition Time
–
–
10
ns
fΦB
ΦB Burst Bus Clock Frequency
–
–
tB3
tB2
ΦB Clock Output
High/Low Ratio
tB1
ΦB Clock Output Delay Time
after Ident Output
tB4
Ident Output Delay Time after
ΦB Clock
tB5
Burst Bus Data Output Setup
Time before ΦD Clock Output
tB6
Burst Bus Data Output Hold
Time after ΦB Clock Output
VIMOL
IM Bus Data Output Low Voltage
IIMOH
IM Bus Data Output
High Current
t4
IM Bus Data Output Setup Time
before ΦI Clock Input High
t5
IM Bus Data Output Hold Time
after ΦI Clock Input Fall
VCLOL
Clamping Output Low Voltage
VCLOH
Clamping Output High Voltage
VAGCOL
AGC Output Low Voltage
IAGCOZ
AGC Output High–Impedance
Current
VAGCOH
AGC Output High Voltage
tAGCO
AGC Output Pulse Duration
–
tSAGCO
AGC Output Pulse Start Time
VHBCKOL
Combined Horizontal Blanking
& Color Key Output Low Voltage
IHBCKOZ
Combined Horizontal Blanking
and Color Key Output High–Impedance Current
60
58, 60
59, 60
14
14, 12
48
49
–
0.9
1
1.1
–
–
0
–
–
–
0
–
–
–
50
–
ns
–
0
–
–
–
–
0.3
V
IIMO = 6 mA
–
–
10
µA
VIMO = 5 V
0
–
–
–
0
–
–
–
–
–
0.2
V
ICLO = 2 mA
–
–
V
–ICLO = 1 mA
–
–
0.4
V
IAGCO = 6 mA
–10
–
+10
µA
VAGC = 0 to 5 V
–
–
V
–IAGC = 1 mA
40
–
ms
– line No. 624
–
–
–
–
0.4
V
IHBCKO = 6 mA
–10
–
+10
µA
VHBCKO = 0 to 5 V
VSUP –0.5
50
fΦM or
2 fΦM
Test Conditions
VSUP –0.5
13
DMA 2271, DMA 2280, DMA 2281
Characteristics, continued
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
Test Conditions
VHBCKOH
Combined Horizontal Blanking &
Color Key Output High Voltage
50
4.0
–
–
V
–IHBCKO = 0.1 mA
tHB2
Horizontal Blanking Output Time
–
10.5
0
µs
tCK2
Color Key High Z
Output Low Time
–
2.27
–
µs
tCK1
Color Key Output Delay Time
after Horizontal Blanking Output
–
5.5
–
µs
tHB1
Horizontal Blanking Output
Lead Time before
Chroma Output High
50,
21 to 24,
27 to 30
5.8
–
18.4
µs
VHVBOL
Combined Horizontal and Vertical Blanking Output Low Voltage
51
–
–
0.4
V
IHVBO = 6 mA
IHVBOZ
Combined Horizontal and
Vertical Blanking Output
High–Impedance Current
–10
–
+10
µA
VHVBO = 0 to 5 V
VHVBOH
Combined Horizontal & Vertical
Blanking Output High Voltage
4.0
–
–
V
–IHVBO = 0.1 mA
tVB1
Vertical Blanking Output Time
–
0.64
–
ms
tHB2
Horizontal Blanking Output Time
–
10.5
–
µs
VHBOL
Horizontal Blanking Output
Low Voltage
–
–
0.4
V
IHBO = 1.6 mA
VHBOH
Horizontal Blanking Output
High Voltage
2.4
–
–
V
–IHBO = 0.1 mA
tHB2
Horizontal Blanking Output
Low Time
–
12
–
µs
VCSOL
Composite Sync Output
Low Voltage
–
–
0.4
V
ICSO = 1.6 mA
VCSOH
Composite Sync Output
High Voltage
2.8
–
–
V
–ICSO = 0.1 mA
tCS2
Composite Sync Output
Low Time 1
–
4.8
–
µs
tCS3
Composite Sync Output
Low Time 2
–
2.4
–
µs
tVB2
Composite Sync Output Delay
Time after Vertical Blanking
Output
51, 53
–
1.5
–
µs
tCSOLC
Composite Sync Output Lead
Time before Chroma Output
53,
21 to 24,
27 to 30
4.2
–
16.8
µs
VPDOL
Packet Data Output Low Voltage
55
–
–
0.4
V
IPDO = 1.6 mA
VPDOH
Packet Data Output
High Voltage
2.4
–
–
V
–IPDO = 0.1 mA
VTSOL
Teletext Sync Output
Low Voltage
–
–
0.4
V
ITSO = 1.6 mA
VTSOH
Teletext Sync Output
High Voltage
2.4
–
–
V
–ITSO = 0.1 mA
14
52
53
57
DMA 2271, DMA 2280, DMA 2281
2.5.5. DRAM Interface Characteristics
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
VDIL
RAM Data Input Low Voltage
1
–
–
0.8
V
VDIH
RAM Data High Voltage
2.0
–
–
V
tDIS
RAM Data Input Setup Time
before CAS Output High
–
–
75
ns
tDIH
RAM Data Input Hold Time
after CAS Output High
0
–
33
ns
VDOL
RAM Data Output Low Voltage
–
–
0.4
V
IDO = 1.6 mA
VDOH
RAM Data Output High Voltage
2.4
–
–
V
–IDO = 0.1 mA
tDT
RAM Data Op. Transition Time
3
–
50
ns
tDHR
RAM Data Hold Time after
RAS Low
140
–
–
ns
tDS
RAM Data Setup Time before
CAS Low
20
–
–
ns
tDH
RAM Data Output Hold Time
after CAS Output Low
1, 68
80
–
–
ns
VAOL
RAM Address Output
Low Voltage
2 to 6,
9 to 11
–
–
0.4
V
IAO = 1.6 mA
VAOH
RAM Address Output
High Voltage
2.4
–
–
V
–IAO = 0.1 mA
tAT
RAM Address Output
Transition Time
3
–
50
ns
tRAH
Row Address Output Hold Time
after RAS Output Low
22
–
–
ns
tASR
Row Address Output Setup
Time before RAS Output Low
30
–
–
ns
tAR
Column Address Output Hold
Time after RAS Output Low
125
–
–
ns
tCAH
Column Address Output Hold
Time after CAS Output
70
–
–
ns
tASC
Column Address Output Setup
Time before CAS Output
10
–
–
ns
VRASOL
RAS Output Low Voltage
–
–
0.4
V
IRASO = 1.6 mA
VRASOH
RAS Output High Voltage
2.4
–
–
V
–IRASO = 0.1 mA
tRAST
RAS Output Transition Time
3
–
50
ns
tRAS
RAS Low Pulsewidth
125
–
3000
ns
tRP
RAS Output Precharge Time
130
–
–
ns
tRSH
RAS Output Hold Time after
CAS Output Low
8, 68
110
–
–
ns
VCASOL
CAS Output Low Voltage
68
–
–
0.4
V
ICASO = 1.6 mA
VCASOH
CAS Output High Voltage
2.4
–
–
V
–ICASO = 0.1 mA
tPC
Page Mode Cycle Time
170
–
–
ns
1, 68
1
1, 8, 68
2 to 6, 9 to
11, 8
2 to 6, 9 to
11, 68
8
Test Conditions
15
DMA 2271, DMA 2280, DMA 2281
DRAM Interface Characteristics, continued
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
tCAST
CAS Output Transition Time
68
3
–
50
ns
tCP
CAS Output Precharge Time
70
–
–
ns
tCAS
CAS Low Pulsewidth
95
–
150
ns
tRCD
CAS Output Delay Time after
RAS Output
45
–
–
ns
tCSH
CAS Output Hold Time after
RAS Output
170
–
–
ns
tCRP
CAS Output Precharge Time
before RAS Output
150
–
–
ns
VWOL
WRITE Output Low Voltage
–
–
0.4
V
IWO = 1.6 mA
VWOH
WRITE Output High Voltage
2.4
–
–
V
–IWO = 0.1 mA
tWT
WRITE Output Transition Time
3
–
50
ns
tCWL
WRITE Low before CAS High
180
–
–
ns
tWCH
WRITE Command Hold Time
after CAS Low
80
–
–
ns
tRCH
READ Command Hold Time
after CAS High
50
–
–
ns
tRRH
READ Command Hold Time
after RAS High
20
–
–
ns
16
68, 8
7
7, 68
7, 8
Test Conditions
DMA 2271, DMA 2280, DMA 2281
2.5.6. Waveforms
H
Ident
L
H
Clock
1
2
3
4
5
6
7
8
9
10
11
12
13
16
or 24
L
H
Data
Address
LSB
MSB LSB
Data
MSB
L
A
B
Section A
C
Section B
Section C
tIM10
H
Ident
L
tIM1
tIM3
tIM4
tIM6
tIM5
tIM2
H
Clock
L
tIM7
H
tIM8
tIM9
Address LSB
Data
Address MSB
Data MSB
L
Fig. 2–13: IM bus waveforms
H
S–Ident
L
H
S–Clock
64 Clock Cycles
L
H
S–Data
16 Bit Sound 1
16 Bit Sound 2
16 Bit Sound 3
16 Bit Sound 4
L
A
B
Section A
Section B
tS6
H
S–Ident
L
tS1
tS2
tS3
H
S–Clock
L
tS4
H
S–Data
tS5
LSB of Sound 1
MSB of Sound 4
L
Fig. 2–14: S bus waveforms
17
DMA 2271, DMA 2280, DMA 2281
H
Sync
Line 1–624
Line 625
L
H
Clock
L
H
Data
644 645 646 647 648 1
2
3
4
5
6
7
8
9
10
11
99 100 101 102 103 104 105
L
A
B
C
Section A
Sections B and C
H
Sync
L
tB1
tB3
tB4
tB2
H
Clock
L
tB5
tB6
H
Data
L
Fig. 2–15: Burst bus waveforms
tCWL
WE
VOH
VOL
tAR
tRRH
tRAS
RAS
VOH
VOL
tCSH
tPC
tWCH
tRP
tRSH
tRCD
CAS
tCP
tRCH
tASR
DRAM VOH
ADDR. VOL
tRAH
ROW ADDR.
tASC
tCAH
tCRP
COLUMN ADDR. 0
tDS
DOUT
tCAS
VOH
VOL
VOH
VOL
COLUMN ADDRESS 1
COLUMN ADDRESS 14
ROW ADDR.
tDH
VALID DATA
VALID DATA
VALID DATA
tDHR
DIN
VOH
VOL
Fig. 2–16: DRAM waveform
18
VALID
DATA
tDIS
tDIH
VALID DATA
VALID DATA
DMA 2271, DMA 2280, DMA 2281
First Frame
Composite Synchronization
Pin 53
Fig. 2–18a
Vertical Blanking
internal
tVB1
Horizontal Blanking
Pin 52
Combined Horizontal
and Vertical Blanking
Pin 51
Second Frame
Composite Synchronization
Pin 53
Fig. 2–18b
Vertical Blanking
internal
tVB1
Horizontal Blanking
Pin 52
Combined Horizontal
and Vertical Blanking
Pin 51
Fig. 2–17: Synchronization signals
32 µs
Composite Synchronization
Pin 53
tC52
a
tC53
tVB2
Vertical Blanking
internal
64 µs
Composite Synchronization
Pin 53
tC52
b
tC53
tVB2
Vertical Blanking
internal
Fig. 2–18: Details of Fig. 2–17
19
DMA 2271, DMA 2280, DMA 2281
Chroma out
Pins 21–24, 27–30
tLD
Luma out
Pins
31–38
tC51
Composite
Synchronization out
Pin 53
tC52
tHB1
Horizontal Blank out
Pin 52
tHB2
tCK1
Color Key
internal
tCK2
Combined Horizontal
Blanking and Color Key
Pin 50
Fig. 2–19: Timing of video and sync signals
2.5.7. Frequency Responses
5
5
0
0
I
–5
–5
IV
II
–10
III
–10
III
II
I
VIII
dB –15
dB –15
IV
VI
–20
–20
–25
–25
V
–30
–30
VI
–35
–35
VII
–40
–40
0
1
2
3
4
5
6
7
8
0
1
f (MHz)
2
3
f (MHz)
Fig. 2–20: Luminance channel frequency response
Fig. 2–21: Chrominance channel frequency response
Table 2–1: Selection of the luma filter response
Table 2–2: Selection of the chroma filter response
20
LFI
Curve No.
CFI
Curve No.
0
1
2
3
I
II
III
IV
0
1
2
3
4
5
6
7
I
II
III
IV
V
VI
VII
VIII
4
DMA 2271, DMA 2280, DMA 2281
3. Functional Description
3.1.3. The Phase Comparator and the PLL Filter
The DMA 2271, DMA 2280 and DMA 2281 process the
digitized D2–MAC video signal supplied by the VCU
2133 or by the UVC 3130 in the various circuit parts
shown in Fig. 1–4. The resulting digital luminance and
chrominance signals are then reconverted to analog signals in the VCU or HDAA. The resulting digital audio signals are processed in the AMU 2481 Audio Mixer which
provides filtering of the medium–quality channels and allows mixing of the four sound channels. The AMU’s digital output signals are reconverted to analog in the ACP
2371 Audio Processor, which additionally carries out
functions like adjustment of volume, bass and treble,
loudness, etc. Remaining digital data as service and
channel information in packet 0 or line 625 can be handled by software via the IM bus or by additional hardware
which uses the serial B–Data interface (B–Data, B–
Clock and B–Sync). Section 1.2. shows how the DMA
2271, DMA 2280 and DMA 2281 can be used together
with other circuits of INTERMETALLS’s DIGIT 2000 digital TV system to realize a multistandard
NTSC/PAL/SECAM/C/D/D2–MAC color TV receiver.
The phase comparator derives the reference signal from
the slopes contained in the data burst of each line. Its
output signal, an 8–bit word which is passed through a
digital lowpass filter, is added to an 8–bit word, VCOA,
which is provided by the CCU for adjustment of the crystal frequency. This digital PLL signal is output via pins 25
and 26 and routed to the MCU 2600 Clock Generator IC
thus closing the PLL, existing between DMA 2271, DMA
2280, and DMA 2281, VCU 2133 Video Codec and MCU
2600 Clock Generator IC. In this way, the main clock signal FM of the system is in phase with the duobinary–
coded signal.
To understand the signal processing in the DMA 2271,
DMA 2280, and DMA 2281 it may be useful to distinguish three different function blocks, namely:
– Clock and Data Recovery
– Video Processing
– Sound/Data Processing
3.1. Clock and Data Recovery
3.1.1. The Code Converter
This circuit converts the digitized C/D/D2–MAC baseband signal, delivered by the VCU 2133 in a parallel
Gray code, into a simple binary–coded signal. The function of the circuit is controlled by the CCU 3000 via the
IM bus (see section 4.2.).
3.1.2. The Video Clamping Circuit and the AGC Circuit
The video clamping circuit measures the DC voltage level of the clamp period and, by means of the pulse density
modulated signal from pin 48, sets the DC level of the
clamp period to a constant 5.5 V. The white and the black
levels in line 624 are measured for automatic gain control (AGC pin 49) and the two values are fed to the IM
bus interface which organizes the data communication
with the CCU.
To adjust the crystal frequency, it is possible to render inoperative the PLL by setting PLLO bit 4 in address 201
(Table 4–1). The VCO in the MCU is then free–running
and the center frequency can be aligned by varying the
data word VCOA (bits 0 to 7) in the IM bus address 14.
3.1.4. The Data Slicer and the Synchronization Circuit
The digitized C/D/D2–MAC baseband signal is filtered
by a 5 MHz lowpass filter before being routed to the data
slicer. The output of the slicer is connected to pin 59 (B–
Data). In phase with the continuous bit stream of 20.25
or 10.125 MBit/s, a clock signal (B–Clock), a synchronization signal (B–Sync) and a signal for Teletext information (TTSYNC) are available at pins 60, 58, and 57 (see
Fig. 2–15).
The vertical synchronization pulse, on–chip, is derived
from a 64–bit correlator which compares the data stream
at the output of the slicer with the fixed Frame Synchronization Word (FSW). Whenever the correlation is equal
to or greater than 61 a frame reset pulse is generated.
Horizontal synchronization is derived by counting. In
phase with the video outputs (L0 to L7, C0 to C7), the
various synchronization and blanking signals are outputs at pins 50 to 53 (Fig. 2–17, 2–18 and 2–18).
3.2. Video Processing
The DMA 2271, DMA 2280, and DMA 2281 process the
C/D/D2–MAC baseband signal, digitized by the VCU or
UVC at a sample frequency of 20.25 MHz. For time expansion, the video samples of each line are stored in an
on–chip RAM and read to at the lower frequencies of
13.5 MHz for the luminance signal and 6.75 MHz for the
color difference signals.
3.2.1. The Luminance Store
AGC (pin 49) = high if WL – BL < 224
AGC (pin 49) = high impedance if 224 ≤ WL – BL ≤ 240
AGC (pin 49) = low if WL – BL > 240
Time expansion of the luminance signal is achieved by
digitizing the analog signal at a clock frequency of 20.25
MHz, storing the Bytes, and reading them at a frequency
of 13.5 MHz. For this, a fast RAM is provided on–chip.
21
DMA 2271, DMA 2280, DMA 2281
3.2.2. The Luminance Interpolating Filter
An interpolation from 13.5 MHz to 20.25 MHz is performed in order to overcome the need for a second system clock of 13.5 MHz and to simplify the reconstruction
filters placed after the D/A conversion (RGB outputs of
the VCU). The interpolation filter has a linear phase and
can be switched to broad or narrow bandwidth by means
of the CCU via the IM bus (bits 10 and 11, address 201).
The different frequency responses are shown in Fig.
2–20 and in Table 2–1.
3.2.3. The Contrast Multiplier
After the luminance interpolating filter is a contrast multiplier. The contrast setting is controlled by the CCU via
the IM bus (bits 10 to 15, address 200), depending on the
user’s instruction. From the contrast multiplier, the digital luminance signal is fed back to the VCU 2133 in the
form of an 8–bit signal. In the VCU, this signal is converted from digital to analog and fed to the RGB matrix.
The setting range of the contrast multiplier comprises 6
bits (64 steps). If the product at the multiplier’s output is
higher than the working range, the largest possible number is output.
NO TAG, Table 2–2) using bits 13 to 15 in address 201.
This filter is used for conversion of the sample rate from
6.75 MHz up to 10.125 MHz.
3.2.7. The Color Saturation Multiplier
The digital color difference signals U and V are routed to
a color saturation multiplier, whose setting is also controlled by the CCU via the IM bus (address 23). The
range of the multiplier comprises 6 bits, with each color
difference signal being set independently.
The PAL matrix in the VCU requires a compensation factor of 0.71. This means that the color saturation factor for
(B – Y) is equal to 0.71 the color saturation factor for
(R – Y). Both factors are calculated in the CCU.
3.2.8. The Color Multiplexer
The color difference signals are transferred back to the
VCU 2133 in multiplex via a 4–line bus. Demultiplexing
takes place in the VCU. The digital signals are then reconverted to analog. Subsequently they are dematrixed
in the RGB matrix together with the Y signal, giving the
RGB signals which drive the output amplifiers of the
VCU 2133 Video Codec.
3.2.4. The Chrominance Store
The chrominance store contains the color information
for 3 lines. It is used for time expansion and line interpolation. The input frequency is 20.25 MHz, the output frequency 6.75 MHz.
The color multiplexer can drive a 4–line bus with an effective sample rate of 5.6025 MHz for each color difference signal or an 8–line bus with a sample rate of 10.125
MHz. This function is controlled by the IM bus (Table
4–1), using bit 6 in address 201.
3.2.5. The Line Interpolating Filter
3.3. Sound/Data Processing
The color difference signals are transmitted within alternate lines as U and V. A “1, 2, 1” post–filter required to
interpolate the color difference information is implemented. The action of the filter is for even lines:
This section begins with a descrambler and de–interleaver. The descrambler uses the same pseudo–random binary sequence (PRBS) generator as is used for
the scrambling process. Its clock rate is 10.125 MHz or
20.25 MHz. The de–interleaver corrects the succession
of the transmitted packet bits which are interleaved in order to minimize the effect of multiple bit errors.
U = Un, V =
Vn–1 + Vn +1
2
and for odd lines:
U = Un–1 + Un +1 , V = Vn
2
Table 3–1: Transmission Order
3.2.6. The Chrominance Interpolating Filter
1
2
95
96
After the line interpolating filter the 8–bit color difference
signals U and V are routed to the chroma interpolating
filter which has linear phase and can be switched to different frequency responses via the IM bus (Fig.
93
94
187
188
22
189
190
...
...
...
281
282
283
284
377
378
375
376
469
470
471
472
...
...
...
563
564
565
566
659
660
657
658
751
(1)
DMA 2271, DMA 2280, DMA 2281
3.3.1. The Golay and PT Byte Decoder
The data format has changed now from data burst format (99 bits) to packet format (751 bits). The header of
each packet contains defined addresses for the different
sound and data services and four bits representing the
sound characteristics. The PT Byte of each packet distinguishes between sound and data packets. After correction of header and PT Byte with the Golay and PT
Byte decoder, this information is used for automatic configuration of the DMA 2271, DMA 2280, and DMA 2281.
In addition, the Golay decoder is used for measuring the
bit error rate of the transmission channel. The bits in error in each packet header are accumulated over one
frame (82 packets). The sum is stored in IM bus register
206 (Table 4–2) and can be read by the CCU which may
control different muting functions.
3.3.2. The Address Comparator
The DMA 2271, DMA 2280, and DMA 2281 D2–MAC
Decoders are able to treat different sound services automatically by decoding the address field of the packet
header. The two continuity bits CI1 and CI0 are used to
link successive packets of the same service in case of
a 120 Byte sound coding service.
rors. The range check uses the highly protected scale
factor bits to check the MSBs of each sample. Its error
correction and detection abilities are shown in Table
3–2.
Erroneous samples, i.e. samples with uncorrectable errors, are concealed by replacement with interpolated adjacent samples. The storage capacity for buffering the
sound samples during processing and for obtaining a
smooth, regular output of sound samples is provided by
an external 64–K DRAM. To ensure the continuity of output sound samples in case of packet loss or packet gain,
the silence information is used and blocks of samples
corresponding to “silence” are repeated or omitted.
3.3.4. The Sound Multiplex
After extension from 14 bits to 16 bits, the sound samples of the four channels are loaded into a 64–bit shift
register and transferred to the AMU 2481 Audio Mixer
via a serial 3–lines S bus. Fig. 2–14 shows the S bus timing.
Table 3–2: Error correction and detection
Protection
Range
Defective
Bits
Error
Correction
Error
Detection
111
1
–
–
–
110
2
X13, X12
–
1
101
3
X13, X12, X11
–
2
3.3.3. The Sound Decoder
011
4
X13 → X10
1
2
The sound decoding section converts all types of selected sound packets into a sequence of 14–bit sound
samples. The medium–quality channels are up–
sampled to the 32 kHz sampling frequency of the high–
quality channels, i.e. every sample of a medium–quality
channel is put out twice, the second time as a zero sample. The second part of the interpolation is performed in
the AMU 2481 Audio Mixer where two oversampling filters are provided. The error correction section uses a
range check and/or Hamming decoder, depending on
the sound coding mode. The Hamming decoder is able
to correct one error per sample and to detect double er-
100
5
X13 → X9
1
3
010
6
X13 → X8
2
3
001
7
X13 → X7
2
4
000
8
X13 → X6
2
4
Among the different coding characteristics all combinations are possible. The user can select up to four sound
channels simultaneously by programming the sound
services via the IM bus (address 203, 194, 195 and 196).
These addresses are compared with the address of
each transmitted sound packet. At correspondence, this
packet is selected and decoded.
Scale
Factor
linear:
companded:
010
6
X9, X8
–
1
001
7
X9, X8, X7
–
2
000
7
X9, X8, X7
–
2
23
DMA 2271, DMA 2280, DMA 2281
3.3.5. The ΦA Audio Clock
The audio clock ΦA for the AMU 2481 Audio Mixer and
the ACP 2371 Audio Processor is also supplied by the
DMA 2271, DMA 2280 and DMA 2281 which generate
this 18.432 MHz clock by means of the crystal connected to pins 16 and 17 and supply it via pin 65. The frequency of 18.432 MHz is an integer multiple of the sound
sampling frequency (32 kHz).
The ΦA audio clock output pin 65 can be switched over
to the normal main clock ΦM if a standard other than C/
D/D2–MAC is received. For this, bit ACS in address 204
of the IM bus is provided (Table 4–1).
The clock frequency ΦS for the serial S bus is also
derived from the audio clock ΦA (pin 65) by dividing by
eight (18.432 MHz: 4 = 4.608 MHz)
3.3.6. The Buffer for Packet 0
One packet address (000H) is reserved for service and
network identification data. A 720–bit (90 Byte) Buffer is
24
implemented on–chip especially for this, and is controlled by the CCU via the IM bus (bits 8 and 9, address
204). The following conditions must be met to ensure
that a received packet is stored in this buffer:
Packet Address
PA = 000H
Packet Type
PT = F8H
Data Group Type TG = selected type in IM bus
register 204
Packet 0 Status
P0 = 0 (see IM bus registers 204
and 206)
The packet 0 buffer can be read sequentially from a
16–bit IM bus register (address 210, Table 4–2). One
complete read cycle takes about 1.5 ms (IM bus frequency = 1 MHz). It is possible to reset and to clear the
buffer via the IM bus in order to repeat the last–read
cycle or to receive the next zero packet. Additionally, the
last 16 bits of the zero packet are used for error checking. This CRC check calculates the 16–bit syndrom vector of the packet concerned and stores it in an IM bus
register. It can then be used by software for error detection.
DMA 2271, DMA 2280, DMA 2281
4. The Three Serial Interfaces
4.1. The S Bus Interface and the S Bus
The S bus has been designed to connect the digital
sound output of the DMA 2271, DMA 2280, and DMA
2281 MAC Decoders or the MSP 2400 NICAM Demodulator/Decoder to audio–processing ICs such as the AMU
2481 Audio Mixer or the ACP 2371 Audio Processor
etc., and to connect these ICs one to the other. The S bus
is a unidirectional, digital bus which transmits the sound
information in one direction only, so that it is not necessary to solve priority problems on the bus.
The S bus consists of the three lines: S–Clock, S–Ident,
and S–Data. The DMA 2271, DMA 2280, and DMA 2281
or the MSP 2400 generates the signals S–Clock and S–
Ident, which control the data transfer to and between the
various processors which follow the DMA 2271, DMA
2280, and DMA 2281 or the MSP 2400. For this, the S–
Clock and S–Ident inputs of all processors in the system
are connected to the S–Clock and S–Ident outputs of the
DMA 2271, DMA 2280, and DMA 2281 or the MSP 2400.
S–Data output of the DMA 2271, DMA 2280, and DMA
2281 or MSP 2400 is connected to the S–Data input of
the next following AMU, the AMU’s S–Data output is
connected to the ACP’s S–Data input and so on.
The sound information is transmitted in frames of 64 bits,
divided into four successive 16–bit samples. Each sample represents one sound channel. The timing of a complete transmission of four samples is shown in Fig. 2–14,
the times are specified under “Recommended Operating Conditions”. The transmission starts with the LSB of
the first sample. The S–Clock signal is used to write the
data into the receiver’s input register. the S–Ident signal
marks the end of one frame of 64 bits and is used as latch
pulse for the input register. The repetition rate of S–Ident
pulses is identical to the sampling rate of the D2–MAC
or NICAM sound signal; thus it is possible to transfer four
sound channels simultaneously.
The S bus interface of the DMA 2271, DMA 2280, and
DMA 2281 mainly consists of an output register, 64–bit
wide. The timing to write bit by bit is supplied by the S–
Clock signal. In the case of an S–Ident pulse, the contents of the output register are written to the S–Data output.
The IM bus consists of three lines for the signals Ident
(ID), Clock (CL) and Data (D). The clock frequency
range is 50 Hz to 1 MHz. Ident and clock are unidirectional from the CCU to the slave ICs, Data is bidirectional. bidirectionality is achieved by using open–drain outputs. The 2.5 ... 1 kOhm pull–up resistor common to all
outputs must be connected externally.
The timing of a complete IM Bus transaction is shown in
Fig. 5–2. In the non–operative state the signals of all
three bus lines are High. To start a transaction the CCU
sets the ID signal to Low level, indicating an address
transmission, and sets the CL signal to Low level, as well
as to switch the first bit on the Data line. Then eight address bits are transmitted, beginning with the LSB. Data
takeover in the slave ICs occurs at the positive edge of
the clock signal. At the end of the address byte the ID signal switches to High, initiating the address comparison
in the slave circuits. In the addressed slave, the IM bus
interface switches over to Data read or write, because
these functions are correlated to the address. Also controlled by the address the CCU now transmits eight or
sixteen clock pulses, and accordingly one or two bytes
of data are written into the addressed IC or read out from
it, beginning with the LSB.
The completion of the bus transaction is signalled by a
short Low state pulse of the ID signal. This initiates the
storing of the transferred data.
For future software compatibility, the CCU must write a
zero into all bits not used at present. Reading undefined
or unused bits, the CCU must adopt “don’t” care behavior.
4.2.2. IM Bus Addresses and Instructions
By means of the IM bus, the DMA 2271, DMA 2280, and
DMA 2281 communicate with the CCU 3000 Central
Control Unit. The DMA 2271, DMA 2280, and DMA 2281
receive the instructions for the user–actuated settings
such as color saturation, contrast, sound channel select,
packet 0 control, etc., and transmits the measured or received values such as bit error rate, signal level, sound
coding mode,packet 0 data, etc. The address numbers
and the associated data for this interaction via the IM bus
are shown in Tables 4–1 to 4–4. In these tables “W”
means data written by the CCU into the DMA, and “R”
means data read by the CCU from the DMA.
4.2. The IM Bus Interface and the IM Bus
4.3. The Burst Bus
4.2.1. The IM Bus
The INTERMETALL Bus (IM Bus for short) was designed to control the DIGIT 2000 ICs by the CCU Central
Control Unit. Via this bus the CCU can write data to the
ICs or read data from them. This means the CCU acts
as a master, whereas all controlled ICs have purely
slave status.
The Burst bus serves for transfer of the digitized
D2–MAC baseband signal, after code conversion, lowpass filtering and slicing as described in sections 3.1.1.
and 3.1.4., to e.g., the TPU 2735 Teletext Processor or
the DMA 2275/DMA 2285/DMA 2286 MAC Descrambler. Timing of the B bus is shown in Fig. 2–15 and under
Recommended Operating Conditions.
25
DMA 2271, DMA 2280, DMA 2281
4.3.1. Control and Status Registers
Note: Not–used bits must be set to zero for control (receive) registers and are don’t care for status (transmit) registers.
Table 4–1: 16–bit DMA control registers, instructions from CCU to DMA
Address
Label
Bit No.
Default
Setting
Typical
Value
Function
14
VCOA
0–7
0
0
VCO adjustment (range –128...+127)
alignment of the 20.25 MHz VCO
14
VCOS
8–10
4
4
VCO select
1 = VCO3 selected
2 = VCO2 selected
4 = VCO1 selected
14
DI1
DI2
DI3
11
14
15
0
0
disable PLL output (pin 25, 26)
if (DI1 . or . DI2 . or DI3) then
PLL output = high impedance
23
SAV
2–7
32
25
saturation V adjust
0: gain = 0
63: gain = 2
23
SAU
10–15
32
18
saturation U adjust
0: gain = 0
63: gain = 2
200
LD
3–7
4
6
luma delay adjust (range 0...30)
resolution: 20.25 MHz clock
200
CTS
8
0
1
luma contrast switch
200
CT
10–15
32
16
luma contrast adjust
0: gain = 0
63: gain = 1 if CTS = 1
63: gain = 2 if CTS = 0
201
DSY
0
1
0
disable sync outputs (pins 50–53, 58–60)
0 = enabled
1 = high impedance
201
DCL
1
0
0
disable clamping output (pin 48)
0 = enabled
1 = high impedance
201
DLC
2
0
0
disable luma/chroma output (pin 21–24, 27–38)
0 = enabled
1 = high impedance
201
NIN
3
0
0
non interlace
0 = interlace on
1 = interlace off
201
PLLO
4
0
0
PLL open
0 = PLL closed
1 = PLL opened
201
STA
5
0
0
stand alone operation
0 = digital insertion
1 = stand alone
201
CMP
6
0
0
chroma output multiplex
0 = 4 x 4 multiplex
1 = 2 x 8 multiplex
26
DMA 2271, DMA 2280, DMA 2281
Table 4–1, continued
Address
Label
Bit No.
Default
Setting
Typical
Value
Function
201
DGC
7
0
0
disable gray code converter input signal (pin 39–45)
0 = gray coded
1 = binary coded
201
L525
8
0
0
525 lines standard select
0 = 625 lines standard selected
1 = 252 lines standard selected
201
LF
10–11
0
0
luma filter selection
201
CF
13–15
0
0
chroma filter selection
202
BD
1–7
64
64
horizontal blank delay adjust (pin 50–52)
resolution: 10.125 MHz clock
202
SD
9–15
64
64
comp. sync delay adjust (pin 53)
resolution: 10.125 MHz clock
203
C1A
0–9
0
128
channel 1 packet address
203
C1E
10
0
1
channel 1 enable
203
C1U
11
0
0
channel 1 mode update
203
C1M
12–15
0
12
channel 1 mode
linear/nicam
hamming/parity protection
high/medium quality
stereo/mono
194
see register 203
channel 2
195
see register 203
channel 3
196
see register 203
channel 4
197
SFS
0–10
7
7
subframe select
SFS = sample number of the first bit
in the selected subframe
examples:
DRS = 1, first subframe
SFS = 7
DRS = 1, second subframe SFS = 106
DRS = 0, first subframe
SFS = 14
197
CD
13
0
0
chip definition
0 = DMA 2280
1 = DMA 2285
197
AUM
14
0
0
auto mode
0 = auto mode off
1 = sound coding in packet header
197
DRS
15
0
1
data rate select
0 = 10.125 Mbits/s
1 = 20.25 Mbits/s
D2–MAC
C/D–MAC
198
EDC
0–3
0
0
energy dispersal compensation (–8...+7)
198
CLG
4–5
0
2
clamping loop gain
198
CS
14–15
0
0
chip select
0 = IM bus of DMA 2280 active
1 = IM bus of DMA 2285 active
27
DMA 2271, DMA 2280, DMA 2281
Table 4–1, continued
Address
Label
Bit No.
Default
Setting
Typical
Value
Function
199
PLLS
0
0
0
PLL select
0 = D/D2 MAC PLL
1 = CMAC PLL
199
ENF2
1
0
0
enable filter 2
0 for C/D MAC
1 for D2 MAC
199
SLS
2–3
0
1
slicer select
0 for D2–MAC
1 for D–MAC
2 for C–MAC
199
PLLG
4–5
0
2
PLL gain
0 = maximal gain
3 = minimal gain
199
FCD
6
0
0
full channel data
0: DBW is gated (pin 52)
1: DBW is active all the time
199
BPH
7
0
0
burst phase
0 = with DMA 2285
1 = only DMA 2280
199
SLL
8–15
0
40
0
slice level (range –128...+127)
for D/D2–MAC
for C–MAC
204
SBE
0–3
0
15
S bus enable
channel 1 enable
channel 2 enable
channel 3 enable
channel 4 enable
204
DGT
4–7
0
0
data group type selection
204
POR
8
0
0
packet 0 reset
1: select first byte in packet 0 buffer
(first byte = data group type DGT)
204
POC
9
0
0
packet 0 clear
1: enable packet 0 buffer to store
next packet 0
204
DSB
10
1
0
disable S bus outputs (pins 64, 66, 67)
0 = enabled
1 = high impedance
204
ACS
11
0
1
audio clock switch (pin 65)
0: audio clock = main clock
1: audio clock = 18.432 MHz
204
ACF
12
1
0
audio clock free running
0 = audio clock locked to main clock
1 = audio clock free running
28
DMA 2271, DMA 2280, DMA 2281
Table 4–1, continued
Address
Label
Bit No.
Default
Setting
Typical
Value
Function
205
T0
0
0
0
for test only
205
T1
1
0
0
for test only
205
T2
2
0
0
for test only
205
T3
3
0
0
for test only
205
T4
4
0
0
for test only
205
T5
5
0
0
for test only
205
T6
6
0
0
enable PDAT input
205
T7
7
0
0
for test only
205
T8
8
0
0
disable error concealment
205
T9
9
0
0
for test only
205
T10
10
0
0
enable BDAT input
205
T11
11
0
0
for test only
205
T12
12
0
0
for test only
205
T13
13
0
0
disable luma/chroma interpolation filters
205
T14
14
0
0
for test only
205
T15
15
0
0
for test only
29
DMA 2271, DMA 2280, DMA 2281
Table 4–2: 16–bit DMA status registers, information from DMA to CCU
Address
Label
Bit No.
Function
206
BER
0–7
bit error rate
number of erroneous bits detected by the golay decoder within the 82 packet
headers of one frame
206
VER
8–9
version
0: C/D/D2–MAC Decoder
1: D2–MAC Decoder
2: D–MAC Decoder
3: C/D2–MAC Decoder
206
C1S
10
status of sound signal selected by C1A
0: sound signal is inactive or interrupted
1: sound signal is present
206
C2S
11
status of sound signal selected by C2A
0: sound signal is inactive or interrupted
1: sound signal is present
206
C3S
12
status of sound signal selected by C3A
0: sound signal is inactive or interrupted
1: sound signal is present
206
C4S
13
status of sound signal selected by C4A
0: sound signal is inactive or interrupted
1: sound signal is present
206
P0S
14
status of packet 0 buffer
0: packet 0 selected by DGT not received
1: packet 0 received
206
SYNC
15
status of frame sync word detector
0: frame sync word not detected within 8 frames
1: frame sync word detected
207
WL
0–7
white level measured in line 624 (typical value = 240)
207
BL
8–15
black level measured in line 624 (typical value = 16)
208
C1L
0–3
coding law of sound signal selected by C1A
208
C2L
4–7
coding law of sound signal selected by C2A
208
C3L
8–11
coding law of sound signal selected by C3A
208
C4L
12–15
coding law of sound signal selected by C4A
L = 0: companded law
1: linear law
H = 0: first level protection
1: second level protection
HQ = 0: medium quality sound
1: high quality sound
S = 0: monophonic sound
1: stereophonic sound
209
PSL
0–7
packet 0 syndrom low byte
209
PSH
8–15
packet 0 syndrom high byte
PSL + PSH = 0: packet 0 received without error
PSL + PSH > 0: packet 0 received with error
210
PDL
0–7
packet 0 data low byte
210
PDH
8–15
packet 0 data high byte
30
DMA 2271, DMA 2280, DMA 2281
Table 4–3: DMA control and status registers, graphical overview
Addr. Bit
No.
No.
MSB
15
14
DI3
DI2
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
0
0
Direct.
14
DI1
VCOS
VCOA
W
VCO Adjustment
0
0
0
0
0
0
1
0
0
SAU
23
200
W
SAV
Saturation U
W
Saturation V
28
0
0
CT
CSE
CTS
0
0
0
0
0
CSP
L525
DGC
CMP
STA
PLLO
NIN
DLC
DCL
DSY
0
525
lines
0
Disable
Gray
0
Chroma
Mult.
0
Stand
alone
0
PLL
open
0
Non
Interl.
0
Disable
L/C
0
Clamp.
off
0
Disable
Sync.
0
Luma Contrast
Luma Delay
32
CSP
CFI
201
W
LFI
Chroma Filter
Luma Filter
0
0
202
W
0
W
S
BD
Composite Sync. Delay
Blank Delay
C1E
C1A
Channel Mode
Mode
Update
0
Channel
Enable
1
Channel Packet Addres
C2U
C2E
C2A
Mode
Update
0
Channel
Enable
1
Channel Packet Address
C3M
C3U
C3E
C3A
Channel Mode
Mode
Update
0
Channel
Enable
0
Channel Packet Address
C4U
C4E
C4A
Mode
Update
0
Channel
Enable
0
Channel Packet Address
H
L
Channel Mode
S
195
HQ
W
S
H
HQ
L
H
L
C4M
196
W
Channel Mode
S
DRS
197
W
Data
Rate
Select
1
HQ
H
L
AUM
CD
Auto
Mode
0
Chip
Defin.
0
100
100
100
100
SFS
Subframe Select
0
0
7
CLG
CS
198
199
W
Chip
Select
0
0
0
W
0
0
0
0
SLL
BPH
Burst
Phase
0
0
205
206
W
208
EDC
Clamping
Loop
Gain
2
0
FCD
Full
Chanel
Data
0
Energy Dispersal
Compensation
2
PLLG
SLS
ENF2
PLLT
PLL
Gain
2
Slicer
Select
1
Enable
Filters
0
PLL
Test
0
ACS
DSB
P0C
P0R
DGT
SBE
Audio Clock
Free
Switch
0
0
Disable
S_Bus
0
P0
Clear
0
P0
Reset
0
Data Group Type
S_Bus Enable
0
3
0
0
0
T15
T14
T13
T12
T11
T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SYNC
P0S
C49
C39
C29
C19
W
R
Status
207
0
Slice Level
ACF
204
0
C1U
HQ
W
64
0
C1M
C2M
194
6
SD
64
203
40
LD
S
209
R
210
R
BER
Bit Error Rate
BL
WL
Black Level
White Level
R
R
VER
Version
C4L
C3L
C2L
C1L
Coding Law CH4
Coding Law CH3
Coding Law CH2
Coding Law CH1
HQ
H
L
S
HQ
H
L
S
HQ
H
L
S
PSH
PSL
Packet 0 Syndrom High Byte
Packet 0 Syndrom Low Byte
PDH
PDL
Packet 0 Data High Byte
Packet 0 Data Low Byte
Bits must be set to zero for write registers (W) and
are don’t care for read registers (R)
HQ
H
L
Bits not used in DMA 2280 registers, but in other devices
31
DMA 2271, DMA 2280, DMA 2281
Table 4–4: VCU control and status registers, graphical overview
Addr. Bit
No.
No.
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
Direct.
SCS
16
17
18
19
W
W
W
W
SECAM
Chroma
Sync
1
NIE
Noise
Invert.
Enable
0
VI2
COB
BCR
BR
Video
Input 2
0
Code Bits
Beam Current
Reduction
0
Brightness
7
128
CR
DR
YDA
Cutoff Voltage Red
White Drive Red
127
127
Luma
Adder
1
CG
DG
BLD
Cutoff Voltage Green
White Drive Green
Blank
Disable
1
127
127
CB
DB
Cutoff Voltage Blue
White Drive Blue
127
W
0
Bits must be set to zero for write registers (W) and
are don’t care for read registers (R)
32
Luma
Adder
Shift
0
127
RGBC
27
YDAS
DGD
BEN
Ext. RGB Contrast
Double
Gain
Disable
Bit
Enlarg.
32
1
1
DMA 2271, DMA 2280, DMA 2281
33
DMA 2271, DMA 2280, DMA 2281
34
DMA 2271, DMA 2280, DMA 2281
35
DMA 2271, DMA 2280, DMA 2281
MICRONAS INTERMETALL GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: http://www.intermetall.de
Printed in Germany
by Simon Druck GmbH & Co., Freiburg (8/91)
Order No. 6251-331-1E
36
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for
conclusion of a contract nor shall they be construed as to
create any liability. Any new issue of this data sheet invalidates
previous issues. Product availability and delivery dates are exclusively subject to our respective order confirmation form; the
same applies to orders based on development samples delivered. By this publication, MICRONAS INTERMETALL GmbH
does not assume responsibility for patent infringements or
other rights of third parties which may result from its use.
Reprinting is generally permitted, indicating the source. However, our prior consent must be obtained in all cases.
MICRONAS INTERMETALL