Freescale Semiconductor, Inc. HYBRID MCU/DSP 56854 120 MIPS Hybrid Processor TARGET APPLICATIONS Freescale Semiconductor, Inc... • • • • • • • Stand-alone MP3 player DTAD Feature phone Voice recognition and command Embedded modem/data pump Voice processing Multi-processor Telephony Systems • LCD and keypad support • General purpose devices • Automotive hands-free BENEFITS • Supports multiple processor connections • Flexible 6-Channel Direct Memory Access (DMA) allows both internal and external memory transfers with almost no CPU interruption • 16-bit quad timer module (with four external pins) that allows capture/compare functionality, and can be cascaded • Serial peripheral interface with master and slave mode supporting connection to other processors or serial memory devices • Quad timer module can also be used for simple digital-to-analog conversion functionality • External memory expansion up to 2M words program memory or up to 8M words data memory increases capabilities of device for larger algorithms • Easy to program with flexible application development tools • Enhanced synchronous serial interface with enhanced network and audio modes • Time of Day for applications requiring clock display The 56854 offers a total of 32 KB of on-chip program SRAM and 32 KB of on-chip data SRAM. It is pin-to-pin compatible with the 56853, and can be dropped in as a replacement when applications require more on-chip memory. This device is an example of how Motorola is continuing to provide ease-of-use and flexibility in the design process. It enables you to retain your investment through design changes or future product enhancements via a cost-effective upward migration path. COP/Watchdog 56854 16-BIT DIGITAL SIGNAL PROCESSORS • 120 MIPS at 120MHz • Serial Peripheral Interface (SPI) • 32 KB Program SRAM • 8-bit parallel Host Interface • 32 KB Data SRAM • General purpose 16-bit Quad Timer • 2 KB Boot ROM • Access up to 4 MB of program or 16 MB data memory • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Chip Select Logic for glueless interface to ROM and SRAM • Computer Operating Properly (COP)/Watchdog Timer • Six independent channels of DMA • Time of Day (TOD) • Enhanced Synchronous Serial Interfaces (ESSI) • 128-pin LQFP package • Up to 41 GPIO • Two Serial Communication Interfaces (SCI) Program Memory ENERGY INFORMATION Ext Memory I/F 32 KB SRAM SPI 6-channel DMA Prog Chip Selects 2 KB Boot ROM (2) SCI ESSI Up to 41 GPIO 16-Bit Quad Timer • Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs 56800E Core 120 MIPS Time of Day Data Memory PLL 32 KB SRAM JTAG/EOnCE 8-Bit Host IF For More Information On This Product, Go to: www.freescale.com • Wait and Stop modes available Freescale Semiconductor, Inc. 56800E CORE FEATURES HYBRID MCU/DSP The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C compilers, enabling rapid development of optimized control applications. Features of the 56800E core include: 56854 PRODUCT DOCUMENTATION DSP56800E Reference Manual Freescale Semiconductor, Inc... DSP5685x User’s Manual DSP56854 Technical Data Sheet Detailed description of the 56800E architecture, 16-bit DSP core processor and the instruction set • Efficient 16-bit hybrid controller engine with dual Harvard architecture • Four internal data buses and one external data bus Order Number: DSP56800ERM/D • 120 Million Instructions Per Second (MIPS) at 120MHz core frequency • Instruction set supports both DSP and controller functions Detailed description of memory, peripherals, and interfaces of the 56853, 56854, 56855, 56857, and 56858 • Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) • Four hardware interrupt levels Order Number: DSP5685xUM/D • Four 36-bit accumulators, including extension bits • Controller-style addressing modes and instructions for compact code • 16-bit bidirectional shifter • Efficient C compiler and local variable support Electrical and timing specifications, pin descriptions, and package descriptions • Hardware DO and REP loops • Software subroutine and interrupt stack with depth limited only by memory Summary description and block diagram of the core, memory, peripherals • Three internal address buses and one external address bus • JTAG/Enhanced OnCE debug programming interface Order Number: DSP56854PB/D 56854 MEMORY FEATURES Order Number: DSP56854/D DSP56854 Product Brief and interfaces • Parallel instruction set with unique addressing modes • Five software interrupt levels • Harvard architecture permits up to three simultaneous accesses to program and data memory AWARD-WINNING DEVELOPMENT ENVIRONMENT • On-chip Memory – 32 KB Program SRAM • Processor Expert™ (PE) technology provides a rapid application design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. • The CodeWarrior™ Integrated Development Environment (IDE) is a sophisticated tool for code navigation, compiling and debugging. A comprehensive set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, the CodeWarrior tool suite and EVMs create a comprehensive, scalable tools solution for easy, fast and efficient development. – 32 KB Data SRAM • Off-Chip Memory Expansion (EMI) – Access up to 4 MB of program memory or up to 16 MB of data memory – Chip Select Logic for glueless interface to ROM and SRAM – 2 KB Boot ROM 56854 PERIPHERAL CIRCUIT FEATURES • General Purpose 16-bit Quad Timer with four external pins* • Six independent channels of DMA • Two Serial Communication Interfaces (SCI)* • Time of Day (TOD) • Serial Peripheral Interface (SPI) Port* • Enhanced Synchronous Serial Interface (ESSI) module* • 8-bit parallel Host Interface* • Up to 41 GPIO * Each peripheral I/O can be used alternately as a General Purpose I/O • Computer Operating Properly (COP) • Watchdog Timer • JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging ORDERING INFORMATION PART SUPPLY VOLTAGE PACKAGE TYPE PIN COUNT FREQUENCY (MHz) ORDER NUMBER DSP56854 DSP56854 1.8V, 3.3V 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) Low-Profile Quad Flat Pack (LQFP) 128 128 120 120 DSP56854FG120 SPAK56854FG120 Motorola and the stylized M Logo are registered in the U.S. Patent and Trademark Office. This product incorporates SuperFlash® technology licensed from SST. All other product or service names are the property of their respective owners. © Motorola, Inc. 2003 DSP56854PB/D For More Information On This Product, REV 3 Go to: www.freescale.com