Freescale Semiconductor, Inc. HYBRID MCU/DSP 56853 120 MIPS Hybrid Processor TARGET APPLICATIONS Freescale Semiconductor, Inc... • • • • • • • DTAD Feature phone Voice recognition and command Embedded modem/data pump Voice processing Low bit rate audio processing Multi-processor Telephony Systems • LCD and keypad support • General purpose devices • Automotive hands-free BENEFITS • Supports multiple processor connections • Flexible 6-Channel Direct Memory Access (DMA) allows both internal and external memory transfers with almost no CPU interruption • 16-bit quad timer module (with four external pins) that allows capture/compare functionality, and can be cascaded • Serial peripheral interface with master and slave mode supporting connection to other processors or serial memory devices • Quad timer module can also be used for simple digital-to-analog conversion functionality • External memory expansion up to 2M words program memory or up to 8M words data memory increases capabilities of device for larger algorithms • Easy to program with flexible application development tools • Enhanced synchronous serial interface with enhanced network and audio modes The 56853’s memory and peripheral set make it ideal for a variety of applications, with a total of four external timer outputs for the quad timer, an additional SCI/UART, an 8-bit host interface and 6-channel direct memory access (DMA). Also, the 56853 offers an enhanced synchronous serial interface (ESSI), with enhanced networking mode and audio capabilities. The external memory expansion is also increased for an additional 2 MB of data addressing space. The 56853 also includes a Time of Day module for applications, requiring clock features. With the host interface and serial peripherals, multiple 56853 devices can be designed into a system to interface gluelessly with other Motorola processors, such as the MPC8xx and ColdFire processors, adding such DSP functionality as voice processing to network applications. The 56853 is available in a 128-pin LQFP package and is an ideal stand-alone processor for client-side telecom/datacom applications, requiring only a few channels. • Time of Day for applications requiring clock display 56853 16-BIT DIGITAL SIGNAL PROCESSORS • 120 MIPS at 120MHz • Serial Peripheral Interface (SPI) • 24 KB Program SRAM • 8-bit parallel Host Interface • 8 KB Data SRAM • General purpose 16-bit Quad Timer • 2 KB Boot ROM • Access up to 4 MB of program memory or up to 16 MB of data memory • JTAG/Enhanced On-Chip Emulation (OnCETM) for unobtrusive, real-time debugging • Chip Select Logic for glueless interface to ROM and SRAM • Computer Operating Properly (COP)/Watchdog Timer • Six independent channels of DMA • Time of Day (TOD) • Enhanced Synchronous Serial Interfaces (ESSI) • 128-pin LQFP package • Two Serial Communication Interfaces (SCI) ENERGY INFORMATION • Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs COP/Watchdog Program Memory Ext Memory I/F 24 KB SRAM SPI 6-channel DMA Prog Chip Selects 2 KB Boot ROM 16-Bit Quad Timer (2) SCI ESSI Up to 41 GPIO 56800E Core 120 MIPS Time of Day Data Memory PLL 8 KB SRAM JTAG/EOnCE For More Information On This Product, Go to: www.freescale.com 8-Bit Host • Up to 41 GPIO • Wait and Stop modes available Freescale Semiconductor, Inc. 56800E CORE FEATURES HYBRID MCU/DSP The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C compilers, enabling rapid development of optimized control applications. Features of the 56800E core include: 56853 PRODUCT DOCUMENTATION DSP56800E Reference Manual Freescale Semiconductor, Inc... DSP5685x User’s Manual DSP56853 Technical Data Sheet DSP56853 Product Brief Detailed description of the 56800E architecture, 16-bit DSP core processor and the instruction set • Efficient 16-bit hybrid controller engine with dual Harvard architecture • Four internal data buses and one external data bus Order Number: DSP56800ERM/D • 120 Million Instructions Per Second (MIPS) at 120MHz core frequency • Instruction set supports both DSP and controller functions Detailed description of memory, peripherals, and interfaces of the 56853, 56854, 56855, 56857, and 56858 • Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) • Four hardware interrupt levels Order Number: DSP5685xUM/D • Four 36-bit accumulators, including extension bits • Controller-style addressing modes and instructions for compact code • 16-bit bidirectional shifter • Efficient C compiler and local variable support Electrical and timing specifications, pin descriptions, and package descriptions Order Number: DSP56853/D Summary description and block diagram of the core, memory, peripherals and interfaces Order Number: DSP56853PB/D • Parallel instruction set with unique addressing modes • Hardware DO and REP loops • Software subroutine and interrupt stack with depth limited only by memory • Three internal address buses and one external address bus • JTAG/Enhanced OnCE debug programming interface 56853 MEMORY FEATURES • Harvard architecture permits up to three simultaneous accesses to program and data memory AWARD-WINNING DEVELOPMENT ENVIRONMENT • On-chip Memory – 24 KB Program SRAM • Processor Expert™ (PE) technology provides a rapid application design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. • The CodeWarrior™ Integrated Development Environment (IDE) is a sophisticated tool for code navigation, compiling and debugging. A comprehensive set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, the CodeWarrior tool suite and EVMs create a comprehensive, scalable tools solution for easy, fast and efficient development. • Five software interrupt levels • Off-Chip Memory Expansion (EMI) – Access up to 2 MB of program memory or up to 16 MB data memory – Chip Select Logic for glueless interface to ROM and SRAM – 8 KB Data SRAM – 2 KB Boot ROM 56853 PERIPHERAL CIRCUIT FEATURES • General Purpose 16-bit Quad Timer with four external pins* • Six independent channels of DMA • Two Serial Communication Interfaces (SCI)* • Time of Day (TOD) • Serial Peripheral Interface (SPI) Port* • Enhanced Synchronous Serial Interface (ESSI) modules* • 8-bit parallel Host Interface* • Up to 41 GPIO * Each peripheral I/O can be used alternately as a General Purpose I/O • Computer Operating Properly (COP)/Watchdog Timer • JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging ORDERING INFORMATION PART SUPPLY VOLTAGE PACKAGE TYPE PIN COUNT FREQUENCY (MHz) ORDER NUMBER DSP56853 DSP56853 1.8V, 3.3V 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) Low-Profile Quad Flat Pack (LQFP) 128 128 120 120 DSP56853FG120 SPAK56853FG120 Motorola and the stylized M Logo are registered in the U.S. Patent and Trademark Office. This product incorporates SuperFlash® technology licensed from SST. All other product or service names are the property of their respective owners. © Motorola, Inc. 2003 DSP56853PB/D REV 3 For More Information On This Product, Go to: www.freescale.com