ISL6526 ® Data Sheet July 2003 Single Synchronous Buck Pulse-Width Modulation (PWM) Controller Features • Operates from 3.3V to 5V Input The ISL6526 makes simple work out of implementing a complete control and protection scheme for a DC-DC stepdown converter. Designed to drive N-Channel MOSFETs in a synchronous buck topology, the ISL6526 integrates the control, output adjustment, monitoring and protection functions into a single package. The ISL6526 provides simple, single feedback loop, voltagemode control with fast transient response. The output voltage can be precisely regulated to as low as 0.8V, with a maximum tolerance of ±1.5% over temperature and line voltage variations. A fixed frequency oscillator reduces design complexity, while balancing typical application cost and efficiency. The error amplifier features a 15MHz gain-bandwidth product and 6V/µs slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty cycles range from 0% to 100%. Protection from overcurrent conditions is provided by monitoring the rDS(ON) of the upper MOSFET to inhibit PWM operation appropriately. This approach simplifies the implementation and improves efficiency by eliminating the need for a current sense resistor. Ordering Information TEMP PART NUMBER RANGE (oC) PACKAGE PKG DWG. # • 0.8V to VIN Output Range - 0.8V Internal Reference - ±1.5% Over Load, Line Voltage and Temperature • Drives N-Channel MOSFETs • Simple Single-Loop Control Design - Voltage-Mode PWM Control • Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Cycle • Lossless, Programmable Overcurrent Protection - Uses Upper MOSFET’s rDS(on) • Converter can Source and Sink Current • Small Converter Size - Internal Fixed Frequency Oscillator - ISL6526: 300kHz - ISL6526A: 600kHz • Internal Soft-Start • 14 Lead SOIC or 16 Lead, 5x5 QFN • QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile ISL6526CB 0 to 70 14 Lead SOIC M14.15 Applications ISL6526ACB 0 to 70 14 Lead SOIC M14.15 ISL6526CR 0 to 70 16 Lead 5x5 QFN L16.5x5B ISL6526ACR 0 to 70 16 Lead 5x5 QFN L16.5x5B • Power Supplies for Microprocessors - PCs - Embedded Controllers ISL6526IB -40 to 85 14 Lead SOIC M14.15 ISL6526AIB -40 to 85 14 Lead SOIC M14.15 ISL6526IR -40 to 85 16 Lead 5x5 QFN L16.5x5B ISL6526AIR -40 to 85 16 Lead 5x5 QFN L16.5x5B ISL6526EVAL1 ISL6526 SOIC Evaluation Board ISL6526EVAL2 ISL6526 QFN Evaluation Board ISL6526AEVAL1 ISL6526A SOIC Evaluation Board ISL6526AEVAL2 ISL6526A QFN Evaluation Board FN9055.3 • Subsystem Power Supplies - PCI/AGP/GTL+ Busses - ACPI Power Control - DDR SDRAM Bus Termination Supply • Cable Modems, Set Top Boxes, and DSL Modems • DSP and Core Communications Processor Supplies • Memory Supplies • Personal Computer Peripherals • Industrial Power Supplies • 3.3V-Input DC-DC Regulators • Low-Voltage Distributed Power Supplies 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL6526 Pinouts 12 PHASE CT1 4 11 VCC CT2 5 10 CPGND 15 14 13 1 12 PHASE CT1 2 11 VCC CT2 3 10 CPGND OCSET 4 9 7 8 ENABLE 6 COMP 5 FB 8 COMP NC FB 7 16 CPVOUT 9 ENABLE OCSET 6 BOOT 13 BOOT CPVOUT 3 UGATE 14 UGATE LGATE 2 GND GND 1 16 LEAD 5X5 (QFN) TOP VIEW LGATE 14 LEAD (SOIC) TOP VIEW NC Typical Application - 3.3V Input 3.3V VIN CIN CBULK VCC OCSET CT1 ROCSET CPUMP CPVOUT CT2 ISL6526 DBOOT CDCPL CHF BOOT CPGND CBOOT UGATE GND Q1 PHASE ENABLE LGATE COMP DISABLE Q2 FB CI RFB RF CF ROFFSET 2 LOUT COUT VOUT ISL6526 Typical Application - 5V Input +5V VIN CBULK VCC OCSET CT1 ROCSET CPVOUT N/C CT2 ISL6526 DBOOT CIN CHF BOOT CPGND CBOOT UGATE GND Q1 PHASE ENABLE LGATE COMP DISABLE Q2 FB LOUT VOUT COUT CI RFB CF RF ROFFSET Block Diagram VCC CT1 CPVOUT CHARGE PUMP CT2 POWER-ON RESET (POR) ENABLE CPGND BOOT + - OCSET SOFTSTART OC COMPARATOR 20µA UGATE ERROR AMP + - + 0.8V PWM COMPARATOR + - INHIBIT PHASE GATE CONTROL LOGIC PWM LGATE FB OSCILLATOR COMP FIXED 300kHz or 600kHz GND 3 ISL6526 Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Thermal Resistance θJA (oC/W) θJC (oC/W) SOIC Package (Note 1) . . . . . . . . . . . . 67 N/A QFN Package (Note 2). . . . . . . . . . . . . 35 5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) For Recommended soldering conditions see Tech Brief TB389. Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V ±10% Ambient Temperature Range . . . . . . . . . . . . . . . . . . . -40oC to 85oC Junction Temperature Range. . . . . . . . . . . . . . . . . . -40oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the “case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications Recommended Operating Conditions, unless otherwise noted VCC = 3.3V±5% and TA = 25°C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 6.1 6.9 7.7 mA Commercial 4.25 4.30 4.42 V Industrial 4.10 4.30 4.50 V 0.3 0.6 0.9 V IC = ISL6526C, Commercial 275 300 325 kHz IC = ISL6526I, Industrial 250 300 340 kHz IC = ISL6526AC, Commercial 575 600 625 kHz IC = ISL6526AI, Industrial 550 600 640 kHz - 1.5 - VP-P - - 1.5 % - 0.800 - V - 5.1 - V - 2 - % - 88 - dB GBWP - 15 - MHz SR - 6 - V/µs Commercial 6.2 - 7.3 ms Industrial 6.2 - 7.6 ms VCC SUPPLY CURRENT Nominal Supply IBIAS POWER-ON RESET Rising CPVOUT POR Threshold POR CPVOUT POR Threshold Hysteresis OSCILLATOR Frequency fOSC ∆VOSC Ramp Amplitude REFERENCE Reference Voltage Tolerance Nominal Reference Voltage VREF Charge Pump Nominal Charge Pump Output VCPVOUT VVCC = 3.3V, No Load Charge Pump Output Regulation ERROR AMPLIFIER DC Gain Guaranteed by Design Gain-Bandwidth Product Slew Rate SOFT START Soft Start Slew Rate 4 ISL6526 Electrical Specifications Recommended Operating Conditions, unless otherwise noted VCC = 3.3V±5% and TA = 25°C (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS GATE DRIVERS Upper Gate Source Current IUGATE-SRC VBOOT - VPHASE = 5V, VUGATE = 4V - -1 - A Upper Gate Sink Current IUGATE-SNK - 1 - A Lower Gate Source Current ILGATE-SRC VVCC = 3.3V, VLGATE = 4V - -1 - A Lower Gate Sink Current ILGATE-SNK - 2 - A Commercial 18 20 22 µA Industrial 16 20 22 µA - - 0.8 V PROTECTION / DISABLE OCSET Current Source IOCSET Disable Threshold VDISABLE Functional Pin Description GND 14 LEAD (SOIC) TOP VIEW 14 UGATE GND 1 LGATE 2 CPVOUT 3 13 BOOT PHASE 12 PHASE Connect this pin to the upper MOSFET’s source. This pin is used to monitor the voltage drop across the upper MOSFET for overcurrent protection. CT1 4 11 VCC CT2 5 10 CPGND 9 ENABLE OCSET 6 FB 7 This pin represents the signal and power ground for the IC. Tie this pin to the ground island/plane through the lowest impedance connection available. 8 COMP LGATE GND UGATE BOOT 16 LEAD 5X5 (QFN) TOP VIEW 16 15 14 13 UGATE Connect this pin to the upper MOSFET’s gate. This pin provides the PWM-controlled gate drive for the upper MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the upper MOSFET has turned off. BOOT This pin provides ground referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive a logic-level N-Channel MOSFET. 2 11 VCC LGATE CT2 3 10 CPGND OCSET 4 9 Connect this pin to the lower MOSFET’s gate. This pin provides the PWM-controlled gate drive for the lower MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the lower MOSFET has turned off. 5 6 7 8 ENABLE CT1 COMP 12 PHASE FB 1 NC CPVOUT NC VCC This pin provides the bias supply for the ISL6526. Connect a well-decoupled 3.3V supply to this pin. COMP and FB COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the internal error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltagecontrol feedback loop of the converter. 5 OCSET Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET (VIN). ROCSET, an internal 20µA current source (IOCSET), and the upper MOSFET on-resistance (rDS(ON)) set the converter overcurrent (OC) trip point according to the following equation: I OCSET xR OCSET I PEAK = ------------------------------------------------r DS ( ON ) An overcurrent trip cycles the soft-start function. ISL6526 ENABLE This pin is the open-collector enable pin. Pulling this pin to a level below 0.8V will disable the controller. Disabling the ISL6526 causes the oscillator to stop, the LGATE and UGATE outputs to be held low, and the softstart circuitry to re-arm. width on the UGATE pin increases to reach the steady-state duty cycle at time t3. (1V/DIV) CPVOUT (5V) VCC (3.3V) CT1 and CT2 These pins are the connections for the external charge pump capacitor. A minimum of a 0.1µF ceramic capacitor is recommended for proper operation of the IC. VOUT (2.50V) CPVOUT This pin represents the output of the charge pump. The voltage at this pin is the bias voltage for the IC. Connect a decoupling capacitor from this pin to ground. The value of the decoupling capacitor should be at least 10x the value of the charge pump capacitor. This pin may be tied to the bootstrap circuit as the source for creating the BOOT voltage. CPGND This pin represents the signal and power ground for the charge pump. Tie this pin to the ground island/plane through the lowest impedance connection available. Functional Description Initialization The ISL6526 automatically initializes upon receipt of power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the the output voltage of the charge pump. During POR, the charge pump operates on a free running oscillator. Once the POR level is reached, the charge pump oscillator is synched to the PWM oscillator. The POR function also initiates the soft-start operation after the charge pump output voltage exceeds its POR threshold. Soft-Start The POR function initiates the digital soft-start sequence. The PWM error amplifier reference is clamped to a level proportional to the soft-start voltage. As the soft-start voltage slews up, the PWM comparator generates PHASE pulses of increasing width that charge the output capacitor(s). This method provides a rapid and controlled output voltage rise. The soft start sequence typically takes about 6.5ms. Figure 1 shows the soft-start sequence for a typical application. At t0, the +3.3V VCC voltage starts to ramp. At time t1, the Charge Pump begins operation and the +5V CPVOUT IC bias voltage starts to ramp up. Once the voltage on CPVOUT crosses the POR threshold at time t2, the output begins the soft-start sequence. The triangle waveform from the PWM oscillator is compared to the rising error amplifier output voltage. As the error amplifier voltage increases, the pulse- 6 0V T0 T1 T3 T2 TIME FIGURE 1. SOFT-START INTERVAL Shoot-Through Protection A shoot-through condition occurs when both the upper MOSFET and lower MOSFET are turned on simultaneously, effectively shorting the input voltage to ground. To protect the regulator from a shoot-through condition, the ISL6526 incorporates specialized circuitry which insures that the complementary MOSFETs are not ON simultaneously. The adaptive shoot-through protection utilized by the ISL6526 looks at the lower gate drive pin, LGATE, and the upper gate drive pin, UGATE, to determine whether a MOSFET is ON or OFF. If the voltage from UGATE or from LGATE to GND is less than 0.8V, then the respective MOSFET is defined as being OFF and the complementary MOSFET is turned ON. This method of shoot-through protection allows the regulator to sink or source current. Since the voltage of the lower MOSFET gate and the upper MOSFET gate are being measured to determine the state of the MOSFET, the designer is encouraged to consider the repercussions of introducing external components between the gate drivers and their respective MOSFET gates before actually implementing such measures. Doing so may interfere with the shoot-through protection. Output Voltage Selection The output voltage can be programmed to any level between VIN and the internal reference, 0.8V. An external resistor divider is used to scale the output voltage relative to the reference voltage and feed it back to the inverting input of the error amplifier, see Figure 2. However, since the value of R1 affects the values of the rest of the compensation components, it is advisable to keep its value less than 5kΩ. R4 can be calculated based on the following equation: R1 × 0.8V R4 = -------------------------------------V OUT1 – 0.8V ISL6526 If the output voltage desired is 0.8V, simply route the output back to the FB pin through R1, but do not populate R4. mode style of protection would continue to repeat indefinitely. +3.3V VOUT (2.5V) VIN VCC CPVOUT D1 BOOT C4 UGATE ISL6526 Q1 LOUT VOUT PHASE Q2 LGATE 0V + COUT INTERNAL SOFT-START FUNCTION FB C1 COMP R1 C3 C2 Delay Interval R3 R2 R4 T1 T0 T2 TIME FIGURE 3. OVER CURRENT PROTECTION RESPONSE FIGURE 2. OUTPUT VOLTAGE SELECTION Overcurrent Protection The overcurrent function protects the converter from a shorted output by using the upper MOSFET on-resistance, rDS(ON), to monitor the current. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor. The overcurrent function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the overcurrent trip level (see Typical Application diagrams on pages 2 and 3). An internal 20µA (typical) current sink develops a voltage across ROCSET that is referenced to VIN. When the voltage across the upper MOSFET (also referenced to VIN) exceeds the voltage across ROCSET , the overcurrent function initiates a soft-start sequence. Figure 3 illustrates the protection feature responding to an overcurrent event. At time t0, an overcurrent condition is sensed across the upper MOSFET. As a result, the regulator is quickly shutdown and the internal soft-start function begins producing soft-start ramps. The delay interval seen by the output is equivalent to three soft-start cycles. The fourth internal soft-start cycle initiates a normal soft-start ramp of the output, at time t1. The output is brought back into regulation by time t2, as long as the overcurrent event has cleared. Had the cause of the over current still been present after the delay interval, the over current condition would be sensed and the regulator would be shut down again for another delay interval of three soft-start cycles. The resulting hiccup 7 The overcurrent function will trip at a peak inductor current (IPEAK) determined by: I OCSET x R OCSET I PEAK = ----------------------------------------------------r DS ( ON ) where IOCSET is the internal OCSET current source (20µA typical). The OC trip point varies mainly due to the MOSFET rDS(ON) variations. To avoid overcurrent tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. ( ∆I ) 3. Determine IPEAK for I PEAK > I OUT ( MAX ) + --------2 , where ∆I is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’. A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage. Current Sinking The ISL6526 incorporates a MOSFET shoot-through protection method which allows a converter to sink current as well as source current. Care should be exercised when designing a converter with the ISL6526 when it is known that the converter may sink current. When the converter is sinking current, it is behaving as a boost converter that is regulating its input voltage. This ISL6526 means that the converter is boosting current into the input rail of the regulator. If there is nowhere for this current to go, such as to other distributed loads on the rail or through a voltage limiting protection device, the capacitance on this rail will absorb the current. This situation will allow the voltage level of the input rail to increase. If the voltage level of the rail is boosted to a level that exceeds the maximum voltage rating of any components attached to the input rail, then those components may experience an irreversible failure or experience stress that may shorten their lifespan. Ensuring that there is a path for the current to flow other than the capacitance on the rail will prevent this failure mode. Application Guidelines the GATE pins to the MOSFET gates should be kept short and wide enough to easily handle the 1A of drive current.f +3.3V VIN ISL6526 VCC CVCC CPVOUT CBP GND CIN D1 BOOT CBOOT Layout is very important in high frequency switching converter design. With power devices switching efficiently at 300kHz or 600kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit board design minimizes the voltage spikes in the converters. As an example, consider the turn-off transition of the PWM MOSFET. Prior to turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the lower MOSFET. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. There are two sets of critical components in a DC-DC converter using the ISL6526. The switching components are the most critical because they switch large amounts o energy, and therefore tend to generate large amounts of noise. Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. A multi-layer printed circuit board is recommended. Figure 4 shows the connections of the critical components in the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer, usually a middle layer of the PC board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminals to the output inductor short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. The wiring traces from 8 Q1 UGATE PHASE Q2 LGATE COMP LOUT PHASE C2 VOUT COUT LOAD Layout Considerations C1 R2 R1 FB R4 C3 R3 KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER VIA CONNECTION TO GROUND PLANE FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS The switching components should be placed close to the ISL6526 first. Minimize the length of the connections between the input capacitors, CIN, and the power switches by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible. Position the output inductor and output capacitors between the upper MOSFET and lower MOSFET and the load. The critical small signal components include any bypass capacitors, feedback components, and compensation components. Position the bypass capacitor, CBP, close to the VCC pin with a via directly to the ground plane. Place the PWM converter compensation components close to the FB and COMP pins. The feedback resistors for both regulators should also be located as close as possible to the relevant FB pin with vias tied straight to the ground plane as required. Feedback Compensation Figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage ISL6526 (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulsewidth modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR . The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ∆VOSC . PWM COMPARATOR LO + ∆VOSC DRIVER PHASE VOUT CO ESR (PARASITIC) ZFB VE/A ZIN + ERROR AMP REFERENCE DETAILED COMPENSATION COMPONENTS ZFB C1 C2 VOUT ZIN C3 R2 R3 R1 COMP FB + 3. Place second zero at filter’s double pole. 4. Place first pole at the ESR zero. 5. Place second pole at half the switching frequency. 6. Check gain against error amplifier’s open-loop gain. 7. Estimate phase margin - repeat if necessary. Compensation Break Frequency Equations 1 F Z1 = ---------------------------------2π × R 2 × C 2 1 F P1 = -------------------------------------------------------- C 1 x C 2 2π x R 2 x ---------------------- C1 + C2 1 F Z2 = ------------------------------------------------------2π x ( R 1 + R 3 ) x C 3 1 F P2 = -----------------------------------2π x R 3 x C 3 VIN DRIVER OSC 1. Pick gain (R2/R1) for desired converter bandwidth. 2. Place first zero below filter’s double pole (~75% FLC). ISL6526 REFERENCE FIGURE 5. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN Figure 6 shows an asymptotic plot of the DC-DC converter’s gain vs frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 6. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the graph of Figure 6 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. FZ1 FZ2 FP1 FP2 100 Modulator Break Frequency Equations 1 F ESR = ------------------------------------------2π x ESR x C O The compensation network consists of the error amplifier (internal to the ISL6526) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figure 5. Use these guidelines for locating the poles and zeros of the compensation network: 9 V IN 20 log ------------------ V OSC 80 60 GAIN (dB) 1 F LC = -----------------------------------------2π x L O x C O OPEN LOOP ERROR AMP GAIN 40 COMPENSATION GAIN 20 0 -20 -40 -60 R2 20 log -------- R1 MODULATOR GAIN 10 100 FLC 1K LOOP GAIN FESR 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN ISL6526 Component Selection Guidelines Charge Pump Capacitor Selection A capacitor across pins CT1 and CT2 is required to create the proper bias voltage for the ISL6526 when operating the IC from 3.3V. Selecting the proper capacitance value is important so that the bias current draw and the current required by the MOSFET gates do not overburden the capacitor. A conservative approach is presented in the following equation. I BiasAndGate C PUMP = ------------------------------------ × 1.5 V CC × f s Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern digital ICs can produce high transient load slew rates. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function 10 of the ripple current. The ripple voltage and current are approximated by the following equations: ∆I = VIN - VOUT fs x L x VOUT ∆VOUT = ∆I x ESR VIN Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6526 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUT where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2 . The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. ISL6526 The maximum RMS current required by the regulator may be closely approximated through the following equation: I RMS MAX = V OUT V IN – V OUT V OUT 2 2 1 -------------- × I OUT + ------ × ----------------------------- × -------------- V IN V IN 12 L × f s MAX For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge currentrating. These capacitors must be capable of handling the surge-current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. MOSFET Selection/Considerations The ISL6526 requires two N-Channel power MOSFETs. These should be selected based upon rDS(ON) , gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor. The switching losses seen when sourcing current will be different from the switching losses seen when sinking current. When sourcing current, the upper MOSFET realizes most of the switching losses. The lower switch realizes most of the switching losses when the converter is sinking current (see equations on next page). These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse-recovery of the upper and lower MOSFET’s body diode. The gate-charge losses are dissipated by the ISL6526 and don't heat the MOSFETs. However, large gate-charge increases the switching interval, tSW which increases the MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. Losses while Sourcing current 2 1 P UPPER = Io × r DS ( ON ) × D + --- ⋅ Io × V IN × t SW × f s 2 PLOWER = Io2 x rDS(ON) x (1 - D) Losses while Sinking current PUPPER = Io2 x rDS(ON) x D 2 1 P LOWER = Io × r DS ( ON ) × ( 1 – D ) + --- ⋅ Io × V IN × t SW × f s 2 Where: D is the duty cycle = VOUT / VIN , tSW is the combined switch ON and OFF time, and fs is the switching frequency. 11 Given the reduced available gate bias voltage (5V), logiclevel or sub-logic-level transistors should be used for both NMOSFETs. Caution should be exercised with devices exhibiting very low VGS(ON) characteristics. The shootthrough protection present aboard the ISL6526 may be circumvented by these MOSFETs if they have large parasitic impedences and/or capacitances that would inhibit the gate of the MOSFET from being discharged below its threshold level before the complementary MOSFET is turned on. Bootstrap Component Selection External bootstrap components, a diode and capacitor, are required to provide sufficient gate enhancement to the upper MOSFET. The internal MOSFET gate driver is supplied by the external bootstrap circuitry as shown in Figure 7. The boot capacitor, CBOOT, develops a floating supply voltage referenced to the PHASE pin. This supply is refreshed each cycle, when DBOOT conducts, to a voltage of CPVOUT less the boot diode drop, VD, plus the voltage rise across QLOWER. CPVOUT DBOOT + VD - VIN BOOT CBOOT ISL6526 UGATE QUPPER PHASE + LGATE NOTE: VG-S = VCC -VD QLOWER NOTE: VG-S = VCC GND FIGURE 7. UPPER GATE DRIVE BOOTSTRAP Just after the PWM switching cycle begins and the charge transfer from the bootstrap capacitor to the gate capacitance is complete, the voltage on the bootstrap capacitor is at its lowest point during the switching cycle. The charge lost on the bootstrap capacitor will be equal to the charge transferred to the equivalent gate-source capacitance of the upper MOSFET as shown: Q GATE = C BOOT × ( V BOOT1 – V BOOT2 ) where QGATE is the maximum total gate charge of the upper MOSFET, CBOOT is the bootstrap capacitance, VBOOT1 is the bootstrap voltage immediately before turn-on, and VBOOT2 is the bootstrap voltage immediately after turn-on. The bootstrap capacitor begins its refresh cycle when the gate drive begins to turn-off the upper MOSFET. A refresh cycle ends when the upper MOSFET is turned on again, which varies depending on the switching frequency and duty cycle. ISL6526 The minimum bootstrap capacitance can be calculated by rearranging the previous equation and solving for CBOOT. For example, consider an upper MOSFET is chosen with a maximum gate charge, Qg, of 100nC. Limiting the voltage drop across the bootstrap capacitor to 1V results in a value of no less than 0.1µF. The tolerance of the ceramic capacitor should also be considered when selecting the final bootstrap capacitance value. Q GATE C BOOT = ----------------------------------------------------V BOOT1 – V BOOT2 Typical gate charge values for MOSFETs considered in these types of applications range from 20 to 100nC. Since the voltage drop across QLOWER is negligible, VBOOT1 is simply VCPVOUT - VD. A schottky diode is recommended to minimize the voltage drop across the bootstrap capacitor during the on-time of the upper MOSFET. Initial calculations with VBOOT2 no less than 4V will quickly help narrow the bootstrap capacitor range. A fast recovery diode is recommended when selecting a bootstrap diode to reduce the impact of reverse recovery charge loss. Otherwise, the recovery charge, QRR, would have to be added to the gate charge of the MOSFET and taken into consideration when calculating the minimum bootstrap capacitance. ISL6526 DC-DC Converter Application Circuit Figure 8 shows an application circuit of a DC-DC Converter. Detailed information on the circuit, including a complete Bill- of-Materials and circuit board description, can be found in Application Note AN9994.. 3.3V C1 0.1µF GND 11 TP1 4 C2 1000pF U1 VCC OCSET CT1 C3 6 ISL6526 CPVOUT 5 10 1 ENABLE 3 C5 10µF Ceramic D1 CT2 BOOT CPGND UGATE GND PHASE 9 R1 9.76kΩ TP3 C4 0.22µF ENABLE LGATE COMP 13 14 C7 0.1µF L1 12 2 C8,9 7 C10 R3 33pF R2 C11 2.26kΩ R4 6.49kΩ 5600pF R5 1.07kΩ 124Ω C12 8200pF FIGURE 8. 3.3V TO 2.5V 5A DC-DC CONVERTER Component Selection Notes: C3,8,9 - Each 150µF, Panasonic EEF-UE0J151R or Equivalent. D1 - 30mA Schottky Diode, MA732 or Equivalent L1 - 1µH Inductor, Panasonic P/N ETQ-P6F1ROSFA or Equivalent. Q1 - Fairchild MOSFET; ITF86110DK8. 12 2.5V @ 5A Q1 FB 8 C6 1µF GND ISL6526 Small Outline Plastic Packages (SOIC) M14.15 (JEDEC MS-012-AB ISSUE C) N INDEX AREA 0.25(0.010) M H 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- µα e A1 B 0.25(0.010) M C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 e C 0.10(0.004) B S 0.050 BSC 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 13 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N NOTES: MILLIMETERS α 14 0o 14 8o 0o 7 8o Rev. 0 12/93 ISL6526 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L16.5x5B 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHB ISSUE C) MILLIMETERS SYMBOL MIN NOMINAL A 0.80 A1 - A2 - A3 b NOTES 0.90 1.00 - - 0.05 - - 1.00 9 0.20 REF 0.28 D 0.33 9 0.40 5, 8 5.00 BSC D1 D2 MAX - 4.75 BSC 2.95 3.10 9 3.25 7, 8 E 5.00 BSC - E1 4.75 BSC 9 E2 2.95 e 3.10 3.25 7, 8 0.80 BSC - k 0.25 - - - L 0.35 0.60 0.75 8 L1 - - 0.15 10 N 16 2 Nd 4 3 Ne 4 3 P - - 0.60 9 θ - - 12 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14