AD AD9927BBCZRL

14-Bit CCD Signal Processor with V-Driver
and Precision TimingTM Generator
AD9927
FEATURES
GENERAL DESCRIPTION
Integrated 18-channel V-driver
1.8 V AFETG core
Internal LDO regulator and charge pump circuitry
Compatibility with 3 V or 1.8 V systems
24 programmable vertical clock signals
Correlated double sampler (CDS) with −3 dB, 0 dB,
+3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
14-bit, 40 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with ~400 ps resolution
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and
system support
On-chip driver for external crystal
On-chip sync generator with external sync input
128-lead CSP_BGA package, 9 mm × 9 mm, 0.65 mm pitch
The AD9927 is a highly integrated CCD signal processor for
digital still camera applications. It includes a complete analog
front end with A/D conversion, combined with a full-function
programmable timing generator and 18-channel vertical driver
(V-driver). The timing generator is capable of supporting up to
24 vertical clock signals to control advanced CCDs. The onchip V-driver supports up to 18 channels for use with 5-field
CCDs. A Precision Timing core allows adjustment of high speed
clocks with approximately 400 ps resolution at 40 MHz
operation. The AD9927 also contains eight general-purpose
outputs, which can be used for shutter and system functions.
The analog front end includes black level clamping, CDS, VGA,
and a 14-bit ADC. The timing generator provides all the
necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control.
The AD9927 is specified over an operating temperature range
of –25°C to +85°C.
APPLICATIONS
Digital still cameras
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9927
–3dB, 0dB, +3dB, +6dB
CDS
CCDIN
VREF
14-BIT
ADC
VGA
6dB TO 42dB
3V INPUT
14
DOUT
CLAMP
LDO
REG
1.8V OUTPUT
1.8V INPUT
CHARGE
PUMP
3V OUTPUT
INTERNAL CLOCKS
RG
8
PRECISION
TIMING
GENERATOR
HORIZONTAL
DRIVERS
H1 TO H8
V1A-V6 (3-LEVEL)
V7-V15 (2-LEVEL)
SL
INTERNAL
REGISTERS
SDATA
XV1 TO XV24
18
VERTICAL
DRIVER
24
SUBCK
XSUBCK
XSUBCNT
SCK
VERTICAL
TIMING
CONTROL
SYNC
GENERATOR
8
GP01 TO GP08
HD
VD SYNC CLI
CLO
RSTB
05892-103
HL
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD9927
TABLE OF CONTENTS
Features .............................................................................................. 1
Internal Vertical Driver Connections...................................... 45
Applications....................................................................................... 1
Vertical Timing Example........................................................... 53
General Description ......................................................................... 1
Shutter Timing Control ............................................................. 55
Functional Block Diagram .............................................................. 1
Substrate Clock Operation (SUBCK) ...................................... 55
Specifications..................................................................................... 3
Field Counters............................................................................. 58
Digital Specifications ................................................................... 4
General-Purpose Outputs (GPOS) .......................................... 59
Analog Specifications................................................................... 5
GP Look-Up Tables (LUT)........................................................ 63
Timing Specifications .................................................................. 6
Complete Exposure/Readout Operation
Using Primary Counter and GPO Signals .............................. 64
Vertical Driver Specifications ..................................................... 7
Absolute Maximum Ratings............................................................ 8
Package Thermal Characteristics ............................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 12
Typical Performance Characteristics ........................................... 13
Equivalent Circuits ......................................................................... 14
System Overview ............................................................................ 15
High Speed Precision Timing Core........................................... 16
Horizontal Clamping and Blanking......................................... 20
Horizontal Timing Sequence Example.................................... 26
Vertical Timing Generation ...................................................... 28
Manual Shutter Operation Using Enhanced SYNC Modes .... 66
Analog Front-End Description and Operation...................... 70
Power-Up Sequence for Master Mode..................................... 72
Standby Mode Operation .......................................................... 76
CLI Frequency Change.............................................................. 76
Circuit Layout Information........................................................... 78
Serial Interface Timing .............................................................. 82
Layout of Internal Registers ...................................................... 83
Updating New Register Values ................................................. 84
Complete Register Listing ............................................................. 85
Outline Dimensions ....................................................................... 99
Ordering Guide .......................................................................... 99
Vertical Sequences (VSEQ) ....................................................... 31
REVISION HISTORY
1/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 100
AD9927
SPECIFICATIONS
Table 1.
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE INPUTS
AVDD (AFE Analog Supply)
TCVDD (Timing Core Supply)
CLIVDD (CLI Input Supply)
RGVDD (RG, HL Driver)
HVDD (H1 to H8 Drivers)
DVDD (Digital Logic)
DRVDD (Parallel Data Output Drivers)
IOVDD (Digital I/O)
XVVDD (Vertical Output Drivers)
CP1P8 (CP Supply Input)
LDOIN (LDO Supply Input)
V-DRIVER POWER SUPPLY VOLTAGES
VDD1, VDD2 (V-Driver Logic)
VH1, VH2 (V-Driver High Supply)
VL1, VL2 (V-Driver Low Supply)
VM1, VM2 (V-Driver Mid Supply)
VLL (SUBCK Low Supply)
VMM (SUBCK Mid Supply)
POWER SUPPLY CURRENTS—40 MHz OPERATION
AVDD (1.8 V)
TCVDD (1.8 V)
CLIVDD (3 V)
RGVDD (3.3 V, 20 pF RG Load, 20 pF HL Load)
HVDD 1 (3.3 V, 480 pF Total Load on H1 to H8)
DVDD (1.8 V)
DRVDD (3 V, 10 pF Load on Each DOUT Pin)
IOVDD (3 V, Depends on Load and Output Frequency of Digital I/O)
XVVDD (3 V, Depends on Load and Output Frequency of XV Signals)
POWER SUPPLY CURRENTS—STANDBY MODE OPERATION
Standby1 Mode
Standby2 Mode
Standby3 Mode
MAXIMUM CLOCK RATE (CLI)
1
Min
Typ
−25
−65
Unit
+85
+150
°C
°C
1.6
1.6
1.6
2.7
2.7
1.6
1.6
2.7
2.7
1.6
2.25
1.8
1.8
3.0
3.0
3.0
1.8
3.0
3.0
3.0
1.8
3.0
2.0
2.0
3.6
3.6
3.6
2.0
3.6
3.6
3.6
2.0
3.6
V
V
V
V
V
V
V
V
V
V
V
2.7
11.5
−8.5
−1.5
−8.5
−4.0
3.0
15.0
−7.5
0.0
−7.5
0.0
3.6
16.5
−5.5
+1.5
−5.5
+0.3
V
V
V
V
V
V
27
5
1.5
10
59
9.5
6
2
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
12
5
1.5
mA
mA
mA
MHz
40
The total power dissipated by the HVDD (or RGVDD) supply can be approximated using the equation
Total HVDD Power = [CL × HVDD × Pixel Frequency] × HVDD
Reducing the capacitive load and/or reducing the HVDD supply reduces the power dissipation. CL is the total capacitance seen by all H-outputs.
Rev. 0 | Page 3 of 100
Max
AD9927
DIGITAL SPECIFICATIONS
IOVDD = 1.6 V to 3.6 V, RGVDD = HVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
LOGIC INPUTS (IOVDD)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS (IOVDD, XVDD, DRVDD)
High Level Output Voltage @ IOH = 2 mA
Low Level Output Voltage @ IOL = 2 mA
RG and H-DRIVER OUTPUTS (HVDD, RGVDD)
High Level Output Voltage @ Maximum Current
Low Level Output Voltage @ Maximum Current
Maximum Output Current (Programmable)
Maximum Load Capacitance (for Each Output)
Symbol
Min
VIH
VIL
IIH
IIL
CIN
VDD − 0.6
VOH
VOL
VDD − 0.5
VOH
VOL
VDD − 0.5
Max
0.6
10
10
10
0.5
0.5
18
60
Rev. 0 | Page 4 of 100
Typ
Unit
V
V
μA
μA
pF
V
V
V
V
mA
pF
AD9927
ANALOG SPECIFICATIONS
AVDD = 1.8 V, fCLI = 40 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CDS 1
Allowable CCD Reset Transient
CDS Gain Accuracy
−3.0 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
+6 dB CDS Gain
Maximum Input Range Before Saturation
−3 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
+6 dB CDS Gain
Allowable OB Pixel Amplitude1
0 dB CDS Gain (Default)
+6 dB CDS Gain
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
Low Gain (VGA Code 15, Default)
Maximum Gain (VGA Code 1023)
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Minimum Clamp Level (Code 0)
Maximum Clamp Level (Code 1023)
ADC
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Integral Nonlinearity (INL)
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
SYSTEM PERFORMANCE
Gain Accuracy
Low Gain (VGA Code 15)
Maximum Gain (VGA Code 1023)
Peak Nonlinearity, 1.0 V Input Signal
Total Output Noise
Power Supply Rejection (PSR)
Typ
Max
Unit
0.5
1.2
V
−2.8
0
2.9
5.5
−2.3
+0.5
3.4
6.0
dB
dB
dB
dB
VGA gain = 6.3 dB (Code 15, default value)
1.4
1.0
0.7
0.5
−100
−50
V p-p
V p-p
V p-p
V p-p
+200
+100
1024
Guaranteed
1V MAX
INPUT SIGNAL RANGE
(0dB CDS GAIN)
mV
mV
Steps
6.3
42.4
dB
dB
1024
Steps
0
255
LSB
LSB
Measured at ADC output
14
−1.0
±0.5
Guaranteed
4
16
2.0
1.4
0.4
5.8
41.9
6.3
42.4
0.1
0.5
50
Bits
LSB
LSB
V
V
V
6.8
42.9
0.3
Input signal characteristics defined as follows:
500mV TYP
RESET TRANSIENT
200mV MAX
OPTICAL BLACK PIXEL
Notes
VGA gain = 6.3 dB (Code 15, default value)
−3.3
−0.5
2.4
5.0
05892-002
1
Min
Rev. 0 | Page 5 of 100
dB
dB
%
LSB rms
dB
Includes entire signal chain
0 dB CDS gain
Gain = (0.0358 × Code) + 5.76 dB
6 dB VGA gain, 0 dB CDS gain applied
AC-grounded input, 6 dB VGA gain applied
Measured with step change on supply
AD9927
TIMING SPECIFICATIONS
CL = 20 pF, AVDD = DVDD = TCVDD = 1.8 V, DRVDD = 3.0 V, fCLI = 40 MHz, unless otherwise noted.
Table 4.
Parameter
MASTER CLOCK (See Figure 16)
CLI Clock Period
CLI High/Low Pulse Width
Delay from CLI Rising Edge to Internal Pixel Position 0
VD FALLING EDGE TO HD FALLING EDGE IN SLAVE MODE (See Figure 89)
AFE CLPOB PULSE WIDTH (See Figure 23 and Figure 33) 1, 2
AFE SAMPLE LOCATION (See Figure 17 and Figure 20)1
SHP Sample Edge to SHD Sample Edge
DATA OUTPUTS (See Figure 21 and Figure 22)
Output Delay from DCLK Rising Edge
Inhibited Area for DOUTPHASE Edge Location
Pipeline Delay from SHP/SHD Sampling to DOUT
SERIAL INTERFACE (See Figure 97)
Maximum SCK Frequency (Must Not Exceed CLI Frequency)
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
1
2
Symbol
Min
tCONV
25
10
Typ
Max
12.5
6
15
Unit
0
2
20
ns
ns
ns
ns
Pixels
tS1
11
12.5
ns
tOD
tDOUTINH
SHDLOC + 1
tCLIDLY
tVDHD
VD period − 5 × tCONV
1
SHDLOC + 15
16
fSCLK
tLS
tLH
tDS
tDH
40
10
10
10
10
Parameter is programmable.
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
Rev. 0 | Page 6 of 100
ns
Edge
location
Cycles
MHz
ns
ns
ns
ns
AD9927
VERTICAL DRIVER SPECIFICATIONS
VH1, VH2 = 15 V. VM1, VM2, VMM = 0 V. VL1, VL2, VLL = −7.5 V. CL shown in load model, 25°C.
Table 5.
Parameter
V-DRIVER OUTPUTS (SIMPLIFIED LOAD CONDITIONS, 3000 pF to GROUND)
Delay Time, VL to VM and VM to VH
Delay Time, VM to VL and VH to VM
Rise Time, VL to VM
Rise Time, VM to VH
Fall Time, VM to VL
Fall Time, VH to VM
Output Currents
@ −7.25 V
@ −0.25 V
@ +0.25 V
@ +14.75 V
RON
SUBCK OUTPUT (SIMPLIFIED LOAD CONDITIONS, 1000 pF to GROUND)
Delay Time, VLL to VH
Delay Time, VH to VLL
Delay Time, VLL to VMM
Delay Time, VMM to VH
Delay Time, VH to VMM
Delay Time, VMM to VLL
Rise Time, VLL to VH
Rise Time, VLL to VMM
Rise Time, VMM to VH
Fall Time, VH to VLL
Fall Time, VH to VMM
Fall Time, VMM to VLL
Output Currents
@ −7.25 V
@ −0.25 V
@ +0.25 V
@ +14.75 V
RON
50%
tPLM, tPMH
tPML, tPHM
tRLM
tRMH
tFML
tFHM
tPLH
tPHL
tPLM
tPMH
tPHM
tPML
tRLH
tRLM
tRMH
tFHL
tFHM
tFML
10%
tPML, tPHM, tPHL
90%
tPLM, tPMH, tPLH
10%
tFML, tFHM, tFHL
Figure 2. Definition of V-Driver Timing Specifications
Rev. 0 | Page 7 of 100
Max
Unit
35
35
125
260
220
125
ns
ns
ns
ns
ns
ns
10
−22
22
−10
mA
mA
mA
mA
Ω
25
30
25
25
30
25
40
45
30
40
90
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
−12
12
−20
mA
mA
mA
mA
Ω
35
50%
90%
Typ
35
tRLM, tRMH, tRLH
V-DRIVER
OUTPUT
Min
05892-114
V-DRIVER
INPUT
Symbol
AD9927
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
AVDD
TCVDD
HVDD1, HVDD2
RGVDD
DVDD
DRVDD
IOVDD
XVVDD
CLIVDD
LDOIN
CP1P8
VH1, VH2
VH1, VH2
VL1, VL2
VM1, VM2
VLL
VMM
V5V
V1A to V15
RG Output
H1 to H8, HL Output
Digital Outputs
Digital Inputs
SCK, SL, SDATA
REFT, REFB, CCDIN
Junction Temperature
Lead Temperature,
10 sec
With
Respect To
AVSS
TCVSS
HVSS1,
HVSS2
RGVSS
DVSS
DRVSS
IOVSS
DVSS
TCVSS
LDOVSS
CPVSS
VL1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
RGVSS
HVSS
DVSS
DVSS
DVSS
AVSS
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +2.0 V
−0.3 V to +25.0 V
−0.3 V to +17.0 V
−17.0 V to +0.3 V
−6.0 V to +0.3 V
−17.0 V to +0.3 V
−6.0 V to +0.3 V
−0.3 V to +6.0 V
VL − 0.3 V to VH + 0.3 V
−0.3 V to RGVDD + 0.3 V
−0.3 V to HVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
150°C
350°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
CSP_BGA package: θJA = 40.3°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 8 of 100
AD9927
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
BOTTOM VIEW
(Not to Scale)
05892-115
M
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
L7
L8
B11
C10
A2
A1
M6
L6
L5
K12
J12
H12
C4
M2
C5
L3
C3
K3
G10
D11
K5
J5
H9
C11
D1
C2
B1
E2
E11
H1
G2
L1
K2
M4
L4
E10
Mnemonic
AVDD
AVSS
DVDD
DVSS
DRVDD
DRVSS
TCVSS
TCVDD
CLIVDD
IOVDD
IOVSS
XVVDD
VL1
VL2
VH1
VH2
VM1
VM2
VSS1
VSS2
VLL
VMM
VDD1
VDD2
CP1P8
CPVSS
CP3P3
LDOIN
LDOVSS
HVDD1
HVSS1
HVDD2
HVSS2
RGVDD
RGVSS
V5V
Type 1
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Description
AFE Supply: 1.8 V
Analog Supply Ground
Digital Logic Supply: 1.8 V
Digital Logic Ground
Data Driver Supply: 1.8 V, 3.3 V
Data Driver Ground
Analog Ground for Timing Core
Timing Core Supply: 1.8 V
CLI Input Supply: 3.3 V
Digital I/O Supply: 1.8 V, 3.3 V (GPIO, SUBCK, HD/VD, SL, SCK, SDATA, SYNC, RSTB)
Digital I/O Ground
XV Output Supply: 1.8 V, 3.3 V
V-Driver Low Supply
V-Driver Low Supply
V-Driver High Supply
V-Driver High Supply
V-Driver Mid Supply
V-Driver Mid Supply
V-Driver Ground
V-Driver Ground
V-Driver Low Supply for SUBCK Output
V-Driver Mid Supply for SUBCK Output
V-Driver Logic Supply (3 V)
V-Driver Logic Supply (3 V)
Charge Pump 1.8 V Input
Charge Pump Ground
Charge Pump 3.3 V Output
LDO 3.3 V Input
LDO Ground
H-Driver Supply 1: 3.3 V
H-Driver Ground 1
H-Driver Supply 2: 3.3 V
H-Driver Ground 2
RG Driver Supply: 3.3 V
RG Driver Ground
Connect to 3 V supply through diode
Rev. 0 | Page 9 of 100
AD9927
Pin No.
M7
E1
F1
B2
C1
M8
M9
K7
L9
M10
M11
D2
F9
F10
G11
F11
H10
H11
J11
M12
L10
L11
K9
L12
K10
K11
J10
K6
F2
G1
H2
J1
J2
K1
L2
M1
M3
M5
A10
B9
A9
B8
A8
B7
A7
B6
A6
B5
A5
B4
A4
B3
Mnemonic
CCDIN
SENSE
LDOOUT
CPFCT
CPFCB
REFT
REFB
CLI
SL
SDATA
SCK
CPCLI
LDO3P2EN
LDO1P8EN
SYNC
RSTB
XSUBCNT
VD
HD
GPO8
GPO7
GPO6
GPO5
GPO4
GPO3
GPO2
GPO1
CLO
H1
H2
H3
H4
H5
H6
H7
H8
HL
RG
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
Type 1
AI
AI
AO
AO
AO
AO
AO
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
Description
CCD Signal Input
LDO Output Sense Pin
LDO Output Voltage
Charge Pump Flying Capacitor Top
Charge Pump Flying Capacitor Bottom
Voltage Reference Top Bypass
Voltage Reference Bottom Bypass
Reference Clock Input
3-Wire Serial Load Pulse. Internal pull-up resistor.
3-Wire Serial Data Input
3-Wire Serial Clock
Charge Pump Clock Input
LDO 3.2 V Output Enable
LDO 1.8 V Output Enable
External System Sync Input
External Reset Input (active low pulse to reset). Internal pull-up resistor.
Generates 3-Level Output for SUBCK. Connect high if 3-Level SUBCK not used.
Vertical Sync Pulse (input for slave mode, output for master mode)
Horizontal Sync Pulse (input for slave mode, output for master mode)
General-Purpose Output 8
General-Purpose Output 7
General-Purpose Output 6
General-Purpose Output 5
General-Purpose Output 4
General-Purpose Output 3
General-Purpose Output 2
General-Purpose Output 1
Clock Output for Crystal
CCD Horizontal Clock 1
CCD Horizontal Clock 2
CCD Horizontal Clock 3
CCD Horizontal Clock 4
CCD Horizontal Clock 5
CCD Horizontal Clock 6
CCD Horizontal Clock 7
CCD Horizontal Clock 8
CCD Last Horizontal Clock
CCD Reset Gate Clock
Data Output 0 (LSB).
Data Output 1.
Data Output 2.
Data Output 3.
Data Output 4.
Data Output 5.
Data Output 6.
Data Output 7.
Data Output 8.
Data Output 9.
Data Output 10.
Data Output 11.
Data Output 12.
Data Output 13 (MSB).
Rev. 0 | Page 10 of 100
AD9927
Pin No.
A3
K4
J3
J4
H3
H4
G4
G3
F3
F4
E4
E3
D4
D3
D5
D6
D7
C7
C8
D8
J8
J7
K8
D10
J6
G9
J9
A11, A12,
B10, B12,
C6, C9, C12,
D9, D12, E9,
E12, F12,
G12
1
Mnemonic
DCLK
SUBCK
V1A
V1B
V2A
V2B
V3A
V3B
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
NC
Type 1
DO
VO3
VO3
VO3
VO3
VO3
VO3
VO3
VO3
VO3
VO3
VO2
VO2
VO2
VO2
VO2
VO2
VO2
VO2
VO2
AO
AO
DI
DI
AI
AI
DI
Description
Data Clock Output.
CCD Substrate Clock
CCD Vertical Transfer Clock. 3-Level Output (XV1 + XV16)
CCD Vertical Transfer Clock. 3-Level Output (XV1 + XV17)
CCD Vertical Transfer Clock. 3-Level Output (XV2 + XV18)
CCD Vertical Transfer Clock. 3-Level Output (XV2 + XV19)
CCD Vertical Transfer Clock. 3-Level Output (XV3 + XV20)
CCD Vertical Transfer Clock. 3-Level Output (XV3 + XV21)
CCD Vertical Transfer Clock. 3-Level Output (XV4 + XV22)
CCD Vertical Transfer Clock. 3-Level Output (XV5 + XV23)
CCD Vertical Transfer Clock. 3-Level Output (XV6 + XV24)
CCD Vertical Transfer Clock. 2-Level Output (XV7)
CCD Vertical Transfer Clock. 2-Level Output (XV8)
CCD Vertical Transfer Clock. 2-Level Output (XV9)
CCD Vertical Transfer Clock. 2-Level Output (XV10)
CCD Vertical Transfer Clock. 2-Level Output (XV11)
CCD Vertical Transfer Clock. 2-Level Output (XV12)
CCD Vertical Transfer Clock. 2-Level Output (XV13)
CCD Vertical Transfer Clock. 2-Level Output (XV14)
CCD Vertical Transfer Clock. 2-Level Output (XV15)
Do Not Connect
Do Not Connect
Connect to 1.8 V/3 V Supply
Connect to Ground
Connect to Ground
Connect to Ground
Connect to Ground
Not Internally Connected
AI = analog input, AO = analog output, DI = digital input, DO = digital output, DIO = digital input/output, P = power, VO2 = vertical driver output 2-level, VO3 = vertical
driver output 3-level.
Rev. 0 | Page 11 of 100
AD9927
TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Therefore, every
code must have a finite width. No missing codes guaranteed to
14-bit resolution indicates that all 16,384 codes, each for its
respective input, must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9927 from a true straight
line. The point used as zero scale occurs 0.5 LSB before the first
code transition. Positive full scale is defined as a level 1 LSB and
0.5 LSB beyond the last code transition. The deviation is measured
from the middle of each particular output code to the true straight
line. The error is then expressed as a percentage of the 2 V ADC
full-scale signal. The input signal is always appropriately gained
up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage using the relationship
1 LSB = (ADC Full Scale/2n Codes)
where n is the bit resolution of the ADC. For the AD9927,
1 LSB is 0.122 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
Rev. 0 | Page 12 of 100
AD9927
TYPICAL PERFORMANCE CHARACTERISTICS
500
150
+3dB CDS
450
400
POWER (mW)
RMS OUTPUT NOISE (LSB)
3.3V/1.8V
350
3.0V/1.8V
300
250
2.7V/1.8V
200
150
100
0dB CDS
–3dB CDS
100
50
20
25
30
FREQUENCY (MHz)
35
40
0
05892-004
0
15
0
Figure 4. AFETG Power vs. Frequency (V-Driver not Included)
(AVDD = TCVDD = DVDD = 1.8 V, All Other Supplies at 2.7 V, 3.0 V, or 3.3 V)
2
0.8
1
0.6
15
20
25
30
CDS + VGA GAIN (dB)
35
40
45
0
0.4
–1
INL (LSB)
0.2
0
–0.2
–2
–3
–0.6
–5
–0.8
–6
0
2k
4k
6k
8k
10k
ADC OUTPUT CODE
12k
14k
16k
Figure 5. Typical Differential Nonlinearity (DNL) Performance
–7
0
2k
4k
6k
8k
10k
ADC OUTPUT CODE
12k
14k
Figure 7. Typical System Nonlinearity Performance
Rev. 0 | Page 13 of 100
16k
05892-117
–4
–0.4
05892-116
DNL (LSB)
10
Figure 6. Output Noise vs. Total Gain (CDS + VGA)
1.0
–1.0
5
05892-006
50
AD9927
EQUIVALENT CIRCUITS
IOVDD
AVDD
330Ω
AVSS
IOVSS
Figure 10. Digital Inputs
Figure 8. CCDIN
DVDD
05892-010
AVSS
05892-008
R
HVDD OR
RGVDD
DRVDD
RG, H1 TO H8
DATA
DRVSS
05892-009
DVSS
OUTPUT
THREE-STATE
DOUT
05892-011
THREESTATE
HVSS OR
RGVSS
Figure 11. H1 to H8, HL, RG Drivers
Figure 9. Digital Data Outputs
VH
INTERNAL
REFERENCE
VOLTAGE
05892-119
V5V
Figure 12. V5V
Rev. 0 | Page 14 of 100
AD9927
SYSTEM OVERVIEW
Figure 13 shows the typical system block diagram for the AD9927
in master mode. The CCD output is processed by the AD9927’s
AFE circuitry, which consists of a CDS, VGA, black level clamp,
and ADC. The digitized pixel information is sent to the digital
image processor chip, which performs the postprocessing and
compression. To operate the CCD, all CCD timing parameters
are programmed into the AD9927 from the system microprocessor
through the 3-wire serial interface. From the master clock, CLI,
provided by the image processor or external crystal, the AD9927
generates the CCD’s horizontal and vertical clocks and internal
AFE clocks. External synchronization is provided by a sync
pulse from the microprocessor, which resets the internal
counters and resyncs the VD and HD outputs.
V1A TO V15, SUBCK
DOUT
CCDIN
GPO1 TO GPO8
AD9927
DCLK
AFETG
V-DRIVER
HD, VD
DIGITAL
IMAGE
PROCESSING
ASIC
CLI
The H-drivers for H1 to H8, HL, and RG are included in the
AD9927, allowing these clocks to be directly connected to the
CCD. An H-driver voltage of up to 3.3 V is supported. V1A to
V15 and SUBCK vertical clocks are included as well, allowing
the AD9927 to provide all horizontal and vertical clocks
necessary to clock data out of a CCD.
The AD9927 includes programmable general-purpose outputs
(GPO), which can trigger mechanical shutter and strobe (flash)
circuitry.
Figure 14 and Figure 15 show the maximum horizontal and vertical
counter dimensions for the AD9927. All internal horizontal and
vertical clocking is controlled by these counters, which specify
line and pixel locations. Maximum HD length is 8192 pixels per
line, and maximum VD length is 8192 lines per field.
H1 TO H8, HL,
RG, VSUB
CCD
Alternatively, the AD9927 can be operated in slave mode. In
this mode, the VD and HD are provided externally from the
image processor, and all AD9927 timing is synchronized with
VD and HD.
MAXIMUM COUNTER DIMENSIONS
SERIAL
INTERFACE
µP
05892-120
SYNC
13-BIT HORIZONTAL = 8192 PIXELS MAX
Figure 13. Typical System Block Diagram, Master Mode
05892-013
13-BIT VERTICAL = 8192 LINES MAX
Figure 14. Vertical and Horizontal Counters
MAX VD LENGTH IS 8192 LINES
VD
MAX HD LENGTH IS 8192 PIXELS
HD
05892-014
CLI
Figure 15. Maximum VD/HD Dimensions
Rev. 0 | Page 15 of 100
AD9927
clock by programming the CLIDIVIDE register (AFE Register
Address 0x0D). The AD9927 then internally divides the CLI
frequency by 2.
HIGH SPEED PRECISION TIMING CORE
The AD9927 generates high speed timing signals using the
flexible Precision Timing core. This core is the foundation for
generating the timing used for both the CCD and the AFE; it
includes the reset gate RG, horizontal drivers H1 to H8, HL,
and SHP/SHD sample clocks. A unique architecture makes it
routine for the system designer to optimize image quality by
providing precise control over the horizontal CCD readout
and the AFE correlated double sampling.
The AD9927 includes a master clock output, CLO, which
is the inverse of CLI. This output should be used as a crystal
driver. A crystal can be placed between the CLI and CLO pins
to generate the master clock for the AD9927.
High Speed Clock Programmability
Figure 17 shows when the high speed clocks RG, H1 to H8,
SHP, and SHD are generated. The RG pulse has programmable
rising and falling edges and can be inverted using the polarity
control. Horizontal Clock H1 has programmable rising and
falling edges and polarity control. In HCLK Mode 1, H3, H5,
and H7 are equal to H1 and H2, H4, H6, and H8 are always
inverses of H1.
The high speed timing of the AD9927 operates the same
way in either master or slave mode configuration. For more
information on synchronization and pipeline delays, see
the Power-Up Sequence for Master Mode section.
Timing Resolution
The Precision Timing core uses a 1× master clock input as a
reference (CLI). This clock should be the same as the CCD pixel
clock frequency. Figure 16 illustrates how the internal timing
core divides the master clock period into 64 steps or edge
positions. Using a 40 MHz CLI frequency, the edge resolution
of the Precision Timing core is approximately 0.4 ns. If a 1×
system clock is not available, it is possible to use a 2× reference
POSITION
P[0]
P[16]
The edge location registers are each six bits wide, allowing the
selection of all 64 edge locations. Figure 20 shows the default
timing locations for all of the high speed clock signals.
P[32]
P[48]
P[64] = P[0]
CLI
tCLIDLY
ONE PIXEL
PERIOD
05892-015
NOTES
1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (tCLIDLY).
Figure 16. High Speed Clock Resolution from CLI, Master Clock Input
1
CCD
SIGNAL
2
3
4
RG
5
6
7
8
H1, H3, H5, H7
H2, H4, H6, H8
HL
05892-016
PROGRAMMABLE CLOCK POSITIONS:
1SHP SAMPLE LOCATION.
2SHD SAMPLE LOCATION.
3RG RISING EDGE.
4RG FALLING EDGE.
5H1 RISING EDGE.
6H1 FALLING EDGE.
7HL RISING EDGE.
8HL FALLING EDGE.
Figure 17. High Speed Clock Programmable Locations (HCLKMODE = 001)
Rev. 0 | Page 16 of 100
AD9927
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9927
features on-chip output drivers for the RG, HL, and H1 to H8
outputs. These drivers are powerful enough to drive the CCD
inputs directly. The H-driver and RG current can be adjusted
for optimum rise/fall time for a particular load by using the
drive strength control registers (Addresses 0x35 and 0x36).
The 3-bit drive setting for each output is adjustable in 4.3 mA
increments: 0 = three-state; 1 = 4.3 mA; 2 = 8.6 mA; 3 =
12.9 mA; and 4, 5, 6, 7 = 17.2 mA.
As shown in Figure 17, when HCLK Mode 1 is used, the H2,
H4, H6, and H8 outputs are inverses of the H1, H3, H5, and H7
outputs, respectively. Using the HCLKMODE register (Address
0x23, Bits [9:7]), it is possible to select a different configuration.
Table 9 shows a comparison of the different programmable
settings for each HCLK mode. Figure 18 and Figure 19 show the
settings for HCLK Mode 2 and HCLK Mode 3, respectively.
Note that it is recommended that all H1 to H8 outputs on the
AD9927 be used together for maximum flexibility in drive
strength settings. A typical CCD with H1 and H2 inputs should
only have the AD9927’s H1, H3, H5, and H7 outputs connected
together to drive the CCD’s H1, and the H2, H4, H6, and H8
outputs connected together to drive the CCD’s H2. Similarly, a
CCD with H1, H2, H3, and H4 inputs should have
• H1 and H3 connected to the CCD’s H1.
• H2 and H4 connected to the CCD’s H2.
• H5 and H7 connected to the CCD’s H3.
• H6 and H8 connected to the CCD’s H4.
Table 8. Timing Core Register Parameters for H1, H2, HL, RG, SHP, SHD
Parameter
Polarity
Positive Edge
Negative Edge
Sampling Location
Drive Strength
Length
1b
6b
6b
6b
3b
Range
High/low
0 to 63 edge location
0 to 63 edge location
0 to 63 edge location
0 to 4 current steps
Description
Polarity control for H1, H2, HL, and RG (0 = inversion, 1 = no inversion)
Positive edge location for H1, H2, HL, and RG
Negative edge location for H1, H2, HL, and RG
Sampling location for internal SHP and SHD signals
Drive current for H1 to H8 , HL, and RG outputs (4.3 mA per step)
Table 9. HCLK Modes, Selected by Address 0x23, Bits [9:7]
HCLKMODE
Mode 1
Mode 2
Register Value
001
010
Mode 3
100
Invalid Selection
000, 011, 101, 110, 111
1
Description
H1 edges are programmable, with H3 = H5 = H7 = H1, H2 = H4 = H6 = H8 = inverse of H1
H1 edges are programmable, with H3 = H5 = H7 = H1
H2 edges are programmable, with H4 = H6 = H8 = H2
H1 edges are programmable, with H3 = H1 and H2 = H4 = inverse of H1
H5 edges are programmable, with H7 = H5 and H6 = H8 = inverse of H5
Invalid register settings
2
H1, H3, H5, H7
4
3
H1 TO H8 PROGRAMMABLE LOCATIONS:
1H1 RISING EDGE.
2H1 FALLING EDGE.
3H2 RISING EDGE.
4H2 FALLING EDGE.
Figure 18. HCLK Mode 2 Operation
Rev. 0 | Page 17 of 100
05892-017
H2, H4, H6, H8
AD9927
1
2
H1, H3
H2, H4
3
4
H5, H7
H6, H8
05892-018
H1 TO H8 PROGRAMMABLE EDGES:
1H1 RISING EDGE.
2H1 FALLING EDGE.
3H5 RISING EDGE.
4H5 FALLING EDGE.
Figure 19. HCLK Mode 3 Operation
POSITION
P[0]
P[16]
RGr[0]
RGf[16]
P[32]
P[48]
P[64] = P[0]
PIXEL
PERIOD
RG
HLr[0]
HLf[32]
H1r[0]
H1f[32]
HL
H1, H3, H5, H7
H2, H4, H6, H8
SHP[32]
CCD
SIGNAL
tS1
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.
2. CONNECT H1, H3, H5, AND H7 TOGETHER AND H2, H4, H6, AND H8 TOGETHER FOR MAXIMUM DRIVE STRENGTH.
05892-019
SHD[0]
Figure 20. High Speed Timing Default Locations
Digital Data Outputs
The AD9927 data output and DCLK phase are programmable
using the DOUTPHASE registers (Address 0x38, Bits [11:0]).
DOUTPHASEP (Bits [5:0]) selects any edge location from 0 to
63, as shown in Figure 21. DOUTPHASEN (Bits [11:6]) does
not actually program the phase of the data outputs but is used
internally and should always be programmed to a value of
DOUTPHASEP plus 32 edges. For example, if DOUTPHASEP
is set to 0, DOUTPHASEN should be set to 32 (0x20).
Normally, the DOUT and DCLK signals track in phase, based
on the contents of the DOUTPHASE registers. The DCLK output
phase can also be held fixed with respect to the data outputs by
changing the DCLKMODE register high (Address 0x38, Bit [12]).
In this mode, the DCLK output remains at a fixed phase equal
to a delayed version of CLI while the data output phase is still
programmable.
The pipeline delay through the AD9927 is shown in Figure 22.
After the CCD input is sampled by SHD, there is a 16-cycle
delay until the data is available.
Rev. 0 | Page 18 of 100
AD9927
P[0]
P[16]
P[48]
P[32]
P[64] = P[0]
PIXEL
PERIOD
DCLK
tOD
DOUT
05892-020
NOTES
1. DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 64 DIFFERENT LOCATIONS.
3. DCLK CAN BE INVERTED WITH RESPECT TO DOUT BY USING THE DCLKINV REGISTER.
Figure 21. Digital Output Phase Adjustment Using DOUTPHASEP Register
CLI
tCLIDLY
N
N+1
N+2
N+3
N+4
N – 14
N – 13
N+5
N+6
N+7
N – 11
N – 10
N+8
N+9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
N + 16
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N + 17
CCDIN
SAMPLE PIXEL N
SHD
(INTERNAL)
ADC DOUT
(INTERNAL)
N – 17
N – 16
N – 15
N – 12
N–9
N–8
N
N+1
tDOUTINH
DCLK
PIPELINE LATENCY = 16 CYCLES
N – 16
N – 15
N – 14
N – 13
N – 12
N – 11
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
NOTES
1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0.
2. HIGHER VALUES OF SHD AND/OR DOUT PHASE SHIFTS DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
3. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE SHPLOC OR UP TO 15 EDGES FOLLOWING SHPLOC.
Figure 22. Digital Data Output Pipeline Delay
Rev. 0 | Page 19 of 100
N–3
N–2
N–1
N
N+1
05892-021
DOUT
N – 17
AD9927
HORIZONTAL CLAMPING AND BLANKING
CLPOB and PBLK Masking Areas
The AD9927’s horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. Individual
control is provided for CLPOB, PBLK, and HBLK in the
different regions of each field. This allows the dark pixel
clamping and blanking patterns to be changed at each stage of
the readout in order to accommodate different image transfer
timing and high speed line shifts.
Additionally, the AD9927 allows the CLPOB and PBLK signals to
be disabled in certain lines in the field without changing any of
the existing CLPOB pattern settings.
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 23. These two signals are programmed
independently using the registers in Table 10. The start polarity
for the CLPOB (and PBLK) signal is CLPOBPOL (PBLKPOL),
and the first and second toggle positions of the pulse are
CLPOBTOG1 (PBLKTOG1) and CLPOBTOG2 (PBLKTOG2).
Both signals are active low and should be programmed
accordingly.
A separate pattern for CLPOB and PBLK can be programmed
for each vertical sequence. As described in the Vertical Timing
Generation section, several V-sequences can be created, each
containing a unique pulse pattern for CLPOB and PBLK. Figure 49
shows how the sequence change positions divide the readout field
into different regions. By assigning a different V-sequence to
each region, the CLPOB and PBLK signals can change with
each change in the vertical timing.
To use CLPOB (or PBLK) masking, the CLPMASKSTART
(PBLKMASKSTART) and CLPMASKEND (PBLKMASKEND)
registers are programmed to specify the start and end lines in
the field where the CLPOB (PBLK) patterns are ignored. The
three sets of start and end registers allow up to three CLPOB
(PBLK) masking areas to be created.
The CLPOB and PBLK masking registers are not specific to a
certain V-sequence; they are always active for any existing field
of timing. During operation, to disable the CLPOB masking
feature, these registers must be set to the maximum value of
0x1FFF or a value greater than the programmed VD length.
Note that to disable CLPOB (and PBLK) masking during power-up,
it is recommended to set CLPMASKSTART (PBLKMASKSTART)
to 8191 and CLPMASKEND (PBLKMASKEND) to 0. This
prevents any accidental masking caused by register update events.
Table 10. CLPOB and PBLK Pattern Registers
Register
CLPOBPOL
PBLKPOL
CLPOBTOG1
CLPOBTOG2
PBLKTOG1
PBLKBTOG2
CLPMASKSTART
CLPMASKEND
PBLKMASKSTART
PBLKMASKEND
Length
1b
1b
13b
13b
13b
13b
13b
13b
13b
13b
Range
High/low
High/low
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 line location
0 to 8191 line location
0 to 8191 line location
0 to 8191 line location
Description
Starting polarity of CLPOB for each V-sequence.
Starting polarity of PBLK for each V-sequence.
First CLPOB toggle position within line for each V-sequence.
Second CLPOB toggle position within line for each V-sequence.
First PBLK toggle position within line for each V-sequence.
Second PBLK toggle position within line for each V-sequence.
CLPOB masking area—starting line within field (maximum of three areas).
CLPOB masking area—ending line within field (maximum of three areas).
PBLK masking area—starting line within field (maximum of three areas).
PBLK masking area—ending line within field (maximum of three areas).
Rev. 0 | Page 20 of 100
AD9927
HD
2
CLPOB 1
PBLK
3
ACTIVE
ACTIVE
05892-022
PROGRAMMABLE SETTINGS:
1START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW).
2FIRST TOGGLE POSITION.
3SECOND TOGGLE POSITION.
Figure 23. Clamp and Preblank Pulse Placement
NO CLPOB SIGNAL
FOR LINES 6 TO 8
VD
0
1
NO CLPOB SIGNAL
FOR LINE 600
2
597 598
HD
CLPMASKSTART1 = 6
CLPMASKEND1 = 8
CLPMASKSTART2 = CLPMASKEND2 = 600
Figure 24. CLPOB Masking Example
Rev. 0 | Page 21 of 100
05892-023
CLPOB
AD9927
operation. HBLK Mode 2 supports advanced HBLK operation.
The following sections describe each mode in detail. Register
parameters are described in detail in Table 11.
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 25 is similar
to CLPOB and PBLK; however, there is no start polarity control.
Only the toggle positions are used to designate the start and
stop positions of the blanking period. Additionally, there are
separate masking polarity controls for H1, H2, and HL that
designate the polarity of the horizontal clock signals during the
blanking period. Setting HBLKMASK_H1 high sets H1, and
therefore H3, H5, and H7, low during the blanking, as shown in
Figure 26. As with the CLPOB and PBLK signals, HBLK
registers are available in each V-sequence, allowing different
blanking signals to be used with different vertical timing
sequences.
HBLK Mode 0 Operation
There are six toggle positions available for HBLK. Normally,
only two of the toggle positions are used to generate the
standard HBLK interval. However, the additional toggle
positions can be used to generate special HBLK patterns, as
shown in Figure 27. The pattern in this example uses all six
toggle positions to generate two extra groups of pulses during
the HBLK interval. By changing the toggle positions, different
patterns can be created.
Separate toggle positions are available for even and odd lines. If
alternation is not needed, the same values should be loaded into
the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.
The AD9927 supports three modes of HBLK operation. HBLK
Mode 0 supports basic operation and some support for special
HBLK patterns. HBLK Mode 1 supports pixel mixing HBLK
HD
HBLKTOGE2
BLANK
HBLK
BLANK
05892-024
HBLKTOGE1
BASIC HBLK PULSE IS GENERATED USING HBLKTOGE1 AND HBLKTOGE2 REGISTERS (HBLKALT = 0)
Figure 25. Typical Horizontal Blanking Pulse Placement (HBLKMODE = 0)
HD
HBLK
H1/H3/H5/H7
THE POLARITY OF H1/H3/H5/H7 DURING BLANKING IS PROGRAMMABLE
(H2/H4/H6/H8 AND HL ARE SEPARATELY PROGRAMMABLE)
05892-025
H1/H3/H5/H7
H2/H4/H6/H8
Figure 26. HBLK Masking Polarity Control
HBLKTOGE2
HBLKTOGE1
HBLKTOGE4
HBLKTOGE3
HBLKTOGE6
HBLKTOGE5
HBLK
H1/H3
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS (HBLKALT = 0)
Figure 27. Using Multiple Toggle Positions for HBLK (HBLKMODE = 0)
Rev. 0 | Page 22 of 100
05892-026
H2/H4
AD9927
Table 11. HBLK Pattern Registers
Register
HBLKMODE
Length
2b
Range
0 to 2 HBLK modes
HBLKSTART
HBLKEND
HBLKLEN
HBLKREP
HBLKMASK_H1
HBLKMASK_H2
HBLKMASK_HL
HBLKTOGO1
HBLKTOGO2
HBLKTOGO3
HBLKTOGO4
HBLKTOGO5
HBLKTOGO6
HBLKTOGE1
HBLKTOGE2
HBLKTOGE3
HBLKTOGE4
HBLKTOGE5
HBLKTOGE6
RA0H1REPA/B/C
13b
13b
13b
13b
1b
1b
1b
13b
13b
13b
13b
13b
13b
13b
13b
13b
13b
13b
13b
12b
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixels
0 to 8191 repetitions
High/low
High/low
High/low
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 15 HCLK pulses for
each A, B, and C
RA1H1REPA/B/C
RA2H1REPA/B/C
RA3H1REPA/B/C
RA4H1REPA/B/C
RA5H1REPA/B/C
RA0H2REPA/B/C
12b
12b
12b
12b
12b
12b
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses for
each A, B, and C
RA1H2REPA/B/C
RA2H2REPA/B/C
RA3H2REPA/B/C
RA4H2REPA/B/C
RA5H2REPA/B/C
HBLKSTARTA
HBLKSTARTB
HBLKSTARTC
12b
12b
12b
12b
12b
13b
13b
13b
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
Description
Enables different HBLK toggle position operation.
0: normal mode. Six toggle positions available for even and odd lines.
If even/odd alternation is not needed, set toggles for even/odd the same.
1: pixel mixing mode. In addition to the six toggle positions, the HBLKSTART,
HBLKEND, HBLKLEN, and HBLKREP registers can be used to generate HBLK
patterns. If even/odd alternation is not need, set toggles for even/odd the same.
2: advanced HBLK mode. Divides HBLK interval into six repeat areas. Uses
HBLKSTARTA/B/C and RA*H*REPA/B/C registers.
3: test mode only. Do not access.
Start location for HBLK in HBLK Mode 1 and HBLK Mode 2.
End location for HBLK in HBLK Mode 1 and HBLK Mode 2.
HBLK length in HBLK Mode 1 and HBLK Mode 2.
Number of HBLK repetitions in HBLK Mode 1 and HBLK Mode 2.
Masking polarity for H1, H3, H5, H7 during HBLK.
Masking polarity for H2, H4, H6, H8 during HBLK.
Masking polarity for HL during HBLK.
First HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
Second HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
Third HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
Fourth HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
Fifth HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
Sixth HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
First HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
Second HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
Third HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
Fourth HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
Fifth HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
Sixth HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
HBLK Repeat Area 0. Number of H1 repetitions for HBLKSTARTA/B/C in
HBLK Mode 2 for even lines; odd lines defined using HBLKALT_PAT.
[3:0] RA0H1REPA. Number of H1 pulses following HBLKSTARTA.
[7:4] RA0H1REPB. Number of H1 pulses following HBLKSTARTB.
[11:8] RA0H1REPC. Number of H1 pulses following HBLKSTARTC.
HBLK Repeat Area 1. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 2. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 3. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 4. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 5. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 0. Number of H2 repetitions for HBLKSTARTA/B/C in
HBLK Mode 2 for even lines; odd lines defined using HBLKALT_PAT.
[3:0] RA0H2REPA. Number of H2 pulses following HBLKSTARTA.
[7:4] RA0H2REPB. Number of H2 pulses following HBLKSTARTB.
[11:8] RA0H2REPC. Number of H2 pulses following HBLKSTARTC.
HBLK Repeat Area 1. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 2. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 3. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 4. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 5. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area Start Position A for HBLK Mode 2. Set to 8191 if not used.
HBLK Repeat Area Start Position B for HBLK Mode 2. Set to 8191 if not used.
HBLK Repeat Area Start Position C for HBLK Mode 2. Set to 8191 if not used.
Rev. 0 | Page 23 of 100
AD9927
Register
HBLKALT_PAT1
Length
3b
Range
0 to 5 even repeat area
HBLKALT_PAT2
HBLKALT_PAT3
HBLKALT_PAT4
HBLKALT_PAT5
HBLKALT_PAT6
3b
3b
3b
3b
3b
0 to 5 even repeat area
0 to 5 even repeat area
0 to 5 even repeat area
0 to 5 even repeat area
0 to 5 even repeat area
HBLKTOGE2
HBLKSTART
HBLKTOGE1
Description
HBLK Mode 2, Odd Field Repeat Area 0 pattern, selected from even field
repeat areas previously defined.
HBLK Mode 2, Odd Field Repeat Area 1 pattern.
HBLK Mode 2, Odd Field Repeat Area 2 pattern.
HBLK Mode 2, Odd Field Repeat Area 3 pattern.
HBLK Mode 2, Odd Field Repeat Area 4 pattern.
HBLK Mode 2, Odd Field Repeat Area 5 pattern.
HBLKTOGE4
HBLKTOGE3
HBLKEND
HBLK
HBLKLEN
HBLKREP = 3
H1/H3
HBLKREP NUMBER 1
HBLKREP NUMBER 2
05892-027
H2/H4
HBLKREP NUMBER 3
H-BLANK REPEATING PATTERN IS CREATED USING HBLKLEN AND HBLKREP REGISTERS
Figure 28. HBLK Repeating Pattern Using HBLKMODE = 1
Bits [7:4]) is set to a value between 1 and 15. When this register
is set to 0, the wide HCLK feature is disabled. The reduced
frequency occurs only for H1 to H8 pulses that are located
within the HBLK area.
HBLK Mode 1 Operation
Multiple repeats of the HBLK signal are enabled by setting
HBLKMODE to 1. In this mode, the HBLK pattern can be
generated using a different set of registers: HBLKSTART,
HBLKEND, HBLKLEN, and HBLKREP, along with the six
toggle positions (see Figure 28).
Separate toggle positions are available for even and odd lines. If
alternation is not needed, the same values should be loaded into
the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.
Generating HBLK Line Alternation
HBLK Mode 0 and HBLK Mode 1 provide the ability to
alternate different HBLK toggle positions on even and odd
lines. HBLK line alternation can be used in conjunction with
V-pattern odd/even alternation or on its own. Separate toggle
positions are available for even and odd lines. If even/odd line
alternation is not required, the same values should be loaded into
the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.
The HCLK_WIDTH register is generally used in conjunction
with special HBLK patterns to generate vertical and horizontal
mixing in the CCD.
Note that the wide HCLK feature is available only in HBLK
Mode 0 and HBLK Mode 1. HBLK Mode 2 does not support
wide HCLKs.
Table 12. HCLK Width Register
Register
HCLK_WIDTH
Increasing H-Clock Width During HBLK
HBLK Mode 0 and HBLK Mode 1 allow the H1 to H8 pulse
width to be increased during the HBLK interval. As shown in
Figure 29, the H-clock frequency can be reduced by a factor of
1/2, 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30. To enable
this feature, the HCLK_WIDTH register (Address 0x34,
Rev. 0 | Page 24 of 100
Length
4b
Description
Controls H1 to H8 width during
HBLK as a fraction of pixel rate
0: same frequency as pixel rate
1: 1/2 pixel frequency, that is,
doubles the HCLK pulse width
2: 1/4 pixel frequency
3: 1/6 pixel frequency
4: 1/8 pixel frequency
5: 1/10 pixel frequency
…
15: 1/30 pixel frequency
AD9927
HBLK
H1/H3
1/FPIX
2 × (1/FPIX)
05892-028
H2/H4
H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN),
1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USING HBLKWIDTH REGISTER
Figure 29. Generating Wide H-Clock Pulses During HBLK Interval
HD
CREATE UP TO 3 GROUPS OF TOGGLES
A, B, C COMMON IN ALL REPEAT AREAS
A
CHANGE NUMBER OF A, B, C PULSES IN ANY
REPEAT AREA USING RA*H*REP* REGISTERS
MASK A, B, C PULSES IN ANY REPEAT
AREA BY SETTING RA*H*REP* = 0
B
C
H1
REPEAT AREA 0
REPEAT AREA 1 REPEAT AREA 2
REPEAT AREA 3
REPEAT AREA 4 REPEAT AREA 5
HBLKSTART
HBLKEND
05892-029
H2
Figure 30. HBLK Mode 2 Operation
HD
HBLKLEN
HBLK
HBLKSTARTA
ALL RA*H*REPA/B/C REGISTERS = 2 TO CREATE TWO HCLK PULSES
HBLKSTARTB
HBLKSTARTC
H1
RA0H1REPA RA0H1REPB
RA0H1REPC
RA1H1REPA RA1H1REPB
RA1H1REPC
RA1H2REPA RA1H2REPB
RA1H2REPC
H2
RA0H2REPA RA0H2REPB
RA0H2REPC
REPEAT AREA 1
REPEAT AREA 0
HBLKREP = 2
TO CREATE TWO REPEAT AREAS
Figure 31. HBLK Mode 2 Registers
Rev. 0 | Page 25 of 100
HBLKEND
05892-030
HBLKSTART
AD9927
HBLK Mode 2 Operation
HORIZONTAL TIMING SEQUENCE EXAMPLE
HBLK Mode 2 allows more advanced HBLK pattern operation.
If multiple areas of HCLK pulses that are unevenly spaced apart
from one another are needed, HBLK Mode 2 can be used. Using
a separate set of registers, HBLK Mode 2 can divide the HBLK
region into up to six repeat areas (see Table 11). As shown in
Figure 31, each repeat area shares a common group of toggle
positions, HBLKSTARTA, HBLKSTARTB, and HBLKSTARTC.
However, the number of toggles following each start position
can be unique in each repeat area by using the RAH1REP and
RAH2REP registers. As shown in Figure 30, setting the
RAH1REPA/RAH1REPB/RAH1REPC or RAH2REPA/
RAH2REPB/RAH2REPC registers to 0 masks HCLK groups
from appearing in a particular repeat area. Figure 31 shows only
two repeat areas being used, although six are available. It is possible
to program a separate number of repeat area repetitions for H1
and H2, but generally the same value is used for both H1 and
H2. Figure 31 shows an example of RA0H1REPA/RA0H1REPB/
RA0H1REPC = RA0H2REPA/RA0H2REPB/RA0H2REPC =
RA1H1REPA/RA1H1REPB/RA1H1REPC = RA1H2REPA/
RA1H2REPB/RA1H2REPC = 2.
Figure 32 shows an example CCD layout. The horizontal register
contains 28 dummy pixels, which occur on each line clocked
from the CCD. In the vertical direction, there are 10 optical
black (OB) lines at the front of the readout and two at the back
of the readout. The horizontal direction has four OB pixels in
the front and 48 in the back.
Figure 33 shows the basic sequence layout to be used during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the HBLK time. HBLK
is used during the vertical shift interval.
Because PBLK is used to isolate the CDS input (see the Analog
Preblanking section), the PBLK signal should not be used
during CLPOB operation. The change in the offset behavior
that occurs during PBLK impacts the accuracy of the CLPOB
circuitry.
The HBLK, CLPOB, and PBLK parameters are programmed in
the V-sequence registers. More elaborate clamping schemes,
such as adding in a separate sequence to clamp in the entire
shield OB lines, can be used. This requires configuring a
separate V-sequence for clocking out the OB lines.
Furthermore, HBLK Mode 2 allows a different HBLK pattern
on even and odd lines. The HBLKSTARTA, HBLKSTARTB, and
HBLKSTARTC registers, as well as the RAH1REPA/RAH1REPB/
RAH1REPC and RAH2REPA/RAH2REPB/RAH2REPC registers,
define operation for the even lines. For separate control of the
odd lines, the HBLKALT_PAT registers specify up to six repeat
areas on the odd lines by reordering the repeat areas used for the
even lines. New patterns are not available, but the order of the
previously defined repeat areas on the even lines can be changed
for the odd lines to accommodate advanced CCD operation.
The CLPMASK registers are also useful for disabling the
CLPOB on a few lines without affecting the setup of the
clamping sequences. It is important that CLPOB be used only
during valid OB pixels. During other portions on the frame
timing, such as vertical blanking or SG line timing, the CCD
does not output valid OB pixels. Any CLPOB pulse that occurs
during this time causes errors in clamping operation and
changes in the black level of the image.
2 VERTICAL
OB LINES
V
EFFECTIVE IMAGE AREA
10 VERTICAL
OB LINES
H
48 OB PIXELS
4 OB PIXELS
05892-031
HORIZONTAL CCD REGISTER
28 DUMMY PIXELS
Figure 32. Example CCD Configuration
Rev. 0 | Page 26 of 100
AD9927
OPTICAL BLACK
OPTICAL BLACK
HD
CCD OUTPUT
VERTICAL SHIFT
DUMMY
EFFECTIVE PIXELS
OPTICAL BLACK
VERT. SHIFT
SHP
SHD
H1/H3/H5/H7
H2/H4/H6/H8
HBLK
PBLK
NOTES
1. PBLK ACTIVE (LOW) SHOULD NOT BE USED DURING CLPOB ACTIVE (LOW).
Figure 33. Horizontal Sequence Example
Rev. 0 | Page 27 of 100
05892-032
CLPOB
AD9927
VERTICAL TIMING GENERATION
The AD9927 provides a flexible solution for generating vertical
CCD timing and can support multiple CCDs and different
system architectures. The vertical transfer clocks are used to
shift each line of pixels into the horizontal output register of the
CCD. The AD9927 allows these outputs to be individually
programmed into various readout configurations by using a
4-step process.
Figure 34 shows an overview of how the vertical timing is
generated in four steps.
1. The individual pulse patterns for XV1 to XV24 are created by
using the vertical pattern group registers.
2. The V-pattern groups are used to build the sequences, which
is where additional information is added.
3. The readout for an entire field is constructed by dividing the
field into different regions and then assigning a sequence to
each region. Each field can contain up to nine different regions
to accommodate different steps of the readout, such as high
speed line shifts and unique vertical line transfers. The total
number of V-patterns, V-sequences, and fields is programmable,
but limited by the number of registers.
4. The MODE registers allow the different fields to be combined
in any order for various readout configurations.
Rev. 0 | Page 28 of 100
AD9927
CREATE THE VERTICAL PATTERN GROUPS,
UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT.
1
BUILD THE V-SEQUENCES BY ADDING START POLARITY,
LINE START POSITION, NUMBER OF REPEATS, ALTERNATION,
GROUP A/B/C/D INFORMATION, AND HBLK/CLPOB PULSES.
2
XV1
XV1
XV2
VPAT0
XV2
XV3
XV3
V-SEQUENCE 0
(VPAT0, 1 REP)
XV23
XV23
XV24
XV24
XV1
XV2
XV1
XV3
V-SEQUENCE 1
(VPAT1, 2 REP)
XV2
XV3
VPAT1
XV23
XV24
XV23
XV24
XV1
XV2
XV3
V-SEQUENCE 2
(VPAT1, N REP)
XV23
XV24
USE THE MODE REGISTERS TO CONTROL WHICH FIELDS
ARE USED, AND IN WHAT ORDER (MAXIMUM OF SEVEN
FIELDS MAY BE COMBINED IN ANY ORDER).
3
BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS
AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH
(MAXIMUM OF NINE REGIONS IN EACH FIELD).
FIELD 0
FIELD0
FIELD1
FIELD2
REGION 0: USE V-SEQUENCE 2
REGION 0: USE V-SEQUENCE 3
REGION 1: USE V-SEQUENCE 0
REGION 0: USE V-SEQUENCE 3
REGION
USE V-SEQUENCE
2
REGION
2: USE1:V-SEQUENCE
3
REGION 1: USE V-SEQUENCE 2
FIELD3
FIELD4
REGION 3: USE V-SEQUENCE 0
REGION 2: USE V-SEQUENCE 1
FIELD5
FIELD1
FIELD4
FIELD2
REGION 2: USE V-SEQUENCE 1
REGION 4: USE V-SEQUENCE 2
FIELD1
FIELD2
Figure 34. Summary of Vertical Timing Generation
Rev. 0 | Page 29 of 100
05892-033
4
AD9927
Vertical Pattern Groups (VPAT)
The vertical pattern groups define the individual pulse patterns
for each XV1 to XV24 output signal. Table 13 summarizes the
registers available for generating each of the V-pattern groups.
The first, second, third, and fourth toggle positions (VTOG1,
VTOG2, VTOG3, and VTOG4) are the pixel locations within
the line where the pulse transitions. All toggle positions are
13-bit values, allowing their placement anywhere in the
horizontal line.
More registers are included in the vertical sequence registers to
specify the output pulses. VPOL specifies the start polarity for
each signal; VSTART specifies the start position of the
V-pattern group within the line; VLEN designates the total
length of the V-pattern group, which determines the number of
pixels between each of the pattern repetitions when repetitions
are used.
The VSTART position is actually an offset value for each toggle
position. The actual pixel location for each toggle, measured
from the HD falling edge (Pixel 0), is equal to the VSTART
value plus the toggle position.
When the selected V-output is designated as a VSG pulse, either
the VTOG1/VTOG2 or VTOG3/VTOG4 pair is selected using
V-Sequence Address 0x02, VSGPATSEL. All four toggle positions
are not simultaneously available for VSG pulses.
All unused V-channels must have their toggle positions
programmed to either 0 or maximum value. This prevents
unpredictable behavior because the default values of the
V-pattern group registers are unknown.
Table 13. Vertical Pattern Group Registers
Register
VTOG1
VTOG2
VTOG3
VTOG4
Length
13b
13b
13b
13b
Description
First toggle position within line for each XV1 to XV24 output, relative to VSTART value
Second toggle position, relative to VSTART value
Third toggle position, relative to VSTART value
Fourth toggle position, relative to VSTART value
START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS.
HD
4
1
2
XV2
3
1
2
XV24
3
1
2
3
PROGRAMMABLE SETTINGS:
1START POLARITY (LOCATED IN V-SEQUENCE REGISTERS).
2FIRST TOGGLE POSITION.
3SECOND TOGGLE POSITION (THIRD AND FOURTH TOGGLE POSITIONS ALSO AVAILABLE FOR MORE COMPLEX PATTERNS).
4TOTAL PATTERN LENGTH FOR ALL VERTICAL OUTPUTS (LOCATED IN VERTICAL SEQUENCE REGISTERS).
Figure 35. Vertical Pattern Group Programmability
Rev. 0 | Page 30 of 100
05892-034
XV1
AD9927
VERTICAL SEQUENCES (VSEQ)
into both registers. If a different number of repetitions is
required on odd and even lines, separate values can be used for
each register (see the Generating Line Alternation for VSequences and HBLK section). The VSTARTA and VSTARTB
registers specify where in the line the V-pattern group starts.
The VMASK_EN register is used in conjunction with the
FREEZE/RESUME registers to enable optional masking of the
V-outputs. Either or both of the FREEZE1/RESUME1 and
FREEZE2/RESUME2 registers can be enabled.
The vertical sequences are created by selecting one of the
V-pattern groups and adding repeats, start position, horizontal
clamping, and blanking information. The V-sequences are
programmed using the registers shown in Table 14. Figure 36
shows how the different registers are used to generate each
V-sequence.
The VPATSELA, VPATSELB, VPATSELC, and VPATSELD
registers select which V-pattern is used in a given V-sequence.
Having four groups available allows different vertical outputs to
be mapped to different V-patterns. The selected V-pattern group
can have repetitions added for high speed line shifts or for line
binning by using the VREP registers for odd and even lines.
Generally, the same number of repetitions is programmed
The line length (in pixels) is programmable using the HDLEN
registers. Each V-sequence can have a different line length to
accommodate various image readout techniques. The maximum
number of pixels per line is 8192. The last line of the field is
programmed separately using the HDLASTLEN register, which
is located in the field register section.
1
HD
2
XV1 TO XV24
HBLK
4
4
VREP 2
VREP 3
5
6
PROGRAMMABLE SETTINGS FOR EACH VERTICAL SEQUENCE:
1START POSITION IN THE LINE OF SELECTED V-PATTERN GROUP.
2HD LINE LENGTH.
3V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP.
4NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED).
5START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS.
6MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL.
Figure 36. V-Sequence Programmability
Rev. 0 | Page 31 of 100
05892-035
CLPOB
3
V-PATTERN GROUP
AD9927
Table 14. Summary of V-Sequence Registers (see Table 10 and Table 11 for the HBLK, CLPOB, and PBLK Register Summary)
Register
HOLD
Length
4b
VMASK_EN
4b
CONCAT_GRP
4b
VREP_MODE
2b
LASTREPLEN_EN
4b
LASTTOG_EN
4b
HDLENE
HDLEN0
VPOL_A
VPOL_B
VPOL_C
VPOL_D
GROUPSEL_0
13b
13b
24b
24b
24b
24b
24b
GROUPSEL_1
24b
VPATSELA
VPATSELB
VPATSELC
VPATSELD
VSTARTA
VSTARTB
VSTARTC
VSTARTD
VLENA
VLENB
VLENC
VLEND
VREPA_1
VREPA_2
VREPA_3
VREPA_4
VREPB_ODD
VREPC_ODD
5b
5b
5b
5b
13b
13b
13b
13b
13b
13b
13b
13b
13b
13b
13b
13b
13b
13b
Description
Use in conjunction with VMASK_EN.
1 = HOLD function instead of FREEZE/RESUME function.
Enables the masking of V1 to V24 outputs at the locations specified by the FREEZE/RESUME registers.
1= enable masking for all groups. One bit for each set of Freeze and Resume Positions 1 to 4.
Combines toggle positions of Groups A/B/C/D when enabled. Only Group A settings for start, polarity,
length, and repetition are used when this mode is selected.
0 = disable.
1 = enable the addition of all toggle positions from VPATSELA/B/C/D.
2 = test mode only. Do not use.
…
15 = test mode only. Do not use.
Selects line alternation for V-output repetitions. Note separate control for Group A and Groups B/C/D.
0 = disable alternation. Group A uses VREPA_1, Groups B/C/D use VREP _EVEN for all lines.
1 = 2-line. Group A alternates VREPA_1 and VREPA_2. Groups B/C/D alternate VREP_EVEN and VREP_ODD.
2 = 3-line. Group A alternates VREPA_1, VREPA_2, and VREPA_3. Groups B/C/D follow a VREP_EVEN,
VREP_ODD, VREP_ODD, VREP_EVEN, VREP_ODD, VREP_ODD pattern.
3 = 4-line. Group A alternates VREPA_1, VREPA_2, VREPA_3, VREPA_4. Groups B/C/D follow 2-line alternation.
Enables a separate pattern length to be used during the last repetition of the V-sequence. One bit for
each group (A, B, C, and D). Set bit high to enable. Group A is the LSB. Recommended value is enabled.
Enables a final toggle position to be added at the end of the V-sequence. The toggle position is shared
by all V-outputs in the same group. One bit for each group. Set bit high to enable. Group A is the LSB.
HD line length for even lines in the V-sequence.
HD line length for odd lines in the V-sequence.
Group A start polarity bits for each XV1 to XV24 signal.
Group B start polarity bits for each XV1 to XV24 signal.
Group C start polarity bits for each XV1 to XV24 signal.
Group D start polarity bits for each XV1 to XV24 signal.
Assigns each XV1 to XV12 signal to either Group A/B/C/D. Two bits for each signal. Bits [1:0] are for XV1,
Bits [3:2] are for XV2 … Bits [23:22] are for XV12.
0 = assign to Group A, 1 = Group B, 2 = Group C, and 3 = Group D.
Assigns each XV13 to XV24 signal to either Group A/B/C/D. Two bits for each signal. Bits [1:0] are for XV13,
Bits [3:2] are for XV14 … Bits [23:22] are for XV24.
0 = assign to Group A, 1 = Group B, 2 = Group C, and 3 = Group D.
Selected V-pattern for Group A.
Selected V-pattern for Group B.
Selected V-pattern for Group C.
Selected V-pattern for Group D.
Start position for the selected V-pattern Group A.
Start position for the selected V-pattern Group B.
Start position for the selected V-pattern Group C.
Start position for the selected V-pattern Group D.
Length of selected V-pattern Group A.
Length of selected V-pattern Group B.
Length of selected V-pattern Group C.
Length of selected V-pattern Group D.
Number of repetitions for the V-Pattern Group A for first lines (even).
Number of repetitions for the V-Pattern Group A for second lines (odd).
Number of repetitions for the V-Pattern Group A for third lines.
Number of repetitions for the V-Pattern Group A for fourth lines.
Number of repetitions for the V-Pattern Group B for odd lines.
Number of repetitions for the V-Pattern Group C for odd lines.
Rev. 0 | Page 32 of 100
AD9927
Register
VREPD_ODD
VREPB_EVEN
VREPC_EVEN
VREPD_EVEN
FREEZE1
Length
13b
13b
13b
13b
13b
FREEZE2
13b
FREEZE3
13b
FREEZE4
13b
RESUME1
13b
RESUME 2
13b
RESUME3
13b
RESUME4
13b
LASTREPLEN_A
13b
LASTREPLEN_B
13b
LASTREPLEN_C
13b
LASTREPLEN_D
13b
LASTTOG_A
13b
LASTTOG_B
13b
LASTTOG_C
13b
LASTTOG_D
13b
VSEQALT_EN
VALT_MAP
1b
1b
VALTSEL0_EVEN
18b
VALTSEL1_EVEN
18b
VALTSEL0_ODD
18b
VALTSEL1_ODD
18b
SPC_PAT_EN
1b
Description
Number of repetitions for the V-Pattern Group D for odd lines.
Number of repetitions for the V-Pattern Group B for even lines.
Number of repetitions for the V-Pattern Group C for even lines.
Number of repetitions for the V-Pattern Group D for even lines.
Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL0_EVEN [12:0]
register when Special VSEQALT_EN mode is enabled.
Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL1_EVEN [12:0]
register when Special VSEQALT_EN mode is enabled.
Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL0_ODD [12:0]
register when Special VSEQALT_EN mode is enabled.
Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL1_ODD [12:0]
register when Special VSEQALT_EN mode is enabled.
Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL0_EVEN [17:13]
register when Special VSEQALT_EN mode is enabled.
Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL1_EVEN [17:13]
register when Special VSEQALT_EN mode is enabled.
Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL0_ODD [17:13]
register when Special VSEQALT_EN mode is enabled.
Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL1_ODD [17:13]
register when Special VSEQALT_EN mode is enabled.
Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENA register.
Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENB register.
Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENC register.
Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLEND register.
Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN.
Note that the toggle position is common for all vertical signals.
Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN.
Note that the toggle position is common for all vertical signals.
Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN.
Note that the toggle position is common for all vertical signals.
Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN.
Note that the toggle position is common for all vertical signals.
Special V-sequence alternation mode is enabled when this register is programmed high.
Enables the use of FREEZE/RESUME register locations to specify the VALTSEL0 and VALTSEL1 registers.
Must be enabled if VSEQALT mode is enabled.
Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Groups A/B/C/D
into unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments.
Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Groups A/B/C/D
into unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments.
Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Groups A/B/C/D
into unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments.
Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Groups A/B/C/D
into unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments.
Enable special V-pattern to be inserted into one repetition of a VPATA series.
SPC_PAT_EN [0]: set to 1 to enable VPATB to be used as special pattern insertion.
SPC_PAT_EN [1]: set to 1 to enable VPATC to be used as special pattern insertion.
SPC_PAT_EN [2]: set to 1 to enable VPATD to be used as special pattern insertion.
Rev. 0 | Page 33 of 100
AD9927
HD
XV1 TO XV8 USE
V-PATTERN GROUP A
XV1
XV8
XV9, XV10 USE
V-PATTERN GROUP B
05892-036
XV9
XV10
Figure 37. Using Separate Group A and Group B Patterns
HD
V-PATTERN GROUP A
V-PATTERN GROUP B
V-PATTERN GROUP C
V-PATTERN GROUP D
05892-037
XV1
XV24
Figure 38. Combining Multiple V-Patterns Using CONCAT_GRP = 1
HD
V-PATTERN GROUP A
V-PATTERN GROUP B
XV1
GROUP A REP 1
GROUP A REP 2
GROUP A REP 3
05892-038
XV10
Figure 39. Combining Group A and Group B Patterns with Repetition
Group A/Group B/Group C/Group D Selection
The AD9927 has the flexibility to use four different V-pattern
groups in a vertical sequence. In general, the vertical outputs
use the same V-pattern group during a particular sequence. It
is possible to assign some of the outputs to a different V-pattern
group, which can be useful in certain CCD readout modes.
The GROUPSEL registers are used to select Group A, Group B,
Group C, or Group D for each V-output. In general, only a
single V-pattern group is needed for the vertical outputs;
therefore, Group A should be selected for all outputs by default
(GROUPSEL_0, GROUPSEL_1 = 0x00). In this configuration,
all outputs use the V-pattern group specified by the VPATSELA
register.
If additional flexibility is needed, some outputs can be set to
Group B, Group C, or Group D in the GROUPSEL registers. In
this case, those selected outputs use the V-pattern group
specified by the VPATSELB, VPATSELC, or VPATSELD
registers. Figure 37 shows an example where outputs V9 and
V10 are using a separate V-Pattern Group B to perform special
CCD timing.
Another application of the Group A, Group B, Group C, and
Group D registers is to combine up to four different V-pattern
groups together for more complex patterns. This is accomplished by setting the CONCAT_GRP register (Address 0x00,
Bits [13:10]) equal to 0x01. This setting combines the toggle
positions from the V-pattern groups specified by registers
VPATSELA, VPATSELB, VPATSELC, and VPATSELD for a
Rev. 0 | Page 34 of 100
AD9927
maximum of up to 16 toggle positions. Example timing for the
CONCAT_GRP = 1 feature is shown in Figure 38.
If only two groups are needed (up to eight toggle positions) for
the specified timing, the VPATSELB, VPATSELC, and
VPATSELD registers can be programmed to the same value. If
only three groups are needed, VPATSELC and VPATSELD can
be programmed to the same value. Following this approach
conserves register memory if the four separate V-patterns are
not needed.
Note that when CONCAT_GRP is enabled, the Group A
settings are used only for start position, polarity, length, and
repetitions. All toggle positions for Group A, Group B,
Group C, and Group D are combined together and applied
using the settings in the VSTARTA, VPOL_A, VLENA, and
VREPA registers.
Special Vertical Sequence Alternation (SVSA) Mode
The AD9927 has additional flexibility for combining four
different V-pattern groups in a random sequence that can be
programmed for specific CCD requirements. This mode of
operation allows custom vertical sequences for CCDs that
require more complex vertical timing patterns. For example,
using the special vertical sequence alternation mode, it is
possible to support random pattern concatenation, with
additional support for odd/even line alternation.
Figure 40 illustrates four common and repetitive vertical
pattern segments, A through D, that are derived from the
complete vertical pattern. Figure 41 illustrates how each group
can be concatenated together in an arbitrary order.
To enable the SVSA mode, write the VSEQALT_EN bit,
Address 0x20 Bit [13], equal to 0x01. The location of the
VALTSEL registers is shared with the VPAT registers
for XV24. When SVSA mode is enabled, the VALTSEL register
function is selected.
To create SVSA timing, divide the complete vertical timing
pattern into four common and repetitive segments. Identify the
related segments as VPATA, VPATB, VPATC, or VPATD. Up to
four toggle positions for each segment can be programmed
using the V-pattern registers.
Table 15. VALTSEL Bit Settings for Even and Odd Lines
Parameter
VALTSEL0_EVEN
VALTSEL1_EVEN
VALTSEL0_ODD
VALTSEL1_ODD
Resulting pattern for even lines
Resulting pattern for odd lines
When the entire pattern is divided, program VALTSEL0 (even
and odd) [17:0] and VALTSEL1 (even and odd) [17:0] so that
the segments will be concatenated in the desired order. If
separate odd and even lines are not required, set the odd and
even registers to the same value.
Figure 42 illustrates the process of using six vertical pattern
segments that have been concatenated into a small, merged
pattern.
Program the register VREPA_1 to specify the number of
segments that will be concatenated into each merged pattern.
The maximum number of segments that can be concatenated to
create a merged pattern is 18. Program VLENA, VLENB, VLENC,
VLEND to be of equal length. Finally, program HBLK to generate
the proper H-clock timing using the procedure for HBLK Mode 2
described in the HBLK Mode 2 Operation section.
It is important to note that because the FREEZE/RESUME
registers are used to specify the VALTSEL registers, the
VALT_MAP register must be enabled when using the special
VALT mode.
Table 16. VALTSEL Register Locations1
Register Function
When VSEQALT_EN = 1
VALTSEL0_EVEN [12:0]
VALTSEL0_EVEN [17:13]
VALTSEL1_EVEN [12:0]
VALTSEL1_EVEN [17:13]
VALTSEL0_ODD [12:0]
VALTSEL0_ ODD [17:13]
VALTSEL1_ ODD [12:0]
VALTSEL1_ ODD [17:13]
1
Table 15 shows how the segments are specified using a 2-bit
representation. Each bit from VALTSEL0 and VALTSEL1 are
combined to produce four values, corresponding to patterns A,
B, C, and D.
VALTSEL BIT SETTINGS
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
A
B
C
D
A
B
C
D
Register Location
VSEQ register FREEZE1 [12:0]
VSEQ register RESUME1 [17:13]
VSEQ register FREEZE2 [12:0]
VSEQ register RESUME2 [17:13]
VSEQ register FREEZE3 [12:0]
VSEQ register RESUME3 [17:13]
VSEQ register FREEZE4 [12:0]
VSEQ register RESUME4 [17:13]
The VALT_MAP register must be set to 1 to enable the use of VALTSEL
registers.
Rev. 0 | Page 35 of 100
AD9927
V-PATTERN A
V-PATTERN B
VLENA
VLENB
V-PATTERN C
V-PATTERN D
XV1
XV2
XV3
XV23
VLENC
VLEND
05892-039
NOTES
1. EACH SEGMENT MUST BE THE SAME LENGTH.
VLENA = VLENB = VLENC = VLEND.
Figure 40. Vertical Timing Divided Into Four Segments: VPATA, VPATB, VPATC, and VPATD
HD
COMBINED
V-PATTERN
A B B D A C C
B C B D A B A
A
A
05892-040
NOTES
1. ABLE TO CONCATENATE PATTERNS TOGETHER ARBITRARILY.
2. EACH PATTERN CAN HAVE UP TO FOUR TOGGLES PROGRAMMED.
3. MAY CONCATENATE UP TO 18 PATTERNS INTO A MERGED PATTERN.
4. ODD AND EVEN LINES CAN HAVE A DIFFERENT PATTERN CONCATENATION
SPECIFIED BY VALTSEL EVEN AND ODD REGISTERS.
Figure 41. Concatenating Each VPAT Group in Arbitrary Order
HD
A
XV1 TO XV23
SEGMENT 1
C
B
D
SEGMENT 2
D
A
SEGMENT 3
SEGMENT4
SEGMENT 5
VPATB
VPATD
VPATD
1
0
1
1
SEGMENT 6
XV1
XV2
XV3
XV23
0
0
VPATC
0
1
1
1
VPATA
0
0
NOTES
1. SIX V-PATTERN SEGMENTS CONCATENATED INTO A MERGED PATTERN.
2. COMMON AND REPETITIVE VTP SEGMENTS DERIVED FROM THE COMPLETE VTP PATTERN.
3. VALTSEL REGISTERS SPECIFY SEGMENT ORDER TO CREATE THE CONCATENATED MERGED PATTERN.
Figure 42. Example of Special V-Sequence Alternation Mode Using VALTSEL Registers to Specify Segment Order
Rev. 0 | Page 36 of 100
05892-041
VPATA
VALTSEL0_EVEN
VALTSEL1_EVEN
AD9927
Using the LASTREPLEN_EN
The LASTREPLEN_EN register (Address 0x00, Bits [19:16] in
the sequence registers) is used to enable a separate pattern
length to be used in the final repetition of several pulse
repetitions. It is recommended that the LASTREPLEN_EN
register bits be set high (enabled) and the LASTREPLEN_A,
LASTREPLEN_B, LASTREPLEN_C, AND LASTREPLEN_D
registers be set to a value equal to the VLENA, VLENB,
VLENC, and VLEND register values, respectively.
Generating Line Alternation for V-Sequences and HBLK
During low resolution readout, some CCDs require a different
number of vertical clocks on alternate lines. The AD9927 can
support this by using the VREP registers. This allows a different
number of V-pattern group repetitions to be programmed on
odd and even lines. Only the number of repeats can be different
in odd and even lines, while the V-pattern group remains the
same. There are separate controls for the assigned Group A,
Group B, Group C, and Group D patterns. All groups can
support odd and even line alternation. Group A uses the
VREPA_1 and VREPA_2 registers; Group B, Group C, and
Group D use the corresponding VREP_ODD and VREP_EVEN
registers. With the additional VREPA_3 and VREPA_4
registers, Group A can also support 3-line and 4-line
alternation.
As discussed in the Generating HBLK Line Alternation section,
the HBLK signal can be alternated for odd and even lines.
Figure 43 shows an example of V-pattern group repetition
alternation and HBLK Mode 0 alternation used together.
HD
VREPA_1 = 2
(OR VREPB/C/D_EVEN = 2)
VREPA_2 = 5
(OR VREPB/C/D_ODD = 5)
VREPA_1 = 2
(OR VREPB/C/D_EVEN = 2)
XV1
XV2
XV24
TOGE1
TOGE2
TOGO1
TOGO2
TOGE1
TOGE2
NOTES
1. THE NUMBER OF REPEATS FOR V-PATTERN GROUPS A/B/C/D CAN BE ALTERNATED ON ODD AND EVEN LINES.
2. GROUP A ALSO SUPPORTS 3- AND 4-LINE ALTERNATION USING THE ADDITIONAL VREPA_3 AND VREPA_4 REGISTERS.
3. THE HBLK TOGGLE POSITIONS CAN BE ALTERNATED BETWEEN ODD AND EVEN LINES TO GENERATE DIFFERENT HBLK PATTERNS.
Figure 43. Odd/Even Line Alternation of V-Pattern Group Repetitions and HBLK Toggle Positions
Rev. 0 | Page 37 of 100
05892-042
HBLK
AD9927
Vertical Masking Using FREEZE/RESUME Registers
FREEZE/RESUME registers are provided, allowing the vertical
outputs to be interrupted up to four times in the same line. The
FREEZE and RESUME Positions 1 to 4 are enabled independently
and applied to all groups (Group A, Group B, Group C, and
Group D) using the VMASK_EN register.
As shown in Figure 44 and Figure 45, the FREEZE/RESUME
registers are used to temporarily mask the V-outputs. The pixel
locations to begin the masking (FREEZE) and end the masking
(RESUME) create an area in which the vertical toggle positions
are ignored. At the pixel location specified in the FREEZE register,
the V-outputs are held static at their current dc state, high or low.
The V-outputs are held until the pixel location specified by the
RESUME register is reached, at which point the signals continue
with any remaining toggle positions, if any exist. Four sets of
HD
Note that when masking is enabled, each group (Group A,
Group B, Group C, and Group D) uses the same FREEZE/
RESUME positions.
Note that the FREEZE/RESUME registers are also used as the
VALTSEL0 and VALTSEL1 registers during special vertical
alternation mode.
NO MASKING AREA
05892-043
XV1
XV24
Figure 44. No FREEZE/RESUME
HD
V-MASKING AREA
FREEZE
RESUME
XV1
NOTES
1. ALL TOGGLE POSITIONS WITHIN THE FREEZE/RESUME MASKING AREA ARE IGNORED. H-COUNTER CONTINUES TO COUNT DURING MASKING.
2. FOUR SEPARATE MASKING AREAS ARE AVAILABLE, USING FREEZE1/RESUME1, FREEZE2/RESUME2, FREEZE3/RESUME3, AND
FREEZE4/RESUME4 REGISTERS.
Figure 45. Using FREEZE/RESUME
Rev. 0 | Page 38 of 100
05892-044
XV24
AD9927
Hold Area Using FREEZE/RESUME Registers
The FREEZE/RESUME registers can also be used to create a
hold area in which the V-outputs are temporarily held and later
continued, starting at the point where they were held. As shown
in Figure 46, this is different than the VMASK_EN register because
the V-outputs continue from where they stopped rather than
continuing from where they would have been. The hold area
temporarily stops the pixel counter for the V-outputs, while the
V-masking allows the counter to continue in the masking area.
HD
FREEZE
HOLD AREA
FOR GROUP A
RESUME
XV1
XV8
XV9
NOTES
1. WHEN HOLD = 1 FOR ANY V-SEQUENCE GROUP, THE FREEZE AND RESUME REGISTERS ARE USED TO SPECIFY THE HOLD AREA.
2. ABOVE EXAMPLE: XV1 TO XV10 ARE ASSIGNED TO GROUP A. HOLD BIT FOR GROUP A = 1.
3. H-COUNTER FOR GROUP A (XV1 TO XV10) STOPS DURING HOLD AREA.
Figure 46. Hold Area for Group A
Rev. 0 | Page 39 of 100
05892-045
XV10
AD9927
Note that VREPB is used to specify which repetition number
has the special pattern inserted instead of VPATA. VPATB
always has priority over VPATC or VPATD if more than one
SPC_PAT_EN bit is enabled (SPC_PAT_EN [0] has priority).
Special Pattern Insertion
Additional flexibility is available using the SPC_PAT_EN registers,
which allows a Group B, C, or D pattern to be inserted into a series
of Group A repetitions. This feature is useful when a different
pattern is needed at the start, middle, or end of a sequence.
Figure 47 shows an example of a sweep region using VPATA
with multiple repetitions where a single repetition of VPATB has
been added into the middle of the sequence. Figure 48 shows
more detail on how to set the registers to achieve the desired
timing.
VD
HD
SCP1
LINE 0
LINE 1
SCP2
LINE 2
LINE 24
LINE 25
XV1 TO XVN
REGION 1: SWEEP REGION
REGION 2
05892-046
REGION 0
PATTERN B INSERTED DURING PATTERN A REPETITIONS
Figure 47. Example of Special Pattern Insertion
HD
REP 1
REP 2
REP 3
REP 4
REP 5
REP N
XV1
REGISTER SETTINGS:
SPC_PAT_EN[0] = 1
VREPA = N
VREPB = 4
V-PATTERN B
V-PATTERN A
DESCRIPTION:
V-PATTERN B IS USED AS SPECIAL PATTERN
TOTAL NUMBER OF REPS USED FOR SEQUENCE (N REPS)
REP 4 USES V-PATTERN B INSTEAD OF V-PATTERN A
NOTES
1. VSTARTB MUST BE SET EQUAL TO VSTARTA.
Figure 48. Example of Special Pattern Insertion, Detail
Rev. 0 | Page 40 of 100
05892-047
V-PATTERN A
AD9927
Complete Field: Combining V-Sequences
After the V-sequences are created, they are combined to create
different readout fields. A field consists of up to nine regions,
and within each region, a different V-sequence can be selected.
Figure 49 shows how the sequence change positions (SCP)
designate the line boundary for each region and how the SEQ
registers then select which V-sequence is used in each region.
Registers to control the VSG outputs are also included in the
field registers. Table 17 summarizes the registers used to create
the different fields.
The SEQ registers, one for each region, select which of the
V-sequences are active in each region. The MULT_SWEEP
registers, one for each region, are used to enable sweep mode
and/or multiplier mode in any region. The SCP registers create
the line boundaries for each region. The VDLEN register
specifies the total number of lines in the field. The HDLEN
registers specifies the total number of pixels per line, and the
HDLASTLEN register specifies the number of pixels in the last
line of the field. The VPATSECOND register is used to add a
second V-pattern group to the XV1 to XV10 signals in the
vertical sensor gate (VSG) line.
The SGMASK register is used to enable or disable each individual
VSG output. There are two bits for each VSG output to enable
separate masking in SGACTLINE1 and SGACTLINE2.
Setting a masking bit high masks the output; setting it low
enables the output. The VSGPATSEL register assigns one of the
eight SG patterns to each VSG output. The individual SG
patterns are created separately using the SG pattern registers.
The SGACTLINE1 register specifies which line in the field
contains the VSG outputs. The optional SGACTLINE2 register
allows the same VSG pulses to be repeated on a different line.
Separate masking is not available for SGACTLINE1 and
SGACTLINE2.
Table 17. Field Registers (CLPOB, PBLK Masking Shown in Table 10)
Register
SEQx
MULT_SWEEP
Length
5b
2b
Range
0 to 31 V-sequence no.
0 to 3
SCP
VDLEN
HDLASTLEN
VSGPATSEL
13b
13b
13b
24b
0 to 8191 line no.
0 to 8191 lines
0 to 8191 pixels
High/low
SGMASK
24b
High/low, each VSG
SGACTLINE1
SGACTLINE2
13b
13b
0 to 8191 line no.
0 to 8191 line no.
Description
Selected V-sequence for each region in the field.
Enables multiplier mode and/or sweep mode for each region.
0: multiplier off, sweep off.
1: multiplier off, sweep on.
2: multiplier on, sweep off.
3: multiplier on, sweep on.
Sequence change position for each region.
Total number of lines in each field.
Length in pixels of the last HD line in each field.
VSGPATSEL selects which V-pattern toggle positions are used. When set to 0,
Toggle 1 and Toggle 2 are used. When set to 1, Toggle 3 and Toggle 4 are used.
[0]: XV1 selection (0 = use TOG1, TOG2; 1 = use TOG3, TOG4).
…
[23]: XV24 selection.
Set high to mask each individual VSG output.
[0]: XV1 mask.
…
[23]: XV24 mask.
Selects the line in the field where the VSG signals are active.
Selects a second line in the field to repeat the VSG signals. If not used,
set this equal to SGACTLINE1 or to the maximum value.
Rev. 0 | Page 41 of 100
AD9927
SCP0
SCP1
SCP2
SCP4
SCP3
SCP5
SCP8
VD
REGION 0
REGION 1
REGION 2
REGION 3
REGION 4
REGION 8
SEQ0
SEQ1
SEQ2
SEQ3
SEQ4
SEQ8
HD
XV1 TO XVN
SGACTLINE1
VSG
05892-048
FIELD SETTINGS:
1. SEQUENCE CHANGE POSITIONS (SCP0 TO SCP8) DEFINE EACH OF THE NINE AVAILABLE REGIONS IN THE FIELD.
2. SEQ0 TO SEQ8 SELECT THE DESIRED V-SEQUENCE FOR EACH REGION.
3. SGACTLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD CONTAINS THE SENSOR GATE PULSE(S).
Figure 49. Complete Field is Divided into Regions
VD
HD
SCP1
LINE 0
LINE 1
SCP2
LINE 2
LINE 24
LINE 25
REGION 0
REGION 1: SWEEP REGION
REGION 2
05892-049
XV1 TO XVN
Figure 50. Example of Sweep Region for High Speed Vertical Shift
Sweep Mode Operation
The AD9927 contains an additional mode of vertical timing
operation called sweep mode. This mode is used to generate a
large number of repetitive pulses that span across multiple HD
lines. An example of where this mode is needed is at the start of
the CCD readout operation. At the end of the image exposure
before the image is transferred by the sensor gate pulses, the
vertical interline CCD registers should be free of all charge. This
can be accomplished by quickly shifting out any charge using a
long series of pulses from the vertical outputs. Depending on
the vertical resolution of the CCD, up to 3000 clock cycles
might be needed to shift the charge out of each vertical CCD
line. This operation spans across multiple HD line lengths.
Normally, the AD9927 vertical timing must be contained within
one HD line length, but when sweep mode is enabled, the HD
boundaries are ignored until the region is finished. To enable
sweep mode within any region, program the appropriate SWEEP
register to high.
Figure 50 shows an example of the sweep mode operation. The
number of vertical pulses needed depends on the vertical resolution of the CCD. The toggle positions for the XV1 to XV24
signals are generated using the V-pattern registers (shown in
Table 13). A single pulse is created using the polarity and toggle
position registers. The number of repetitions is then programmed
to match the number of vertical shifts required by the CCD.
Repetitions are programmed into the V-sequence registers
(shown in Table 14) by using the VREP registers. This produces
a pulse train of the appropriate length. Normally, the pulse train
is truncated at the end of the HD line length, but when sweep
mode is enabled for this region, the HD boundaries are ignored.
In Figure 50, the sweep region occupies 23 HD lines. After the
sweep mode region is complete, normal sequence operation
resumes in the next region. When using sweep mode, be sure to
set the region boundaries (using the sequence change positions)
to the appropriate lines to prevent the sweep operation from
overlapping the next V-sequence.
Rev. 0 | Page 42 of 100
AD9927
Multiplier Mode
Because the VTOG register is multiplied by VLEN, the resolution
of the toggle position placement is reduced. If VLEN = 4, the
toggle position precision is reduced to 4-pixel increments
instead of to single-pixel increments.
To generate very wide vertical timing pulses, a vertical region
can be configured into a multiplier region. This mode uses the
V-pattern registers in a slightly different manner. Multiplier
mode can be used to support unusual CCD timing requirements,
such as vertical pulses that are wider than the 13-bit V-pattern
toggle position counter. In general, the 13-bit toggle position
counter can be used with the sweep mode feature to support
very wide pulses; however, multiplier mode can be used to
generate even wider pulses.
Table 18 summarizes how the V-pattern group registers are used
in multiplier mode operation. In multiplier mode, the VREP
registers must always be programmed to the same value as the
highest toggle position.
Figure 51 illustrates this operation. The first toggle position is 2,
and the second toggle position is 9. In nonmultiplier mode, this
causes the V-sequence to toggle at Pixel 2 and then at Pixel 9 within
a single HD line. However, in multiplier mode toggle positions are
multiplied by the value of VLEN (in this case, 4); therefore, the first
toggle occurs at Pixel 8, and the second toggle occurs at Pixel 36.
Sweep mode has also been enabled to allow the toggle positions
to cross the HD line boundaries.
The start polarity and toggle positions are still used in the same
manner as the standard V-pattern group programming, but
VLEN is used differently. Instead of using the pixel counter
(HD counter) to specify the toggle position locations (VTOG1,
VTOG 2, VTOG 3, and VTOG 4) of the V-pattern group, the
VLEN is multiplied with the VTOG position to allow very long
pulses to be generated. To calculate the exact toggle position,
which is counted in pixels after the start position, use the
following equation:
Multiplier Mode Toggle Position = VTOG × VLEN
Table 18. Multiplier Mode Register Parameters
Register
MULTI
VPOL
VTOG
VLEN
VREP
Length
1b
1b
13b
13b
13b
Range
High/low
High/low
0 to 8191 pixel location
0 to 8191 pixels
0 to 8191 pixel location
Description
High enables multiplier mode.
Starting polarity of XV1 to XV10 signals in each V-pattern group.
Toggle positions for XV1 to XV10 signals in each V-pattern group.
Used as multiplier factor for toggle position counter.
VREP_EVEN/VREP_ODD must be set to the same value as the highest VTOG value.
START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE V-SEQUENCE REGISTERS
HD
5
3
5
VLEN
1
2
3
4
1
2
3
4
1
PIXEL
NUMBER
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
4
2
3
4
4
XV1 TO XV24
2
2
Figure 51. Example of Multiplier Region for Wide Vertical Pulse Timing
Rev. 0 | Page 43 of 100
05892-050
1
MULTIPLIER MODE V-PATTERN GROUP PROPERTIES:
1START POLARITY (STARTPOL = 0).
2FIRST, SECOND, AND THIRD TOGGLE POSITIONS (VTOG1 = 2, VTOG2 = 9).
3LENGTH OF VPAT COUNTER (VLEN = 4); THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES.
4TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (VTOG × VLEN).
5IF SWEEP REGION IS ENABLED, THE V-PULSES MAY ALSO CROSS THE HD BOUNDRIES, AS SHOWN ABOVE.
AD9927
Vertical Sensor Gate (Shift Gate) Patterns
In an interline CCD, the vertical sensor gate (VSG) pulses are
used to transfer the pixel charges from the light-sensitive image
area into light-shielded vertical registers. From the lightshielded vertical registers, the image is clocked out line-by-line
using the vertical transfer pulses (XV signals) in conjunction
with the high speed horizontal clocks. The AD9927 has 24
vertical signals, and each signal can be assigned as a VSG pulse
instead of an XV pulse.
Table 19 summarizes the VSG control registers, which are
mostly located in the field registers space (see Table 17). The
VSGSELECT register (Address 0x1C in the fixed address space)
determines which vertical outputs are assigned as VSG pulses.
When a signal is selected to be a VSG pulse, only the starting
polarity and two of the V-pattern toggle positions are used. The
VSGPATSEL register in the sequence registers is used to assign
either TOG1 and TOG2 or TOG3 and TOG4 to the VSG signal.
Note that only two of the four V-pattern toggle positions are
available when a vertical signal is selected to be a VSG pulse.
The SGACTLINE1 and SGACTLINE2 registers are used to
select which line in the field is the VSG line. The VSG active
line location is used to reference when the substrate clocking
(SUBCK) signal begins to operate in each field. For more
information, see the Substrate Clock Operation (SUBCK)
section.
Also located in the field registers, the SGMASK register selects
which individual VSG pulses are active in a given field. Therefore,
all SG patterns to be preprogrammed into the V-pattern registers
and the appropriate pulses for the different fields can be enabled
separately.
The AD9927 is an integrated AFETG + V-driver, so the
connections between the AFETG and V-driver are fixed, as
shown in Figure 53. The VSGSELECT must be programmed to
0xFF8000.
Table 19. VSG Control Registers (also see Field Registers in Table 17)
Register
VSGSELECT
(Located in Fixed
Address Space, 0x1C)
Length
24b
Range
High/low
VSGPATSEL
24b
High/low
SGMASK
24b
High/low, each VSG
SGACTLINE1
SGACTLINE2
13b
13b
0 to 8191 line no.
0 to 8191 line no.
Description
Selection of VSG signals from XV signals. Set to 1 to make signal a VSG.
[0]: XV1 selection (0 = XV pulse; 1 = VSG pulse).
[1]: XV2 selection.
…
[23]: XV24 selection.
When VSG signal is selected using the VSGSELECT register, VSGPATSEL
selects which V-pattern toggle positions are used. When set to 0, Toggle 1
and Toggle 2 are used. When set to 1, Toggle 3 and Toggle 4 are used.
[0]: XV1 selection (0 = use TOG1, TOG2; 1 = use TOG3, TOG4).
[1]: XV2 selection.
…
[23]: XV24 selection.
Set high to mask each individual VSG output.
[0]: XV1 mask.
…
[23]: XV24 mask.
Selects the line in the field where the VSG signals are active.
Selects a second line in the field to repeat the VSG signals. If not used,
set this equal to SGACTLINE1 or to the maximum value.
VD
4
HD
1
2
VSG PATTERN
Figure 52. Vertical Sensor Gate Pulse Placement
Rev. 0 | Page 44 of 100
05892-051
3
PROGRAMMABLE SETTINGS FOR EACH PATTERN:
1START POLARITY OF PULSE (FROM VPOL IN SEQUENCE REGISTERS).
2FIRST TOGGLE POSITION (FROM V-PATTERN REGISTERS).
3SECOND TOGGLE POSITION (FROM V-PATTERN REGISTERS).
4ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (FROM FIELD REGISTERS).
AD9927
INTERNAL VERTICAL DRIVER CONNECTIONS
AD9927
V-DRIVER
XV16 (XSG1)
+3V
VH, VL
J3
V1A
XV1
XV17 (XSG2)
XV18 (XSG3)
J4
H3
V1B
V2A
XV2
XV19 (XSG4)
XV20 (XSG5)
H4
G4
V2B
V3A
3-LEVEL OUTPUTS
XV3
XV21 (XSG6)
XV4
G3
F3
V3B
V4
XV22 (XSG7)
XV5
F4
V5
XV23 (XSG8)
XV6
E4
V6
XV24 (XSG9)
XV7
E3
XV8
D4
XV9
D3
XV10
D5
XV11
D6
XV12
XV13
XV14
D7
C7
C8
XV15
D8
XSUBCK
K4
XSUBCNT
H10
Figure 53. Internal AFETG to V-Driver Connections
Rev. 0 | Page 45 of 100
V7
V8
V9
V10
V11
2-LEVEL OUTPUTS
V12
V13
V14
V15
SUBCK
(3-LEVEL OUTPUT WITH XSUBCNT)
XSUBCNT (LOGIC INPUT)
05892-104
INTERNAL
TIMING
GENERATOR
AD9927
Table 20. V1A Output Polarity
Vertical Driver Input
XV1
XV16 (XSG1)
L
L
L
H
H
L
H
H
Table 26. V4 Output Polarity
V1A Output
VH
VM
VL
VL
Table 21. V1B Output Polarity
Vertical Driver Input
XV1
XV17 (XSG2)
L
L
L
H
H
L
H
H
Vertical Driver Input
XV4
XV22 (XSG7)
L
L
L
H
H
L
H
H
Table 27. V5 Output Polarity
V1B Output
VH
VM
VL
VL
Vertical Driver Input
XV5
XV23 (XSG7)
L
L
L
H
H
L
H
H
Table 22. V2A Output Polarity
Table 28. V6 Output Polarity
Vertical Driver Input
XV2
XV18 (XSG3)
L
L
L
H
H
L
H
H
Vertical Driver Input
XV6
XV24 (XSG8)
L
L
L
H
H
L
H
H
V2A Output
VH
VM
VL
VL
Table 23. V2B Output Polarity
Vertical Driver Input
XV2
XV19 (XSG4)
L
L
L
H
H
L
H
H
V2B Output
VH
VM
VL
VL
V3A Output
VH
VM
VL
VL
Table 25. V3B Output Polarity
Vertical Driver Input
XV3
XV21 (XSG6)
L
L
L
H
H
L
H
H
V5 Output
VH
VM
VL
VL
V6 Output
VH
VM
VL
VL
Table 29. V7 Output Polarity
Table 24. V3A Output Polarity
Vertical Driver Input
XV3
XV20 (XSG5)
L
L
L
H
H
L
H
H
V4 Output
VH
VM
VL
VL
V3B Output
VH
VM
VL
VL
Vertical Driver Input
XV7
L
H
V7 Output
VM
VL
Table 30. V8 Output Polarity
Vertical Driver Input
XV8
L
H
V8 Output
VM
VL
Table 31. V9 Output Polarity
Vertical Driver Input
XV9
L
H
V9 Output
VM
VL
Table 32. V10 Output Polarity
Vertical Driver Input
XV10
L
H
Rev. 0 | Page 46 of 100
V10 Output
VM
VL
AD9927
Table 33. V11 Output Polarity
Vertical Driver Input
XV11
L
H
Table 36. V14 Output Polarity
V11 Output
VM
VL
Table 34. V12 Output Polarity
Vertical Driver Input
XV12
L
H
V14 Output
VM
VL
Table 37. V15 Output Polarity
V12 Output
VM
VL
Table 35. V13 Output Polarity
Vertical Driver Input
XV13
L
H
Vertical Driver Input
XV14
L
H
Vertical Driver Input
XV15
L
H
V15 Output
VM
VL
Table 38. SUBCK Output Polarity
V13 Output
VM
VL
Vertical Driver Input
XSUBCK
XSUBCNT
L
L
L
H
H
L
H
H
Rev. 0 | Page 47 of 100
SUBCK Output
VH
VH
VMM
VLL
AD9927
XV1
XV16 (XSG1)
VH
VM
05892-105
V1A
VL
Figure 54. XV1, XV16, and V1A Output Polarities
XV1
XV17 (XSG2)
VH
VM
05892-106
V1B
VL
Figure 55. XV1, XV17, V1B Output Polarities
XV2
XV18 (XSG3)
VH
VM
05892-107
V2A
VL
Figure 56. XV2, XV18, V2A Output Polarities
XV2
XV19 (XSG4)
VH
VM
05892-108
V2B
VL
Figure 57. XV2, XV19, V2B Output Polarities
Rev. 0 | Page 48 of 100
AD9927
XV3
XV20 (XSG5)
VH
VM
05892-109
V3A
VL
Figure 58. XV3, XV20, and V3A Output Polarities
XV3
XV21 (XSG6)
VH
VM
05892-110
V3B
VL
Figure 59. XV3, XV21, and V3B Output Polarities
XV4
XV22 (XSG7)
VH
VM
05892-111
V4
VL
Figure 60. XV4, XV22, and V4 Output Polarities
XV5
XV23 (XSG8)
VH
VM
05892-112
V5
VL
Figure 61. XV5, XV23, and V5 Output Polarities
Rev. 0 | Page 49 of 100
AD9927
XV6
XV24 (XSG9)
VH
VM
05892-113
V6
VL
Figure 62. XV6, XV24, and V6 Output Polarities
XV7, X8, XV9, XV10
XV11, XV12, XV13,
XV14, XV15
05892-100
VM
V7, V8, V9, V10, V11,
V12, V13, V14, V15
VL
Figure 63. 2-Level V-Driver Output Polarities
XSUBCNT
XSUBCK
VH
VMM
05892-118
SUBCK
VLL
Figure 64. XSUBCK, XSUBCNT, and SUBCK Output Polarities
Rev. 0 | Page 50 of 100
AD9927
MODE Registers
The MODE registers are used to select the field timing of the
AD9927. Typically, all of the field, V-sequence, and V-pattern
information is programmed into the AD9927 at startup. During
operation, the MODE registers allow the user to select any combination of field timing to meet the requirements of the system.
The advantage of using the MODE registers in conjunction with
preprogrammed timing is that it greatly reduces the system programming requirements during camera operation. Only a few
register writes are required when the camera operating mode is
changed, rather than having to program all of the vertical timing
information with each camera mode change.
A basic still camera application can require six fields of vertical
timing—one for draft mode operation, one for autofocusing,
and four for still image readout. All of the register timing
information for the six fields is loaded at startup. Then, during
camera operation, the MODE registers select which field timing is
active, depending on how the camera is being used.
Table 39 shows how the MODE registers are used. The MODE
register (Address 0x2A) specifies how many total fields are
used. Any value from 1 to 7 can be selected using these three
bits. The other two registers (0x2B and 0x2C) are used to select
which of the programmed fields are used and in which order.
Up to seven fields can be used in a single MODE write. The
AD9927 starts with the field timing specified by FIELD0, and
on the next VD, switches to the timing specified by FIELD1,
and so on. After completing the total number of fields specified
by MODE, the AD9927 repeats by starting at the first field. This
continues until a new write to the MODE register occurs. Figure
67 shows example MODE register settings for different field
configurations.
Note that only a write to Address 0x2C properly resets the field
counter. Therefore, when changing the values in any of the
mode registers, it is recommended that all three registers are
updated together in the same field (VD period).
Caution
The MODE registers are SCK updated by default. If they are
configured as VD-updated registers by writing Address 0xB4 =
0x03FF and Address 0xB5 = 0xFC00, the new MODE information
is updated on the second VD falling edge after the write occurs,
rather than on the first VD falling edge. See Figure 66 for an
example.
Table 39. MODE Registers—VD Updated
Address
2A
2B
2C
Name
MODE
FIELD0
FIELD1
FIELD2
FIELD3
FIELD4
FIELD5
FIELD6
Length
3b
5b
5b
5b
5b
5b
5b
5b
Description
Total number of fields to cycle through. Set from 1 to 7.
Selected FIELD (from FIELD registers in configurable memory) for the first field to cycle through.
Selected FIELD (from FIELD registers in configurable memory) for the second field to cycle through.
Selected FIELD (from FIELD registers in configurable memory) for the third field to cycle through.
Selected FIELD (from FIELD registers in configurable memory) for the fourth field to cycle through.
Selected FIELD (from FIELD registers in configurable memory) for the fifth field to cycle through.
Selected FIELD (from FIELD registers in configurable memory) for the sixth field to cycle through.
Selected FIELD (from FIELD registers in configurable memory) for the seventh field to cycle through.
Rev. 0 | Page 51 of 100
AD9927
VD
MODE WRITE
MODE FIELD NUMBER
MODE UPDATE
A
REGISTER WRITE
4 (DRAFT)
4 (DRAFT)
0 (STILL 1ST FIELD)
1 (STILL 2ND FIELD)
2
05892-052
EXAMPLE MODE REGISTER CHANGE:
REGISTER WRITE A––WRITE TO MODE REGISTERS 0x2A, 0x2B, 0x2C TO SPECIFY
CHANGE FROM DRAFT MODE (FIELD4) TO STILL MODE (FIELD0/1/2/3).
ALSO WRITE TO VGA GAIN OR ANY NEW REGISTER VALUES NEEDED
FOR STILL FRAME OPERATION, SUCH AS NEW FIELD INFORMATION.
Figure 65. Update of MODE Register, SCK Updated (Default Setting)
VD
MODE WRITE
MODE FIELD NUMBER
MODE UPDATE
A
REGISTER WRITE
B
4 (DRAFT)
4 (DRAFT)
0 (STILL 1ST FIELD)
1 (STILL 2ND FIELD)
2
NOTES
1. NEW MODE INFORMATION IS UPDATED AT SECOND VD FALLING EDGE AFTER
SERIAL WRITE A.
05892-053
EXAMPLE MODE REGISTER CHANGE:
REGISTER WRITE A––WRITE TO MODE REGISTERS 0x2A, 0x2B, 0x2C TO SPECIFY
CHANGE FROM DRAFT MODE (FIELD4) TO STILL MODE (FIELD0/1/2/3).
REGISTER WRITE B––WRITE TO VGA GAIN OR ANY NEW REGISTER VALUES NEEDED
FOR STILL FRAME OPERATION, SUCH AS NEW FIELD INFORMATION.
Figure 66. Update of MODE Register if Changed to VD-Updated Register
EXAMPLE 1:
TOTAL FIELDS = 3, FIRST FIELD = FIELD0, SECOND FIELD = FIELD1, THIRD FIELD = FIELD2
MODE SETTINGS:
0x2A = 0x3
0x2B = 0x820
0x2C = 0x0
FIELD0
FIELD1
FIELD2
EXAMPLE 2:
TOTAL FIELDS = 1, FIRST FIELD = FIELD3
MODE SETTINGS:
0x2A = 0x1
0x2B = 0x3
0x2C = 0x0
FIELD3
EXAMPLE 3:
TOTAL FIELDS = 4, FIRST FIELD = FIELD5, SECOND FIELD = FIELD1, THIRD FIELD = FIELD4, FOURTH FIELD = FIELD2
MODE SETTINGS:
0x2A = 0x4
0x2B = 0x11025
0x2C = 0x0
FIELD1
FIELD4
FIELD2
05892-054
FIELD5
Figure 67. Using the MODE Registers to Select Field Timing
Rev. 0 | Page 52 of 100
AD9927
VERTICAL TIMING EXAMPLE
To better understand how the AD9927 vertical timing
generation is used, consider the example CCD timing chart in
Figure 68. This example illustrates a CCD using a general
3-field readout technique. As described in the previous field
section, each readout field must be divided into separate regions
to perform each step of the readout. The sequence change
positions (SCP) determine the line boundaries for each region,
and the SEQx registers assign a particular V-sequence to each
region. The V-sequences contain the specific timing
information required in each region: V1 to V6 pulses (using Vpattern groups), HBLK/CLPOB timing, and VSG patterns for
the SG active lines.
This timing example requires four regions for each of the three
fields, labeled Region 0, Region 1, Region 2, and Region 3.
Because the AD9927 allows many individual fields to be programmed, FIELD0, FIELD1, and FIELD2 can be used to meet
the requirements of this timing example. The four regions for
each field are very similar in this example, but the individual
registers for each field allow flexibility to accommodate other
timing charts.
Region 0 is a high speed, vertical shift region. Sweep mode can
be used to generate this timing operation with the desired
number of high speed vertical pulses needed to clear any charge
from the CCD’s vertical registers.
Region 1 consists of only two lines and uses standard singleline, vertical shift timing. The timing of this region area is the
same as the timing in Region 3.
Region 2 is the sensor gate line where the VSG pulses transfer
the image into the vertical CCD registers. This region might
require the use of the second V-pattern group for the SG
active line.
Region 3 also uses the standard single-line, vertical shift timing,
the same timing as Region 1. Four regions are required in each
of the three fields.
The timing for Region 1 and Region 3 is essentially the same,
reducing the complexity of the register programming. Other
registers need to be used during the actual readout operation.
These include the MODE registers, shutter control registers
(PRIMARY_ACTION, SUBCK, GPO for MSHUT, and VSUB
control) and AFE gain register.
Important Note Regarding Signal Polarities
When programming the AD9927 to generate the V1 to V24 and
SUBCK signals, the external V-driver circuit usually inverts
these signals. Carefully check the required timing signals needed
at the input and the output of the V-driver circuit being used and
adjust the polarities of the AD9927 outputs accordingly.
Rev. 0 | Page 53 of 100
Rev. 0 | Page 54 of 100
Figure 68. CCD Timing Example—Dividing Each Field into Regions
05892-055
CCD
OUT
VSUB
MSHUT
SUBCK
V6
V5
V4
V3
V2
V1
HD
VD
OPEN
REGION 0
N–5
N–2
REGION 2
REGION 3
1
4
7
10
13
16
FIELD 0
REGION 1
FIRST FIELD READOUT
CLOSED
EXPOSURE (tEXP)
REGION 0
N–4
N–1
REGION 2
REGION 3
2
5
8
11
14
17
20
FIELD 1
REGION 1
SECOND FIELD READOUT
REGION 0
N–3
N
REGION 2
REGION 3
3
6
9
12
15
18
21
FIELD 2
REGION 1
THIRD FIELD READOUT
OPEN
AD9927
AD9927
SHUTTER TIMING CONTROL
SUBCK: Low Speed Operation
The AD9927 supports the generation of electronic shuttering
(SUBCK) and also features flexible general-purpose outputs
(GPO) to control mechanical shuttering, CCD substrate bias
switching, and strobe circuitry. In the following documentation,
the terms sense gate (SG) and vertical sense gate (VSG) are used
interchangeably.
Normal and high precision shutter operations are used when
the exposure time is less than 1 field. For exposure times greater
than 1 field, the low speed (LS) shutter features can be used.
The AD9927 includes a field counter (primary field counter) to
regulate long exposure times. The primary field counter must
be activated (Address 0x70) to serve as the trigger for the LS
operation. The durations of the LS exposure and read are
specified by the SGMASK_NUM and SUBCKMASK_NUM
register (Address 0x74), respectively. As shown in Figure 71,
this mode suppresses the SUBCK and VSG outputs for up to
8192 fields (VD periods).
SUBSTRATE CLOCK OPERATION (SUBCK)
The CCD image exposure time is controlled by the substrate
clock signal (SUBCK), which pulses the CCD substrate to clear
out accumulated charge. The AD9927 supports three types of
electronic shuttering: normal, high precision, and low speed.
Along with the SUBCK pulse placement, the AD9927 can
accommodate different readout configurations to further
suppress the SUBCK pulses during multiple field readouts.
The SUBCK signal is a programmable string of pulses, each
occupying a line following the primary sense gate active line,
SGACTLINE1 (registers are shown in Table 40). The SUBCK
signal has programmable pulse width, line placement, and
number of pulses to accurately control the exposure time.
SUBCK: Normal Operation
By default, the AD9927 operates in the normal SUBCK
configuration, in which the SUBCK signal is pulsing in every
VD field (see Figure 69). The SUBCK pulse occurs once per
line, and the total number of repetitions within the field
determines the length of the exposure time. The SUBCK pulse
polarity and toggle positions within a line are programmable using
the SUBCK_POL and SUBCK_TOG1 registers (see Table 40).
The number of SUBCK pulses per field is programmed in the
SUBCKNUM register (Address 0x75).
As shown in Figure 69, the SUBCK pulses always begin in the
line following the SG-active line, which is specified in the
SGACTLINE registers for each field. The SUBCK_POL,
SUBCK_TOG1, SUBCK_TOG2, SUBCKNUM, and
SUBCKSTARTLINE registers are updated at the start of the line
after the sensor gate line, as described in the Updating New
Register Values section.
SUBCK: High Precision Operation
High precision shuttering is used in the same manner as normal
shuttering but uses an additional register to control the last
SUBCK pulse. In this mode, the SUBCK still pulses once per
line, but the last SUBCK in the field has an additional SUBCK
pulse, whose location is determined by the SUBCKHP_TOG
registers, as shown in Figure 70. Finer resolution of the exposure
time is possible using this mode. Leaving the SUBCKHP_TOG
registers set to its maximum value (0xFFFFFF) disables the last
SUBCK pulse (default setting).
To activate an LS shutter operation, trigger the start of the
exposure by writing to the PRIMARY_ACTION register bits
according to the desired effect. When the primary counter is
activated, the next VD period becomes the first active period of
the exposure for which the VSG and SUBCK masks are applied.
Optionally, if the SUBCKMASK_SKIP1 register is enabled, the
AD9927 ignores the first VSG and SUBCK masks in the
subsequent fields. This is generally desired so that the exposure
time begins in the field after the exposure operation is initiated.
Figure 71 shows operation with SUBCKMASK_SKIP1 = 1.
If the PRIMARY_ACTION register is used while the
SUBCKMASK_NUM and SGMASK_NUM registers are set to 0,
the behavior of the SUBCK and VSG signals are not different
from the normal shutter or high precision shutter operations.
Therefore, the primary field counter can be used for other tasks
(described in the General-Purpose Outputs (GPOs) section)
without disrupting the normal activity. In addition, there exists
a secondary field counter that has no effect on the SUBCK and
VSG signals. These counters are described in detail in the Field
Counters section.
SUBCK Start Line
By default, the SUBCK pulses begin in the line following
SGACTLINE1. For applications where the SUBCK pulse should
be suppressed for one or more lines following the VSG line, the
SUBCKSTARTLINE register can be programmed. This register
setting delays the start of the SUBCK pulses until the specified
number of lines following SGACTLINE1.
Caution
A value of 1 should not be used in the SUBCKSTARTLINE
register. A value of 0 is used to specify the SUBCK pulses to
begin in the next line after the SG line. A value of 2 is used to
specify the SUBCK pulses to begin two lines after the SG line,
and so on.
Rev. 0 | Page 55 of 100
AD9927
Read After Exposure
To read the CCD data after exposure, the SG should resume
normal activity while the SUBCK remains null. By default, the
AD9927 generates the VSG pulses in every field. When only a
single exposure and a single frame read is desired, such as is the
case in the preview mode, the VSG and SUBCK pulses can
operate in every field.
Other applications require that a greater number of frames are
read, in which case SUBCK must be masked until the readout is
finished. The SUBCKMASK_NUM register specifies the total
number of fields (exposure and read) to mask SUBCK. A 2-field
CCD frame read mode typically requires two additional fields of
SUBCK masking (SUBCKMASK_NUM = 2). A 3-field, 6-phase
CCD requires three additional fields of SUBCK masking after
the read begins (SUBCKMASK_NUM = 3).
Note that the SUBCKMASK_SKIP1 register setting allows
SUBCK pulses at the beginning of the field of exposure.
Table 40. SUBCK and Exposure/Read Register Parameters
Register
SGMASK_NUM
SUBCKMASK_NUM
SUBCKMASK_SKIP1
SUBCKSTARTLINE 1
Length
13b
13b
1b
13b
Range
0 to 8191 no. of fields
0 to 8191 no. of fields
On/off
0, 2 to 8191 line location
SUBCKNUM1
SG_SUPPRESS1
SUBCK_TOG1
SUBCK_TOG2
SUBCK_POL
SUBCKHP_TOG1
SUBCKHP_TOG2
13b
1b
13b
13b
1b
13b
13b
1 to 8191 no. of pulses
On/off
0 to 8191 pixel locations
0 to 8191 pixel locations
Low/high
0 to 8191 pixel locations
0 to 8191 pixel locations
1
Description
Exposure duration (number of fields to suppress VSG) for LS operation.
Exposure plus readout duration (number of fields to suppress SUBCK) for LS.
Suppress SG/SUBCK masks for one field (default = 0). Typically set to 1.
Line location to start the SUBCK pulses, relative to SGLINE location.
A value of 1 is invalid. See the SUBCK Start Line section.
Total number of SUBCKs per field, at 1 pulse per line. Must be <VDLEN.
Suppress the SG and allow SUBCK to finish at SUBCKNUM.
SUBCK Toggle Position 1.
SUBCK Toggle Position 2.
SUBCK start polarity.
Hi-precision SUBCK Toggle Position 1. Selectable as SG or VD updated.
Hi-precision SUBCK Toggle Position 2. Selectable as SG or VD updated.
Register is not VD updated but is updated at the start of the line after the sensor gate line.
Rev. 0 | Page 56 of 100
AD9927
VD
HD
VSG
tEXP
tEXP
SUBCK PROGRAMMABLE SETTINGS:
1. PULSE POLARITY USING THE SUBCK_POL REGISTER.
2. NUMBER OF PULSES WITHIN THE FIELD USING THE SUBCKNUM REGISTER (SUBCKNUM = 3 IN THE ABOVE EXAMPLE).
3. PIXEL LOCATION OF PULSE WITHIN THE LINE AND PULSE WIDTH PROGRAMMED USING THE SUBCK1 TOGGLE POSITION REGISTERS.
05892-056
SUBCK
Figure 69. Normal SUBCK Operation
VD
HD
VSG
tEXP
tEXP
NOTES
1. SECOND SUBCK PULSE IS ADDED IN THE LAST SUBCK LINE.
2. LOCATION OF SECOND PULSE IS FULLY PROGRAMMABLE USING THE SUBCKHP TOGGLE POSITION REGISTERS.
05892-057
SUBCK
Figure 70. High Precision SUBCK Operation
TRIGGER
EXPOSURE
(0x70)
VD
VSG
tEXP
NOTES
1. SUBCK CAN BE SUPPRESSED FOR MULTIPLE FIELDS BY PROGRAMMING THE EXPOSURE REGISTER TO BE GREATER THAN 0.
2. ABOVE EXAMPLE USES EXPOSURE = 1.
3. TRIGGER REGISTER MUST ALSO BE USED TO START THE LOW SPEED EXPOSURE.
4. VD/HD OUTPUTS CAN ALSO BE SUPPRESSED USING THE VDHDOFF REGISTER = 1.
Figure 71. Low Speed SUBCK Operation
Rev. 0 | Page 57 of 100
05892-058
SUBCK
AD9927
FIELD COUNTERS
The AD9927 contains three field counters (primary, secondary,
and mode). When these counters are active, they increment
with each VD cycle. The mode counter is the field counter used
with the mode register to control the vertical timing signals,
which was discussed in the
MODE Registers section. The primary and secondary counters
are more flexible and are generally used for shuttering signal
applications. Both the primary and secondary counters have
several modes of operation that are dictated by Address 0x70,
including
•
Normal (single count)
•
RapidShot (repeating count)
•
ShotDelay (delayed count)
•
ShotDelay with RapidShot
•
Manual exposure
•
Manual readout
•
Force to idle
The primary counter regulates the expose and read actions by
regulating the SUBCK and VSG signals. In addition, if the
RapidShot feature is used with the primary counter, the SUBCK
and VSG masking automatically repeats as necessary for
multiple expose/read cycles. The secondary counter has no
effect on the SUBCK or VSG signal. Both counters can be used
to regulate the general-purpose signals described in the
General-Purpose Outputs (GPOs) section.
Table 41. Primary/Secondary Field Counter Registers (Address 0x70, Address 0x71, and Address 0x72)
Register
PRIMARY_ACTION
SECOND_ACTION
Length
3b
3b
PRIMARY_MAX
SECOND_MAX
VDHD_MASK
PRIMARY_DELAY
13b
12b
3b
13b
PRIMARY_SKIP
SECOND_DELAY
1b
13b
SECOND_SKIP
1b
Description
0: idle, no counter action. GPO signals can still be controlled using polarity or GP_PROTOCOL = 1.
1: activate counter. Single cycle of counter from 1 to counter maximum value, and then returns to idle
state.
2: RapidShot. After reaching maximum counter value, counter wraps and repeats until reset.
3: ShotTimer: Active single cycle of counter after added delay of N fields (use the corresponding DELAY
register).
4: ShotTimer with RapidShot. Same as 2, with added delay of N fields between each repetition.
5: manual exposure. Primary counter stays in exposure until manual readout or reset to idle.
This mode keeps the SUBCK and VSG pulses masked indefinitely.
6: manual readout. Primary counter switches to readout (VSG pulses becomes active).
7: force to idle.
Primary counter maximum value.
Secondary counter maximum value.
Mask VD/HD during counter operation.
ShotTimer. Number of fields to delay before the next primary count (exposure) starts. If using ShotTimer
with RapidShot, delay value is used between each repeat.
When using ShotTimer with RapidShot, use primary delay value only before first count (exposure).
ShotTimer. Number of fields to delay before the next secondary count starts. If using ShotTimer with
RapidShot, delay value is used between each repeat.
When using ShotTimer with RapidShot, use secondary delay value only before first count.
Rev. 0 | Page 58 of 100
AD9927
GENERAL-PURPOSE OUTPUTS (GPOS)
For Protocol 1 (no counter association), skip Steps 3 and 4.
The AD9927 provides programmable outputs to control a
mechanical shutter, strobe/flash, the CCD bias select signal, or
any other external component with general-purpose (GP)
signals. Eight GP signals, with up to four toggles each, are
available that can be programmed and assigned to special GPO
pins. These pins are bidirectional and allow visibility (as an
output) and external control (as an input) of HBLK, PBLK,
CLPOB, and OUTCONTROL. The registers introduced in this
section are described in Table 42.
With these four steps, the GP signals can be programmed to
accomplish many common tasks. Careful protocol selection and
application of the field counters yields efficient results to allow
the GP signals smooth integration with concurrent operations.
GP Toggles
When configured as an output, each GPO1 to GPO8 output can
deliver a signal that is the result of programmable toggle
positions. The GP signals are independent and can be linked to
either a specific VD period or over a range of VD periods via
the primary or secondary field counters through the GP
protocol register (Address 0x73). As a result of their
associations with the field counters, the GP toggles inherit the
characteristics of the field counters, such as RapidShot and
ShotDelay. To use the GP toggles
1.
2.
3.
4.
Program the toggle positions (Address 0x7A to
Address 0xA9).
Program the protocol (Address 0x73).
Program the counter parameters (Address 0x71 to
Address 0x72).
Activate the counter (Address 0x70).
Note that the SUBCK and VSG masks are linked to the primary
counter; however, if their parameters are 0, the GPO can use the
primary counter without expose/read activity.
The secondary counter is independent and can be used
simultaneously with the primary counter. Some applications
may require the use of both primary and secondary field
counters with different GPO protocols, start times, and
durations. Such operations are easily handled by the AD9927.
Several simple examples of GPO applications using only one
GPO and one field counter follow. These examples can be used
as building blocks for more complex GPO activity. In addition,
specific GPO signals can be passed through a 4-input LUT to
realize combinational logic between them. For example, GP1
and GP2 can be sent through an XOR look-up table, and the
result can be delivered on GP1, GP2, or both. Also, either GP1
or GP2 can deliver their original toggles.
Table 42. GPO Registers
Register
GP1_PROTOCOL
GP2_PROTOCOL
GP3_PROTOCOL
GP4_PROTOCOL
GP5_PROTOCOL
GP6_PROTOCOL
GP7_PROTOCOL
GP8_PROTOCOL
MANUAL_TRIG
GP<1:8>_POL
SEL_GP<1:8>
Length
3b
3b
3b
3b
3b
3b
3b
8b
8b
8b
8b
Range
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
Off/on
Low/high
Off/on
GPO_OUTPUT_EN
8b
Off/on
GP*_USE_LUT
LUT_FOR_GP12
LUT_FOR_GP34
8b
4b
4b
Off/on
Logic setting
Logic setting
Description
0: idle.
1: no counter association, use MANUAL_TRIG bits to enable each GP signal.
2: link to primary counter.
3: link to secondary counter.
4: link to mode counter (from vertical timing generation).
5: primary repeat (allows GP signals to repeat with RapidShot).
6: secondary repeat (allows GP signals to repeat with RapidShot).
7: keep on.
Manual trigger for each GP signal, for use with Protocol 1.
Starting polarity for GP signals, only updated during PROTOCOL = 0.
1: select GP toggles visible at GPO1 to GPO8 when output is enabled (default);
0: select vertical signals visible at GPO4 to GPO8 when output is enabled.
GPO4: SUBCK.
GPO5: XV21.
GPO6: XV22.
GPO7: XV23.
GPO8: XV24.
1: enable GPO1 to GPO8 outputs (one bit per output);
0: disable GPO1 to GPO8 outputs, pins will be high-Z state (default).
Send GP signals through a programmable look-up table (LUT).
Desired logic to be realized on GP1 combined with GP2.
Desired logic to be realized on GP3 combined with GP4.
Rev. 0 | Page 59 of 100
AD9927
Register
LUT_FOR_GP56
LUT_FOR_GP78
Length
4b
4b
Range
Logic setting
Logic setting
GP*_TOG*_FD
GP*_TOG*_LN
GP*_TOG*_PX
GPO_INT_EN
13b
13b
13b
1b
0 to 8191 field
0 to 8191 line
0 to 8191 pixel
Off/on
Description
Desired logic to be realized on GP5 combined with GP6.
Desired logic to be realized on GP7 combined with GP8.
Example logic settings for LUT_FOR_GPxy:
0x6 = GPy XOR GPx (see Figure 77).
0x7 = GPy NAND GPx.
0x8 = GPy AND GPx.
0xE = GPy OR GPx.
Field of activity, relative to primary and secondary counter for corresponding toggle.
Line of activity for corresponding toggle.
Pixel of activity for corresponding toggle.
When set to 1, internal signals are viewable on GPO5 to GPO8.
GPO5: OUTCONTROL.
GPO6: HBLK.
GPO7: CLPOB.
GPO8: PBLK.
Rev. 0 | Page 60 of 100
AD9927
Single-Field Toggles
Scheduled Toggles
Single-field toggles occur in the next field only. There can be up to
four toggles in the field. The mode is set with GP_PROTOCOL
equal to 1, and then the toggles are triggered in the next field by
writing to the MANUAL_TRIG register (0x70 [13:6]). In this
mode, the field toggle settings must be set to a value of 1. Two
consecutive fields do not have activity. If toggles are required to
repeat in the next field, the MANUAL_TRIG register can be
written to in consecutive fields.
Scheduled toggles are programmed to occur during any
upcoming field. For example, there can be one toggle in Field 1,
two toggles in Field 3, and a last toggle in Field 4. The mode is
set with GP_PROTOCOL = 2 or GP_PROTOCOL = 3. Mode 2
tells the GPO to obey the primary field counter, and Mode 3
tells the GPO to obey the secondary field counter.
The GP toggle positions can be programmed any time prior to
use. For example,
Preparation
The GP toggle positions can be programmed any time prior to
use. For example,
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
Preparation
0x7A
0x7B
0x7C
Å 0x000A001
Å 0x0002000
Å 0x000000F
Å 0x00C4002
Å 0x0004000
Å 0x00000B3
Å 0x00C4002
Å 0x0004000
Å 0x00000B3
Details
A) Field 0:
Details
0x70
0x73
Å 0x0000008
Å 0x0000003
VD
A) Field 0:
B) Field 1:
0x70
0x73
Å 0x0000040
Å 0x0000001
0x73
Å 0x0000000
REGISTER WRITE
1
A
GP1_PROTOCOL 0
SECONDARY 0 (IDLE)
COUNT
VD
2
3
1
2
0
1
GPO1
GP1_PROTOCOL 0
A
B
1
CAUTION! THE PRIMARY COUNTER REGULATES THE SUBCK
AND VSG ACTIVITY. LINK A GPO TO THE PRIMARY COUNTER
ONLY IF IT IS TO HAPPEN DURING EXPOSURE/READ.
0
Figure 73. Scheduled Toggles Using GP_PROTOCOL = 3
NOTES
1. THE FIELD TOGGLE POSITION MUST BE SET TO 1 WHEN
GP PROTOCOL IS 1.
CAUTION! THE GP_PROTOCOL MUST BE RESET BEFORE
USING AGAIN.
05892-059
GPO1
Figure 72. Single-Field Toggles Using GP_PROTOCOL = 1
Rev. 0 | Page 61 of 100
05892-060
REGISTER WRITE
AD9927
RapidShot Sequences
ShotDelay Sequences
RapidShot technology provides continuous repetition of
scheduled toggles.
ShotDelay technology provides internal delay of scheduled
toggles. The delay is in terms of fields.
Preparation
Preparation
The GP toggle positions can be programmed any time prior to
use. For example,
The GP toggle positions can be programmed any time prior to
use. For example,
Å 0x0004000
Å 0x000A001
Å 0x0002000
Å 0x000000F
Å 0x00C4002
Å 0x0004000
Å 0x00000B3
Å 0x0000006
0x71
0x72
0x7A
0x7B
0x7C
0x73
Å 0x0004000
Å 0x000C000
Å 0x000A001
Å 0x0002000
Å 0x000000F
Å 0x0000003
Details
A) Field 0:
Details
A) Field 0:
0x70
Å 0x0000010
B) Field 2:
0x70
Å 0x0000007
Å 0x0000018
0x70
VD
REGISTER WRITE
1
VD
REGISTER WRITE
GP1_PROTOCOL 0
SECONDARY 0 (IDLE)
COUNT
2
3
4
5
A
GP1_PROTOCOL 0
B
SECONDARY 0 (IDLE)
COUNT
6
1
2
1
A
3
1
2
3
1
2
0
GPO1
2
1
2
1
Figure 75. ShotDelay Toggle Operation Using GP_PROTOCOL = 3
0
TERMINATED
AT VD EDGE
NOTES
1. THE GP PROTOCOLS ARE THE SAME AS THE SCHEDULED
TOGGLES, EXCEPT THE TOGGLES CAN BE EXCLUDED FROM
REPETITION BY CHOOSING GP PROTOCOL 2 OR 3.
CAUTION! THE FIELD COUNTER MUST BE FORCED INTO IDLE
STATE TO TERMINATE REPETITIONS.
05892-062
GPO1
Figure 74. RapidShot Toggle Operation Using GP_PROTOCOL = 6
Rev. 0 | Page 62 of 100
05892-063
0x71
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x73
AD9927
Table 43. LUT Results Based on GP1, GP2 Values
GP LOOK-UP TABLES (LUT)
The AD9927 is equipped with a look-up table for each pair of
consecutive GP signals when configured as outputs. GP1 is
always combined with GP2, GP3 is always combined with GP4,
GP5 is always combined with GP6, and GP7 is always combined
with GP8. The external GPO outputs from each pair can output
the result of the LUT or the original GP internal signal.
GP2
0
0
1
1
GP1
0
1
0
1
LUT: XOR
0
1
1
0
LUT: NAND
1
1
1
0
LUT: AND
0
0
0
1
LUT: OR
0
1
1
1
LUT_FOR_GP12[11:8] = 0x06
GP2_USE_LUT = 1 GP1_USE_LUT = 0
GP1_USE_LUT
GP1
0
GP2
GPO1
GPO2
GP1
1
GP2
1
NOTES
1. LOGIC COMBINATION (XOR) OF PROGRAMMED TOGGLES
GP1 AND GP2.
GPO2
0
Figure 77. LUT Example for GP1 XOR GP2
05892-064
GP2_USE_LUT
05892-065
GPO1
LUT
Field Counter and GPO Limitations
The following is a summary of the known limitations of the
field counters and GPO signals that dictate usability.
Figure 76. Internal LUT for GP1 and GP2 Signals
Address 0x79 dictates the behavior of the LUT and which
signals receive the result. Each 4-bit LUT_FOR_GPxy register
can realize any logic combination of GPx and GPy. For example,
Table 43 shows how the register values of LUT_FOR_GP12 [11:8]
are determined. XOR, NAND, AND, and OR results are shown,
but any 4-bit combination is possible. A simple example of XOR
gating is shown in Figure 77.
• The field counter trigger (PRIMARY_ACTION and
SECONDARY_ACTION registers, Address 0x70) is self-reset
at the start of every VD period. Therefore, there must be one
VD period between sequential programming to that address.
• If GP*_PROTOCOL = 1, it must be manually reset to
GP*_PROTOCOL = 0 one VD period before it can be
used again. If manual toggles are desired in sequential fields,
the MANUAL_TRIG register should be used in conjunction
with GP*_PROTOCOL = 1.
Rev. 0 | Page 63 of 100
AD9927
COMPLETE EXPOSURE/READOUT OPERATION
USING PRIMARY COUNTER AND GPO SIGNALS
Write to the MODE registers to configure the next five
fields. The first two fields during exposure are the same as
the current draft mode fields, and the following three fields
are the still-frame readout fields. The register settings for
the draft mode field and the three readout fields are
previously programmed. Note that if the MODE registers
are changed to VD updated, only one field of exposure
should be included (the second one) because the MODE
settings will be delayed an extra field.
Figure 78 demonstrates a typical expose/read cycle while exercising
the GPO signals. Using a 3-field CCD with an exposure time
that is greater than one field but less than two fields in duration,
requires a total of five fields for the entire exposure/readout
operation. Other exposure times and other CCD field configurations require modification of these example settings.
Note that if the MODE registers are changed to be VD updated,
as shown in the MODE Registers section and in Figure 66, the
MODE update will be delayed by one additional field. This should
be accounted for in selecting the number of fields to cycle and
which VD location to write to the MODE registers.
1.
The primary counter is used to control the masking
of VSG and SUBCK during exposure/readout. The
PRIMARY_MAX register should be set equal to the
total number of fields used for exposure and readout.
In this example, PRIMARY_MAX = 5.
The SUBCK masking should not occur immediately at
the next VD edge (Step 2), because this would define an
exposure time that begins in the previous field. Write to
the PRIMARY_DELAY register to delay the masking of
VSG and SUBCK pulses in the first exposure field. In this
example, MASKDELAY = 1.
Write to the SUBCKMASK_NUM register (Address 0x74)
to specify the number of fields to mask SUBCK while the
CCD data is read. In this example, SUBCKMASK_NUM = 4.
Write to the SGMASK_NUM register (Address 0x74) to
specify the number of fields to mask VSG outputs during
exposure. In this example, SGMASK_NUM = 1.
Write to the PRIMARY_ACTION register (Address 0x70)
to trigger the GP1 (STROBE), GP2 (MSHUT), and GP3
(VSUB) signals and to start the expose/read operation.
2.
VD/HD falling edge updates the serial writes from 1.
3.
GP3 (VSUB) output turns on at the field/line/pixel specified.
VSUB Example 1 and Example 2 use GP3TOG1_FD = 1.
4.
GP1 (STROBE) output turns on and off at the location
specified.
5.
GP2 (MSHUT) output turns off at the location specified.
6.
The next VD falling edge automatically starts the first
read field.
7.
The next VD falling edge automatically starts the second
read field.
8.
The next VD falling edge automatically starts the third
read field.
9.
Write to the MODE register to reconfigure the single draft
mode field timing. Note that if the MODE registers are
changed to VD updated, this write should occur one field
earlier.
10. VD/HD falling edge updates the serial writes from 9. VSG
outputs return to draft mode timing. SUBCK output
resumes operation. GP2 (MSHUT) output returns to the
on position (active or open). GP3 (VSUB) output returns
to the off position (inactive).
Rev. 0 | Page 64 of 100
Rev. 0 | Page 65 of 100
05892-066
CCD
OUT
VSUB
(GPO3)
MECHANICAL
SHUTTER
MSHUT
(GPO2)
STROBE
(GPO1)
SUBCK
VSG
VD
PRIMARY
COUNT
SERIAL
WRITES
DRAFT IMAGE
0 (IDLE)
1
2
3
tEXP
2
EXAMPLE 1
4
DRAFT IMAGE
1
CLOSED
EXAMPLE 2
OPEN
5
6
3
STILL IMAGE
FIRST FIELD
7
STILL IMAGE
SECOND FIELD
STILL IMAGE READOUT
4
8
5
9
STILL IMAGE
THIRD FIELD
10
10
10
10
0
OPEN
0
DRAFT IMAGE
AD9927
Figure 78. Complete Exposure/Readout Operation Using Primary Counter and GPO Signals
AD9927
Shutter Operation in SLR Mode
MANUAL SHUTTER OPERATION USING
ENHANCED SYNC MODES
Referring to Figure 84,
The AD9927 also supports an external signal to control exposure,
using the SYNC input. Generally, the SYNC input is used as an
asynchronous reset signal during master mode operation. When
the enhanced SYNC mode is enabled, the SYNC input provides
additional control of the exposure operation.
Normal SYNC Mode (Mode 1)
By default, the SYNC input is used in master mode for
synchronizing the internal counters of the AD9927 with
external timing. The SYNC During Master Mode Operation
section describes how horizontal, vertical, and field designator
signals are reset by the rising edge of the SYNC pulse. Figure 79
also shows how this mode operates, highlighting the behavior of
the mode field designator.
1.
To turn on VSUB, write to the appropriate GP registers to
trigger VSUB and start the manual exposure
[PRIMARY_ACTION = 5]. This change takes effect after
the next VD, and SUBCK is suppressed during the
exposure and readout phases.
2.
To turn on MSHUT during the interval between the next
VD and SYNC, write to the appropriate GP register. When
MSHUT is in the on position, it has line and pixel control.
This change takes effect on the SYNC falling edge since
there is an internal VD.
3.
If the MODE register is programmed to cycle through
multiple fields (5, 7, 3, 5, 7, 3, …, in this example), the internal
field designator increments. If the MODE register is not
required to increment, set up the MODE register such that it
outputs only one field. This prevents the MODE counter
from incrementing during the SYNC interval.
4.
Write to the manual readout trigger to begin the manual
readout [PRIMARY_ACTION = 6]. Write to the
appropriate GP registers to trigger MSHUT to toggle low at
the end of the exposure. This change takes effect on the
SYNC rising edge during readout. Since VD register
update is disabled, the trigger takes effect on the SYNC
rising edge. The MSHUT falling edge is aligned to the
SYNC rising edge. Because the MSHUT falling edge is
aligned with VD, it may be necessary to insert a dummy
VD to delay the readout.
Enhanced SYNC Modes (Modes 2 and 3)
The enhanced SYNC modes can be used to accommodate
unique synchronization requirements during exposure
operations. In SYNC Mode 2, the V and VSG outputs are
suspended and the VD output is masked. The V-outputs are
held at the dc value established by the Sequence 0 start polarities.
There is no SCP operation, but the H-counter is still enabled.
Finally, the AFE sampling clocks, HD, H/RG, CLPOB, HBLK,
are operational and use Sequence 0 behavior. See Figure 80 for
more details.
To enable the enhanced SYNC modes, set the register
ENH_SYNC_EN (Address 0x13 Bit [3]) to 1.
Mode 3 uses all of these features, but the V-outputs are continuous
through the SYNC pulse interval. VD control pulses are masked
during the SYNC interval, and the HD pulse can also be masked,
if required (see Figure 81).
It is important to note that in both of these enhanced modes,
the SYNC pulse resets the counters at both the falling edge and
the rising edge of the SYNC pulse.
Register Update and Field Designator
When using special SYNC Mode 2 or 3, the VD-updated
registers, such as PRIMARY_ACTION, are not updated during
the SYNC interval, and the SCP0 function is ignored and held
at 0 (see Figure 82).
When using either SYNC Mode 2 or 3, both the rising and falling
edges increment the internal field designator; therefore, the new
register data takes effect and VTP information is updated to new
SEQ0 data. However, this does not occur if the MODE register is
to create an output of one field. In that case, the region, sequence,
and group information does not change (see Figure 83).
Note that since the internal exposure counter (PRIMARY
counter) is not used during manual SYNC mode operation and
the VD register update is disabled, control is lost on the fine
placement of the GP signals for VSUB, MSHUT, and STROBE
edges while SYNC is low.
New Serial Registers
SYNC Modes 2 and 3 are controlled using the registers listed
in Table 44.
Table 44. Registers for Enhanced SYNC Modes
Register
ENH_SYNC_EN
Length
1b
SYNC_MASK_V
1b
SYNC_MASK_VD
1b
SYNC_MASK_HD
1b
Description
HI active to enable
(default LO)
HI active to enable masking
(default LO)
HI active to enable masking
(default HI)
HI active to enable masking
(default HI)
Note that registers for enhanced SYNC modes are located at
Address 0x13 Bits [6:3].
Rev. 0 | Page 66 of 100
AD9927
SYNC
VD
FIELD
DESIGNATOR
7
3
5
SUSPEND
HD
NOTES
1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0.
2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13).
3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x13).
4. THE SYNC RISING EDGE CAUSES THE INTERNAL FIELD DESIGNATOR TO INCREMENT.
5. IF SYSCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUTCONTROL = LOW.
6. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.
05892-083
H1 TO H4, RG,
XV1 TO XV24
VSG, SUBCK
Figure 79. Default Mode 1
2
1
SYNC
3
VD
VDLEN
HD
4
SCP
5
1FALLING EDGE RESYNCS THE CIRCUIT TO THE LINE/PIXEL NUMBER 0. VD AND HD INTERNALLY RESYNC.
2RISING EDGE RESETS COUNTERS.
3VD IS DISABLED DURING SYNC. THE REGISTER IS PROGRAMMABLE.
4SCP, HBLK, AND CLPOB ARE HELD AT SEQ0 VALUE.
5XV1 TO XV24 SIGNALS ARE HELD AT THE V-OUTPUT START POLARITY.
Figure 80. Enhanced SYNC Mode 2 with Vertical Signals Held at VTP Start Value
Rev. 0 | Page 67 of 100
05892-084
XV1 TO XV24
AD9927
SYNC
1
VD
VDLEN
2
HD
SCP
3
XV1 TO XV24
A NEW REGISTER. HI WILL MASK VD. DEFAULT = HI.
A NEW REGISTER. HI WILL MASK HD. DEFAULT = LO.
CONTINUE IN SEQUENCE.
05892-085
1SYNC_MASK_VD IS
2SYNC_MASK_HD IS
3V-OUTPUT PULSES
Figure 81. Enhanced SYNC Mode 3
SYNC
VD
1
1
1
1
1
1
05892-086
1VD REGISTERS ARE UPDATED HERE.
NOTES
1. VD-UPDATED REGISTERS (FOR EXAMPLE, PRIMARY_ACTION) ARE DISABLED DURING THE SYNC INTERVAL.
Figure 82. Register Update Behavior
SYNC
VD
5
7
5
3
1
1
1FIELD
DESIGNATOR IS INCREMENTED ON BOTH SYNC EDGES.
Figure 83. Special SYNC Mode Effect on Field Designator
Rev. 0 | Page 68 of 100
7
05892-087
FIELD
DESIGNATOR
AD9927
SYNC
1
4
2
VD
3
FIELD
DESIGNATOR
3
5
7
3
5
7
3
5
7
V-OUTPUTS
MSHUT
5
DRAFT
EXPOSURE
1SEE THE SHUTTER OPERATION IN SLR MODE SECTION.
2SEE THE SHUTTER OPERATION IN SLR MODE SECTION.
3SEE THE SHUTTER OPERATION IN SLR MODE SECTION.
4SEE THE SHUTTER OPERATION IN SLR MODE SECTION.
5SUBCK OUTPUT IS SUPPRESSED DURING EXPOSURE AND
5
DUMMY
FIELD
READOUT
EVEN
READOUT WHEN EXPOSURE TRIGGER IS USED.
Figure 84. Enhanced SYNC Mode—Manual Shutter Operation, SLR Mode
Rev. 0 | Page 69 of 100
READOUT
ODD
DRAFT
05892-088
VSUB
AD9927
ANALOG FRONT-END DESCRIPTION AND OPERATION
0.1µF 0.1µF
REFB REFT
0.4V
DC RESTORE
SHP
SHD
0.1µF
FIXED
DELAY
CLI
SHP
PBLK (WHEN DCBYP = 1)
1.2V
1.4V
INTERNAL
VREF
DCLK
0
DOUTPHASE
DCLK
MODE
2V FULL SCALE
6dB ~ 42dB
AD9927
1
DCLKINV
S11
CCDIN
CDS
–3dB, 0dB,
+3dB, +6dB
S21
PBLK
DAC
VGA GAIN
REGISTER
CDS GAIN
REGISTER
OUTPUT
DATA
LATCH
12-BIT
ADC
VGA
CLPOB PBLK
1S1
CLPOB
BLANK TO
ZERO OR
CLAMP LEVEL
CLAMP LEVEL
REGISTER
PBLK
VD
V-H
TIMING
GENERATION
HD
05892-067
PRECISION
TIMING
GENERATION
CLI
DOUT
OPTICAL BLACK
CLAMP
DIGITAL
FILTER
DOUTPHASE
SHP SHD
12
IS NORMALLY CLOSED; S2 IS NORMALLY OPEN.
Figure 85. Analog Front-End Functional Block Diagram
The AD9927 signal processing chain is shown in Figure 85.
Each processing step is essential for achieving a high quality
image from the raw CCD pixel data.
Note that because the CDS input is shorted during PBLK, the
CLPOB pulse should not be used during the same active time as
the PBLK pulse.
DC Restore
Correlated Double Sampler (CDS)
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.2 V, making it compatible with the 1.8 V core
supply voltage of the AD9927. The dc restore switch is active
during the SHP sample pulse time.
The CDS circuit samples each CCD pixel twice to extract the
video information and to reject low frequency noise. The
timing shown in Figure 20 illustrates how the two internally
generated CDS clocks, SHP and SHD, are used to sample the
reference level and data level of the CCD signal, respectively. The
placement of the SHP and SHD sampling edges is determined by
the setting of the SHPLOC and SHDLOC registers located at
Address 0x37. Placement of these two clock signals is critical for
achieving the best performance from the CCD.
The dc restore circuit can be disabled when the optional PBLK
signal is used to isolate large-signal swings from the CCD input
(see Analog Preblanking). Bit [6] of AFE Register Address 0x00
controls whether the dc restore is active during the PBLK interval.
Analog Preblanking
During certain CCD blanking or substrate clocking intervals,
the CCD input signal to the AD9927 can increase in amplitude
beyond the recommended input range. The PBLK signal can be
used to isolate the CDS input from large-signal swings. While
PBLK is active (low), the CDS input is internally shorted to ground.
The CDS gain is variable in three steps by using the AFE
Address 0x04: −3 dB, 0 dB (default), and +3 dB. Improved noise
performance results from using the +3 dB setting, but the input
range will be reduced (see Analog Specifications).
Rev. 0 | Page 70 of 100
AD9927
Variable Gain Amplifier
The VGA stage provides a gain range of approximately 6 dB to
42 dB, programmable with 10-bit resolution through the serial
digital interface. A gain of 6 dB is needed to match a 1 V input
signal with the ADC full-scale range of 2 V. When compared to
1 V full-scale systems, the equivalent gain range is 0 dB to 36 dB.
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain is calculated for any gain register value by
Gain (dB) = (0.0358 × Code) + 5.75 dB
where Code is the range of 0 to 1023.
42
black clamping can be disabled using Bit D2 in the AFE Register
Address 0x00. When the loop is disabled, the clamp level
register can still be used to provide fixed offset adjustment.
Note that if the CLPOB loop is disabled, higher VGA gain
settings reduce the dynamic range because the uncorrected
offset in the signal path is gained up.
The CLPOB pulse should be aligned with the CCD’s optical
black pixels. It is recommended that the CLPOB pulse duration
be at least 20 pixels wide. Shorter pulse widths can be used, but
the ability for the loop to track low frequency variations in the
black level will be reduced. See the Horizontal Clamping and
Blanking section for timing examples.
Digital Data Outputs
VGA GAIN (dB)
36
The AD9927 digital output data is latched using the rising edge
of the DOUTPHASE register value, as shown in Figure 85.
Output data timing is shown in Figure 21 and Figure 22. It is
also possible to leave the output latches transparent, so that the
data outputs are valid immediately from the ADC. Programming
the AFE Register Address 0x01, Bit D1, to 1 sets the output latches
to transparent. The data outputs can also be disabled (three-stated)
by setting the AFE Register Address 0x01, Bit D0, to 1.
30
24
18
6
0
127
255
383
511
639
767
VGA GAIN REGISTER CODE
895
1023
05892-068
12
Figure 86. VGA Gain Curve
ADC
The AD9927 uses a high performance ADC architecture
optimized for high speed and low power. Differential nonlinearity (DNL) performance is typically better than 0.5 LSB.
The ADC uses a 2 V input range. See Figure 5 and Figure 7 for
typical linearity and noise performance plots for the AD9927.
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the clamp level
register. The value can be programmed between 0 LSB and
255 LSB in 1023 steps. The resulting error signal is filtered to
reduce noise, and the correction value is applied to the ADC
input through a DAC. Normally, the optical black clamp loop is
turned on once per horizontal line, but this loop can be updated
more slowly to suit a particular application. If external digital
clamping is used during postprocessing, the AD9927 optical
The DCLK output can be used for external latching of the
data outputs. By default, the DCLK output tracks the values
of the DOUTPHASE registers. By changing the DCLKMODE
register, the DCLK output can be held at a fixed phase, and the
DOUTPHASE register values are ignored. The DCLK output can
also be inverted with respect to DOUT, using the DCLKINV
register bit.
The switching of the data outputs can couple noise back into
the analog signal path. To minimize switching noise, it is
recommended that the DOUTPHASE registers be set to the
same edge as the SHP sampling location, or up to 15 edges after
the SHP sampling location. Other settings can produce good
results, but experimentation is necessary. It is recommended
that the DOUTPHASE location not occur between the SHD
sampling location and 15 edges after the SHD location. For
example, if SHDLOC = 0, DOUTPHASE should be set to an
edge location of 16 or greater. If adjustable phase is not required
for the data outputs, the output latch can be left transparent
using Address 0x01, Bit D1.
The data output coding is normally straight binary, but the
coding can be changed to gray coding by setting the AFE
Register Address 0x01, Bit D2, to 1.
Rev. 0 | Page 71 of 100
AD9927
POWER-UP SEQUENCE FOR MASTER MODE
6.
To place the part into normal power operation, write 0x04
to register 0x00. This sets the STANDBY register (AFE
Register Address 0x00, Bits [1:0]) to normal operation and
enables the OB clamp (AFE Register Address 0x00, Bit [2]).
If the CLO output is being used to drive a crystal, also power
up the CLO oscillator by writing 1 to Address 0x15.
7.
By default, the internal timing core is held in a reset state,
with TGCORE_RSTB register = 0. Write 1 to the
TGCORE_RSTB register (Address 0x14) to start the
internal timing core operation. Note if a 2× clock is used
for the CLI input, the CLIDIVIDE register (0x0D) should
be set to 1 before resetting the timing core.
8.
Configure the AD9927 for master mode timing by writing 1
to the MASTER register (Address 0x20).
9.
Write 1 to the OUTCONTROL register (Address 0x11).
This allows the outputs to become active after the next
SYNC rising edge. Normally OUTCONTROL takes effect
after the next VD edge; however, because the part is just
being powered up, there is no VD edge until the rising
edge of the SYNC signal. Write 0xFF8000 to the
VSGSELECT register to properly configure the sensor
gate signals.
10.
Generate a SYNC event. If SYNC is high at power-up,
bring the SYNC input low for a minimum of 100 ns, and
then bring SYNC high again. This causes the internal
counters to reset and starts VD/HD operation. The first
VD/HD edge allows VD-updated register updates to
occur, including OUTCONTROL to enable all outputs.
If a hardware SYNC is not available, the SWSYNC register
(Address 0x13, Bit [14]) can be used to initiate a SYNC event.
When the AD9927 is powered up, the following sequence is
recommended (refer to Figure 87 for each step). Note that a
SYNC signal is required for master mode operation. If an
external SYNC pulse is not available, it is possible to generate an
internal SYNC event by writing to the SWSYNC register.
1.
Turn on the power supplies for AD9927 and start the
master clock, CLI.
2.
Reset the internal AD9927 registers by writing 1 to the
SW_RST register (Address 0x10).
3.
By default, Vertical Outputs V1 to V24 are low. If
necessary, write to the Standby3 output polarity
(Address 0x26) to set different polarities for the vertical
outputs in order to avoid damage to the V-driver
and CCD. Write to Address 0x1C to configure each
V-output as a vertical transfer clock (XV) or sensor
pulse (VSG).
4.
Power-up the V-driver supplies, VH and VL, anytime after
Step 3 is complete to set the proper polarities.
5.
Load the required registers to configure the necessary
vertical timing, horizontal timing, high speed timing,
and shutter timing. Set the recommended start-up
Address 0xD8 to 0x888.
Rev. 0 | Page 72 of 100
AD9927
VH SUPPLY FOR V-DRIVER
POWER 0V
SUPPLIES
4
VL SUPPLY FOR V-DRIVER
CLI
(INPUT)
2
3
5
6
7
8
9
SERIAL
WRITES
10
SYNC
(INPUT)
HD
(OUTPUT)
V1 TO V24
SUBCK
H-CLOCKS
1V
HI-Z BY
DEFAULT
FIRST FIELD
1H
HI-Z BY
DEFAULT
LOW BY
DEFAULT
HI-Z BY
DEFAULT
H2, H4, H6, H8
CLOCKS ACTIVE WHEN OUTCONTROL
REGISTER IS UPDATED AT VD/HD EDGE
H1, H3, H5, H7, RG
Figure 87. Recommended Power-Up Sequence and Synchronization, Master Mode
Rev. 0 | Page 73 of 100
05892-069
VD
(OUTPUT)
tSYNC
AD9927
Table 45. Power-Up Register Write Sequence
Power-Up and Synchronization in Slave Mode
Address
0x10
0x26
The power-up procedure for slave mode operation is the same
as the procedure for master mode operation with two exceptions:
0x20 to
0xFFF
0xD8
0x00
0x15
0x14
0x20
0x11
0x1C
0x13
Data
0x01
Userdefined
Userdefined
0x888
0x04
0x01
0x01
0x01
0x01
0xFF8000
0x4XX1
Description
Reset all registers to default values
Standby3 vertical output polarities
•
Eliminate Step 8. Do not write the part into master mode.
•
No SYNC pulse is required in slave mode. Substitute
Step 10 with starting the external VD and HD signals.
This synchronizes the part, allows the register updates,
and starts the timing operation.
Horizontal, vertical, shutter timing
Configure start-up register
Power-up the AFE, enables OB clamp
Starts CLO oscillator (if using crystal)
Starts internal timing core
Configure for master mode
Enable all outputs after SYNC
Configure sensor gate signals
SWSYNC (if using software SYNC)
When the AD9927 is used in slave mode, the VD/HD inputs are
used to synchronize the internal counters. After a falling edge of
VD, there is a latency of 36 master clock CLI edges after the
falling edge of HD until the internal H-counter is reset. The
reset operation is shown in Figure 89.
Using the SWSYNC Register
Additional Restrictions in Slave Mode
If an external SYNC pulse is not available, it is possible to
generate an internal SYNC in the AD9927 by writing 1 to the
SWSYNC register (Address 0x13, Bit [14]). If the software SYNC
option is used, the SYNC input (Pin D3) should be low (VSS)
during power-up. The SYNCENABLE register (Address 0x13,
Bit [0]) should be set high.
When operating in slave mode, the following restrictions
should be noted:
•
The HD falling edge should be located in the same CLI
clock cycle as the VD falling edge, or later than the VD
falling edge. The HD falling edge should not be located
within five cycles prior to the VD falling edge.
•
If possible, all start-up serial writes should be performed
with VD and HD disabled. This prevents unknown
behavior caused by partial updating of registers before all
information is loaded.
SYNC During Master Mode Operation
The hardware SYNC input can be used anytime during
operation to synchronize the AD9927 counters with external
timing, as shown in Figure 88. The operation of the digital
outputs can be suspended during the SYNC operation by
setting the SYNCSUSPEND register (Address 0x13, Bit [2]) to 1.
If SYNCSUSPEND = 1, the polarities of the outputs are held at
the same state as OUTCONTROL = low, as shown in Table 46.
SYNC
VD
SUSPEND
HD
NOTES
1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0.
2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13).
3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x13).
4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUTCONTROL = LOW.
5. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL THE SYNC RESET EDGE.
Figure 88. SYNC Timing to Synchronize the AD9927 with External Timing
Rev. 0 | Page 74 of 100
05892-070
H1 TO H4, RG,
XV1 TO XV24,
VSG, SUBCK
AD9927
VD
tVDHD
HD
3ns MIN
CLI
3ns MIN
tCLIDLY
SHD
INTERNAL
HD
INTERNAL
H-COUNTER
RESET
H-COUNTER
(PIXEL COUNTER)
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0
1
2
NOTES
1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, AND THEN LATCHED AGAIN BY SHD INTERNAL FALLING EDGE.
2. INTERNAL H-COUNTER IS ALWAYS RESET 35.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE.
3. DEPENDING ON THE VALUE OF SHDLOC, H-COUNTER RESET CAN OCCUR 36 OR 37 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHDLOC = 0 IS SHOWN IN ABOVE EXAMPLE. IN THIS CASE, THE H-COUNTER RESET OCCURS 36 CLI RISING EDGES AFTER HD FALLING EDGE.
5. HD FALLING EDGE SHOULD OCCUR COINCIDENT WITH VD FALLING EDGE (WITHIN SAME CLI CYCLE) OR AFTER VD FALLING EDGE. HD FALLING
EDGE SHOULD NOT OCCUR WITHIN FIVE CLI CYCLES PRIOR TO THE VD FALLING EDGE.
05892-071
35.5 CYCLES
Figure 89. External VD/HD and Internal H-Counter Synchronization, Slave Mode
PIXEL NO.
0
60
100 103
112
HD
1
2
H1
3
1HBLKTOG1
2HBLKTOG2
3CLPOB_TOG1
4CLPOB_TOG2
MASTER MODE
SLAVE MODE
60
100
103
112
(60 – 36) = 24
(100 – 36) = 64
(103 – 36) = 67
(112 – 36) = 76
4
05892-072
CLPOB
Figure 90. Example of Slave Mode Register Setting to Obtain Desired Toggle Positions
Vertical Toggle Position Placement Near Counter Reset
An additional consideration during the reset of the internal
counters is the vertical toggle position placement. Prior to the
internal counters being reset, there is a region of 36 pixels
during which no toggle positions should be programmed.
As shown in Figure 91, for master mode the last 36 pixels before
the HD falling edge must not be used for toggle position placement
of the V, VSG, SUBCK, HBLK, PBLK, or CLPOB pulses.
Figure 92 shows the same example for slave mode. The same
restriction applies: the last 36 pixels before the counters are
reset cannot be used. However, in slave mode, the counter reset
is delayed with respect to VD/HD placement, so the inhibited
area is different than it is in master mode.
It is recommended that Pixel Location 0 not be used for any of
the toggle positions for the VSG and SUBCK pulses.
Rev. 0 | Page 75 of 100
AD9927
VD
H-COUNTER
RESET
HD
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
X
X
X
X
N – 35 N – 34 N – 33 N – 32
N – 13 N – 12 N – 11 N – 10 N – 9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
0
1
2
3
4
1
2
05892-073
H-COUNTER
(PIXEL COUNTER)
NOTES
1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 36 PIXELS OF PIXEL 0 LOCATION.
Figure 91. Toggle Position Inhibited Area—Master Mode
VD
H-COUNTER
RESET
HD
H-COUNTER
(PIXEL COUNTER)
X
X
X
X
X
X
N – 35 N – 34 N – 33 N – 32
N – 13 N – 12 N – 11 N – 10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
0
NOTES
1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 36 PIXELS OF PIXEL 0 LOCATION.
05892-074
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
Figure 92. Toggle Position Inhibited Area—Slave Mode
STANDBY MODE OPERATION
The AD9927 contains three standby modes to optimize the
overall power dissipation in a particular application. Bits [1:0]
of Address 0x00 control the power-down state of the device:
• STANDBY [1:0] = 0 = normal operation (full power)
• STANDBY [1:0] = 1 = Standby1 mode
• STANDBY [1:0] = 2 = Standby2 mode
• STANDBY [1:0] = 3 = Standby3 mode (lowest power)
Table 46 summarizes the operation of each power-down mode.
The OUTCONTROL register takes priority over the Standby1
and Standby2 modes in determining the digital output states,
but Standby3 mode takes priority over OUTCONTROL.
Standby3 has the lowest power consumption and even shuts
down the crystal oscillator circuit between CLI and CLO.
Therefore, if CLI and CLO are being used with a crystal to
generate the master clock, this circuit is powered down and
there is no clock signal. When returning from Standby3 mode
to normal operation, the timing core must be reset at least
500 μs after the STANDBY register is written to. This allows
sufficient time for the crystal circuit to settle.
The vertical outputs can also be programmed to hold a specific
value during the Standby3 mode by using Address 0x26. This
register is useful during power-up if different polarities are
required by the V-driver and CCD to prevent damage when VH
and VL areas are applied. The polarities for Standby1 mode and
Standby2 mode are also programmable, using Address 0x25.
OUTCONTROL = low also uses the same polarities programmed
for Standby1 and Standby2 modes in Address 0x25. The GPO
polarities are programmable using Address 0x27.
Note that the GPO outputs are High-Z by default at power-up
until Address 0x78 is used to select them as outputs.
CLI FREQUENCY CHANGE
If the input clock CLI is interrupted or changed to a different
frequency, the timing core must be reset for proper operation.
After the CLI clock has settled to the new frequency, or the
previous frequency is resumed, write 0 and then 1 to the
TGCORE_RSTB register (Address 0x14). This guarantees that
the timing core operates properly.
Rev. 0 | Page 76 of 100
AD9927
Table 46. Standby Mode Operation (Standby Polarities for XV, XSUBCK, GPO Outputs are Programmable)
I/O Block
AFE
Timing Core
CLO Oscillator
CLO
H1
H2
H3
H4
H5
H6
H7
H8
HL
RG
VD
HD
DCLK
DOUT
XV1 to XV24
XSUBCK
GPO1 to GPO8
Standby3 (Default) 1, 2
Off
Off
Off
Low
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Low
Low
Low
Low
Low
Low
Low
OUTCONTROL = Low2
No change
No change
No change
No change
Low
High
Low
High
Low
High
Low
High
Low
Low
VDHDPOL value
VDHDPOL value
Running
Low
Low
Low
Low
1
Standby2 3, 4
Off
Off
Off
Low
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
VDHDPOL value
VDHDPOL value
Low
Low
Low
Low
Low
Standby13, 4
Only REFT, REFB on
On
On
Running
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Running
Running
Running
Low
Low
Low
Low
To exit Standby3, write 00 to STANDBY (Address 0x00, Bits [1:0]), and then reset the timing core after 500 μs to guarantee proper settling of the oscillator and external crystal.
Standby3 mode takes priority over OUTCONTROL for determining the output polarities.
3
These polarities assume OUTCONTROL = high because OUTCONTROL = low takes priority over Standby1 and Standby2.
4
Standby1 and Standby2 set H and RG drive strength to minimum value (4.3 mA).
2
Rev. 0 | Page 77 of 100
AD9927
CIRCUIT LAYOUT INFORMATION
The PCB layout is critical in achieving good image quality from
the AD9927. All of the supply pins, particularly the AVDD,
TCVDD, RGVDD, and HVDD supplies, must be decoupled to
ground with good quality high frequency chip capacitors. The
decoupling capacitors should be located as close as possible to
the supply pins and should have a very low impedance path to a
continuous ground plane. If possible, there should be a 4.7 μF
or larger value bypass capacitor for each main supply—AVDD,
HVDD, and DRVDD—although this is not necessary for each
individual pin. In most applications, the supply for RGVDD
and HVDD is shared, which can be done as long as the
individual supply pins are separately bypassed with 0.1 μF
capacitors. A separate 3 V supply can also be used for DRVDD,
but this supply pin should still be decoupled to the same ground
plane as the rest of the chip. A separate ground for DRVSS is not
recommended.
The analog bypass pins (REFT and REFB) should be carefully
decoupled to ground as close as possible to their respective pins.
The analog input (CCDIN) capacitor should be located close to
the pin.
The H1 to H8, HL, and RG traces should be designed to have
low inductance to minimize distortion of the signals. The
complementary signals, H1/H3/H5/H7 and H2/H4/H6/H8,
should be routed as close together and as symmetrically as
possible to minimize mutual inductance. Heavier PCB traces
are recommended because of the large transient current
demand on H1 to H8 by the CCD. If possible, physically
locating the AD9927 closer to the CCD reduces the inductance
on these lines. As always, the routing path should be as direct as
possible from the AD9927 to the CCD.
Typical 3 V System
The AD9927 typical circuit connections for a 3 V system are
shown in Figure 94. This application uses an external 3.3 V
supply, which is connected to the AD9927’s LDO input. The
LDO is configured to output 1.8 V for the AD9927’s core supply
by connecting the LDO1P8EN pin to 3.3 V and the LDO3P2EN
pin to ground. The LDOOUT and SENSE pins are shorted
together and used to supply 1.8 V to the AVDD, TCVDD, and
DVDD pins.
Typical 1.8 V System
The internal LDO can be disabled by tying the LDO pins to
ground (LDOIN, LDO1P8EN, LDO3P2EN, LDOOUT, and
SENSE). In this case, an external 1.8 V regulator is required to
supply 1.8 V to the AVDD, TCVDD, and DVDD pins.
All of the AD9927’s remaining supplies can be directly supplied
with 1.8 V. The internal charge pump (CP) can be used to
generate 3.3 V for the H and RG supplies.
The AD9927 typical circuit connections for a 1.8 V system are
shown in Figure 95.
External Crystal Application
The AD9927 contains an on-chip oscillator for driving an
external crystal. Figure 96 shows an example application using a
typical 27 MHz crystal. For the exact values of the external
resistors and capacitors, it is best to consult the crystal
manufacturer’s data sheet.
Note that a 2× crystal is not recommended for use with the
CLO oscillator circuit. The crystal frequency should not exceed
40 MHz.
Note that it is recommended that all H1 to H8 outputs on the
AD9927 be used together for maximum flexibility in drive
strength settings. A typical CCD with H1 and H2 inputs only
should have the AD9927’s H1, H3, H5, and H7 outputs connected
together to drive the CCD’s H1, and H2, H4, H6, and H8 outputs
connected together to drive the CCD’s H2. Similarly, a CCD
with H1, H2, H3, and H4 inputs should have the following:
• H1 and H3 connected to the CCD’s H1.
• H2 and H4 connected to the CCD’s H2.
• H5 and H7 connected to the CCD’s H3.
• H6 and H8 connected to the CCD’s H4.
Rev. 0 | Page 78 of 100
AD9927
V-Driver Power Supply Sequencing
When powering up the V-driver of the AD9927, it is important
to pay attention to the order that the various V-driver power
supplies are turned on. Particularly, a bias voltage of 2.3 V or
greater must be applied to the V5V pin prior to powering up the
VH and VL supplies. V5V is an internal voltage that eventually
rises to ~5.4 V after VH and VL are powered up; therefore, it
needs to be driven through a diode. A Schottky diode is
recommended to maximize the bias voltage on V5V. To ensure
proper operation, adhere to the following steps:
Perform any necessary writes to Registers 0x25 and 0x26
(VT_STBY12 and VT_STBY3, respectively) to define the
polarities of the V-driver outputs prior to powering up the
VH and VL supplies.
3.
Bring the signal driving the diode to V5V high. (Note that
a GPO output can be used for this operation.)
4.
After V5V reaches a minimum of 2.3 V, VH and VL can be
powered on. There are no restrictions to the order in which
VH and VL can be powered on at this time.
Connect VDD1 and VDD2 to a 3 V supply and keep V5V low.
VH
VDD
V5V
0V
VL
Figure 93. Suggested Power-Up Sequence for AD9927 V-Driver Supplies
Rev. 0 | Page 79 of 100
05892-001
1.
2.
AD9927
SERIAL INTERFACE
(FROM ASIC/DSP)
3
8
GENERAL-PURPOSE OUTPUTS
NOTE: ONE GPO IS NEEDED TO DRIVE V5V (PIN E10) THROUGH DIODE
HORIZONTAL SYNC IN/OUT
VERTICAL SYNC IN/OUT
EXTERNAL SYNC IN
EXTERNAL RESET IN
OPTIONAL CLOCK OSCILLATOR OUTPUT
(FOR CRYSTAL APPLICATION)
MASTER CLOCK INPUT (3V LOGIC)
DCLK OUTPUT
DATA OUTPUTS
0.1µF
14
0.1µF
0.1µF
RSTB
SYNC
VD
HD
SCK
SDATA
SL
GPO8
GPO7
GPO6
GPO5
GPO4
GPO3
GPO2
GPO1
CLO
CLI
REFB
REFT
CCDIN
RG
HL
H8
H7
M8
M7
M5
M3
M1
L2
F11
G11
H11
J11
M11
M10
L9
M12
L10
L11
K9
L12
K10
K11
J10
K6
K7
M9
A2
K12
H12
J8
J7
K8
E10
A1
J12
D10
J6
G9
J9
L5
E2
F10
F1
E1
F9
D2
D1
C1
B2
B1
AD9927BBCZ
NOT DRAWN TO SCALE
A11
A12
B10
B12
C6
C9
C12
D9
D12
E9
E12
B11
L6
L7
M4
H1
L1
H5, H6 TO CCD
H3, H4 TO CCD
H1, H2 TO CCD
AVSS
DVSS
TCVSS
RGVSS
HVSS1
HVSS2
LDOVSS
CPVSS
CLIVDD
LDOIN
LDO1P8EN
LDOOUT
SENSE
LDO3P2EN
CPCLI
CP1P8
CPFCB
CPFCT
CP3P3
+3V CLI SUPPLY
+3V LDO INPUT
0.1µF
DVDD
TCVDD
AVDD
0.1µF
+1.8V LDO OUT TO
AVDD, TCVDD, DVDD
+1.8V LDO OUT
0.1µF
0.1µF
0.1µF
G10
D11
C3
K3
J5
H9
C11
K5
C4
M2
C5
L3
RGVDD
HVDD1
HVDD2
0.1µF
0.1µF
+3V H, RG SUPPLY
4.7µF
6.3V
VSS1
VSS2
VM1
VM2
VMM
VDD1
VDD2
VLL
VL1
VL2
VH1
VH2
F3
F4
E4
E3
D4
D3
D5
D6
D7
C7
C8
D8
F12
G12
H6
H5
H4
H3
H2
H1
VH SUPPLY
0.1µF
25V
1.0µF
25V
0.1µF
10V
4.7µF
10V
VL SUPPLY
0.1µF
+3V SUPPLY
18
VERTICAL OUTPUT (TO CCD)
SUBCK OUTPUT (TO CCD)
XSUBCNT INPUT (FROM GPO OR TIE TO +3V)
Figure 94. Typical 3 V Circuit Configuration
Rev. 0 | Page 80 of 100
05892-101
B4
A4
B3
A3
A5
K1
J2
L8
C10
M6
L4
G2
K2
E11
C2
H4
G4
G3
GPO OUTPUT
(SEE POWER-UP
PROCEDURE)
DRVDD
IOVDD
XVVDD
TEST0
TEST1
TEST2
V5V
DRVSS
IOVSS
TEST3
TEST4
TEST5
TEST6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
H7, H8 TO CCD
J1
H2
G1
F2
H3
+3V SUPPLY
0.1µF
B6
A7
B7
A8
B8
A9
B9
A10
H10
K4
J3
J4
+3V SUPPLY
0.1µF
A6
RG TO CCD
HL TO CCD
XSUBCNT
SUBCK
V1A
V1B
V2A
V2B
V3A
V3B
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
D8
D7
D6
D5
D4
D3
D2
D1
(LSB) D0
B5
D9
D10
D11
D12
D13 (MSB)
DCLK
ANALOG OUTPUT FROM CCD
AD9927
SERIAL INTERFACE
(FROM ASIC/DSP)
3
8
GENERAL-PURPOSE OUTPUTS
NOTE: ONE GPO IS NEEDED TO DRIVE V5V (PIN E10) THROUGH DIODE
HORIZONTAL SYNC IN/OUT
VERTICAL SYNC IN/OUT
EXTERNAL SYNC IN
EXTERNAL RESET IN
OPTIONAL CLOCK OSCILLATOR OUTPUT
(FOR CRYSTAL APPLICATION)
MASTER CLOCK INPUT (3V LOGIC)
DCLK OUTPUT
DATA OUTPUTS
0.1µF
14
0.1µF
0.1µF
RSTB
SYNC
VD
HD
SCK
SDATA
SL
GPO8
GPO7
GPO6
GPO5
GPO4
GPO3
GPO2
GPO1
CLO
CLI
REFB
REFT
CCDIN
RG
HL
H8
H7
M8
M7
M5
M3
M1
L2
F11
G11
H11
J11
M11
M10
L9
M12
L10
L11
K9
L12
K10
K11
J10
K6
K7
M9
B4
A4
B3
A3
H7, H8 TO CCD
H6
H5
H4
H3
H2
H1
K1
J2
J1
H2
G1
F2
A2
K12
H12
J8
J7
K8
E10
A1
J12
D10
J6
G9
J9
NOT DRAWN TO SCALE
A11
A12
B10
B12
C6
C9
C12
D9
D12
E9
E12
F12
G12
DVDD
TCVDD
AVDD
0.1µF
B11
L6
L7
RGVDD
HVDD1
HVDD2
H1, H2 TO CCD
+1.8V CLI SUPPLY
0.1µF
0.1µF
+1.8V CP INPUT
+3V CP OUTPUT
3.3µF
0.1µF
+1.8V SUPPLY
0.1µF
0.1µF
0.1µF
+3V CP OUTPUT
4.7µF
6.3V
VSS1
VSS2
VM1
VM2
VMM
VDD1
VDD2
VLL
VL1
VL2
VH1
VH2
F3
F4
E4
E3
D4
D3
D5
D6
D7
C7
C8
D8
G10
D11
C3
K3
J5
H9
C11
K5
C4
M2
C5
L3
M4
H1
L1
H4
G4
G3
H3, H4 TO CCD
CLIVDD
LDOIN
LDO1P8EN
LDOOUT
SENSE
LDO3P2EN
CPCLI
CP1P8
CPFCB
CPFCT
CP3P3
L5
E2
F10
F1
E1
F9
D2
D1
C1
B2
B1
AD9927BBCZ
H5, H6 TO CCD
AVSS
DVSS
TCVSS
RGVSS
HVSS1
HVSS2
LDOVSS
CPVSS
L8
C10
M6
L4
G2
K2
E11
C2
H3
VH SUPPLY
0.1µF
25V
1.0µF
25V
0.1µF
10V
4.7µF
10V
VL SUPPLY
0.1µF
+3V CP OUTPUT
VERTICAL OUTPUT (TO CCD)
SUBCK OUTPUT (TO CCD)
XSUBCNT INPUT (FROM GPO OR TIE TO +3V)
Figure 95. Typical 1.8 V Circuit Configuration Using Charge Pump for HVDD and RGVDD
2MΩ
AD9927
375Ω
K6
K7
CLI
CLO
0Ω ~ 500Ω
5pF ~ 20pF
24MHz TO 36MHz
XTAL
5pF ~ 20pF
Figure 96. Crystal Application Using CLI/CLO (Consult Crystal Data Sheet for Component Values)
Rev. 0 | Page 81 of 100
05892-102
18
05892-077
GPO OUTPUT
(SEE POWER-UP
PROCEDURE)
DRVDD
IOVDD
XVVDD
TEST0
TEST1
TEST2
V5V
DRVSS
IOVSS
TEST3
TEST4
TEST5
TEST6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B6
A7
B7
A8
B8
A9
B9
A10
H10
K4
J3
J4
+3V CP OUTPUT
0.1µF
RG TO CCD
HL TO CCD
XSUBCNT
SUBCK
V1A
V1B
V2A
V2B
V3A
V3B
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
+1.8V SUPPLY
0.1µF
A6
A5
D8
D7
D6
D5
D4
D3
D2
D1
(LSB) D0
B5
D9
D10
D11
D12
D13 (MSB)
DCLK
ANALOG OUTPUT FROM CCD
AD9927
Figure 98 shows a more efficient way to write to the registers,
using the AD9927’s address autoincrement capability. Using this
method, the lowest desired address is written first, followed by
multiple 28-bit data-words. Each new 28-bit data-word is
automatically written to the next highest register address. By
eliminating the need to write each 12-bit address, faster register
loading is achieved. Continuous write operations can be used
starting with any register location.
SERIAL INTERFACE TIMING
The internal registers of the AD9927 are accessed through a
3-wire serial interface. Each register consists of a 12-bit address
and a 28-bit data-word. Both the 12-bit address and 28-bit dataword are written starting with the LSB. To write to each register,
a 40-bit operation is required, as shown in Figure 97. Although
many registers are fewer than 28 bits wide, all 28 bits must be
written for each register. For example, if the register is only 20 bits
wide, the upper eight bits are don’t cares and must be filled with
0s during the serial write operation. If fewer than 28 data bits are
written, the register is not updated with new data.
12-BIT ADDRESS
A0
SDATA
A1
A2
A3
A4
A5
A6
A7
tDS
SCK
1
2
3
4
5
A8
28-BIT DATA
A9
A10
A11
D0
D1
D2
D3
D25
D26
D27
tDH
6
7
8
9
10
11
12
13
14
15
16
38
tLS
39
40
tLH
SL
05892-078
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 40 BITS MUST BE WRITTEN: 12 BITS FOR ADDRESS AND 28 BITS FOR DATA.
3. IF THE REGISTER LENGTH IS <28 BITS, 0s MUST BE USED TO COMPLETE THE 28-BIT DATA LENGTH.
4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON THE
PARTICULAR REGISTER WRITTEN TO. SEE THE UPDATING OF NEW REGISTER VALUES SECTION FOR MORE INFORMATION.
Figure 97. Serial Write Operation
DATA FOR STARTING
REGISTER ADDRESS
SDATA
SCK
A0
1
A1
2
A2
3
A3
4
A10
11
A11
12
D0
13
D1
14
D26
DATA FOR NEXT
REGISTER ADDRESS
D27
39
40
D0
D1
41
42
D26
D27
67
68
D0
69
D1
70
D2
71
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 28-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 28-BIT DATA-WORD (ALL 28 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
Figure 98. Continuous Serial Write Operation
Rev. 0 | Page 82 of 100
05892-079
SL
AD9927
LAYOUT OF INTERNAL REGISTERS
The AD9927 address space is divided into two register areas, as
illustrated in Figure 99. In the first address space, Address 0x00
to Address 0xFF contain the registers for the AFE, miscellaneous,
VD/HD, I/O and CP, timing core, shutter and GPO, and update
control functions. The second address space, beginning at
Address 0x800, consists of the V-pattern groups, V-sequences,
and field registers. This is a configurable set of registers; the
user can decide how many V-pattern groups, V-sequences, and
fields are used in a particular design. Therefore, the addresses
for these registers vary, depending on the number of V-patterns
and V-sequences chosen.
Address 0x28 specifies the total number of V-pattern groups
and V-sequences used. The starting address for the V-pattern
groups is always 0x800. The starting address for the
V-sequences is based on the number of V-pattern groups used,
with each V-pattern group occupying 48 register addresses. The
starting address for the field registers depends on both the
number of V-pattern groups and the number of V-sequences.
Each V-sequence occupies 40 register addresses, and each field
occupies 16 register addresses.
ADDR 0x00
FIXED REGISTER AREA
The starting address for the V-sequences is equal to 0x800 plus
the number of V-pattern groups times 48. The starting address
for the fields is equal to the starting address of the V-sequences
plus the number of V-sequences times 40. The V-pattern,
V-sequence, and field registers must always occupy a
continuous block of addresses.
Figure 100 shows an example in which three V-pattern groups,
four V-sequences, and two fields are used. The starting address
for the V-pattern groups is always 0x800. Since VPATNUM = 3,
the V-pattern groups occupies 144 address locations. The start
of the V-sequence registers is 0x890 (that is, 0x800 + 144). With
VSEQNUM = 4, the V-sequences occupy 160 address locations.
Therefore, the field registers begin at 0x930 (that is, 0x890 + 160).
The AD9927 address space contains many unused addresses.
Undefined addresses between Address 0x00 and Address 0xFF
should not be written to; otherwise, the AD9927 may operate
incorrectly. Continuous register writes should be performed
carefully so that undefined registers are not written to.
VPAT START 0x800
CONFIGURABLE REGISTER AREA
AFE REGISTERS
MISCELLANEOUS REGISTERS
V-PATTERN GROUPS
VD/HD REGISTERS
I/O AND CP REGISTERS
VSEQ START
MODE REGISTERS
TIMING CORE REGISTERS
V-SEQUENCES
TEST REGISTERS
TEST REGISTERS
FIELD START
SHUTTER AND GPO REGISTERS
05892-080
FIELDS
UPDATE CONTROL REGISTERS
INVALID DO NOT ACCESS
MAX 0xFFF
ADDR 0xFF
Figure 99. Layout of AD9927 Registers
ADDR 0x800
3 V-PATTERN GROUPS
(48 × 3 = 144 REGISTERS)
ADDR 0x890
4 V-SEQUENCES
(40 × 4 = 160 REGISTERS)
ADDR 0x930
2 FIELDS
(16 × 2 = 32 REGISTERS)
UNUSED MEMORY
MAX 0xFFF
Figure 100. Example Register Configuration
Rev. 0 | Page 83 of 100
05892-081
ADDR 0x950
AD9927
• SCP Updated—At the next SCP where they are used, the
V-pattern group and V-sequence registers are updated. For
example, in Figure 101 this field has selected Region 1 to use
VSEQ3 for the vertical outputs. This means that a write to
any of the VSEQ3 registers, or any of the V-pattern group
registers, which are referenced by VSEQ3, updates at SCP1. If
multiple writes are done to the same register, the last one
done before SCP1 is the one that is updated. Likewise,
register writes to any VSEQ5 registers are updated at SCP2,
and register writes to any VSEQ8 registers are updated at
SCP3.
UPDATING NEW REGISTER VALUES
The AD9927’s internal registers are updated at different times,
depending on the particular register. Table 47 summarizes the
four register update types: SCK, VD, SG-Line, and SCP. Tables
in the Complete Register Listing section also contain an Update
Type column that identifies when each register is updated.
• SCK Updated—As soon as the 28th data bit (D27) is clocked
in, some registers are immediately updated. These registers
are used for functions that do not require gating with the next
VD boundary, such as power-up and reset functions.
• VD Updated—More registers are updated at the next VD
falling edge. By updating these values at the next VD edge,
the current field is not corrupted and the new register values
are applied to the next field. The VD update can be further
delayed past the VD falling edge by using the UPDATE
register (Address 0x17). This delays the VD-updated register
updates to any HD line in the field. Note that the field
registers are not affected by the UPDATE register.
Caution
It is recommended that the registers in the configurable address
area not be written within 36 pixels of any HD falling edge
where a sequence change position (SCP) occurs. See Figure 91
and Figure 92 for an example of what this inhibit area looks like
in master and slave modes. This restriction applies to the Vpattern, V-sequence, and field registers. As shown in Figure
101, writing to these registers before the VD falling edge
typically avoids loading these registers during SCP locations.
• SG-Line Updated—A few of the shutter registers are updated
at the HD falling edge at the start of the SG active line. These
registers control the SUBCK signal so that the SUBCK output
is not updated until the SG line occurs.
Table 47. Register Update Locations
Update Type
SCK
VD
Description
When the 28th data bit (D27) is clocked in, the register is immediately updated.
Register is updated at the VD falling edge. VD-updated registers can be delayed further by using the UPDATE register at
Address 0x17. FIELD registers are not affected by the UPDATE register.
Register is updated at the HD falling edge at the start of the SG-active line.
Register is updated at the next SCP when the register is used.
SG-Line
SCP
VD
UPDATED
SCK
UPDATED
SG
UPDATED
SCP
UPDATED
SERIAL
WRITE
VD
HD
SGLINE
VSG
USE VSEQ2
USE VSEQ3
USE VSEQ5
REGION 0
REGION 1
REGION 2
SCP0
SCP1
SCP2
USE VSEQ8
REGION 3
SCP3
Figure 101. Register Update Locations (See Table 47 for Definitions)
Rev. 0 | Page 84 of 100
SCP0
05892-082
XV1 TO XV24
AD9927
COMPLETE REGISTER LISTING
When an address contains less than 28 data bits, all remaining bits must be written as 0s.
Table 48. AFE Registers
Data
Bits
[1:0]
Default
Value
3
[2]
[3]
[4]
[5]
1
0
0
0
CLPENABLE
CLPSPEED
FASTUPDATE
PBLK_LVL
[6]
0
DCBYP
[0]
[1]
0
0
02
03
04
[2]
[3]
[0]
[23:0]
[2:0]
0
1
0
FFFFFF
0
SCK
SCK
VD
GRAY_EN
TEST
TEST
TEST
CDSGAIN
05
06
0D
[9:0]
[9:0]
[0]
F
1EC
0
VD
VD
VD
VGAGAIN
CLAMPLEVEL
CLIDIVIDE
Address
00
01
Update
Type
SCK
SCK
Name
STANDBY
DOUTDISABLE
DOUTLATCH
Description
Standby modes. 0: normal operation; 1: Standby1 mode;
2: Standby2 mode; 3: Standby3 mode.
0: disable OB clamp; 1: enable OB clamp.
0: select normal OB clamp settling; 1: select fast OB clamp settling.
0: ignore CDS gain; 1: very fast clamping when CDS gain is updated.
0: blank data outputs to 0 during PBLK;
1: blank data outputs to programmed clamp level during PBLK.
0: enable input dc restore circuit during PBLK;
1: disable input dc restore circuit during PBLK.
0: data outputs are driven; 1: data outputs are three-stated.
0: latch data outputs using the rising edge of DOUTPHASEP
(DOUTPHASEP register setting);
1: output latch is transparent.
1: enable gray encoding of the digital data outputs.
Set to 0.
Do not access, or set to 0.
Do not access, or set to 0xFFFFFF.
CDS gain setting. 0: −3 dB; 4: 0 dB; 6: +3 dB; 7: +6 dB.
All other values are invalid.
VGA gain, 6 dB to 42 dB (0.035 dB per step).
Optical black clamp level, 0 to 1023 LSB (1 LSB per step).
0: no division of CLI; 1: divide CLI input frequency by 2.
Table 49. Miscellaneous Registers
Address
10
Data
Bits
[0]
Default
Value
0
Update
Type
SCK
Name
SW_RST
11
[0]
0
VD
OUTCONTROL
12
[0]
[4:1]
[0]
0
0
1
SCK
RSTB_EN
TEST
SYNCENABLE
[1]
[2]
0
0
SYNCPOL
SYNCSUSPEND
[3]
[4]
[5]
[6]
[7]
[12:8]
[13]
[14]
[0]
0
0
1
1
0
0
0
0
0
ENH_SYNC_EN
SYNC_MASK_HD
SYNC_MASK_VD
SYNC_MASK_V
SHADOW_EN
TEST
UPDATE_SHADOW
SWSYNC
TGCORE_RSTB
13
14
SCK
SCK
Description
Software reset. Bit self-clears to 0 when a reset occurs.
1: reset Address 0x00 to Address 0xFF to default values.
0: make all outputs dc inactive; 1: enable outputs at next VD
edge.
1: configure SYNC pin as RSTB input signal.
Test mode only. Must be set to 0.
1: external synchronization enable (configures Pin D3 as an
input).
SYNC active polarity.
Suspend clocks during SYNC active pulse. 0: don’t suspend;
1: suspend.
1: enable enhanced sync/shutter operations.
1: mask HD during SYNCSUSPEND.
1: mask VD during SYNCSUSPEND.
1: mask XV outputs during SYNCSUSPEND.
1: enable use of shadow registers.
Test mode only. Must be set to 0.
1: writes to shadow bits affect shadow registers, not primary.
1: initiate software SYNC event (self-clears to 0 after SYNC).
Timing core reset bar. 0: reset TG core; 1: resume operation.
Rev. 0 | Page 85 of 100
AD9927
Address
15
Data
Bits
[0]
Default
Value
0
Update
Type
SCK
Name
OSC_RSTB
16
17
[27:0]
[12:0]
0
0
SCK
SCK
TEST
UPDATE
[13]
0
PREVENTUP
[14]
0
SYNC_RST_SHUTEN
[15]
[16]
[27:0]
[27:0]
[27:0]
[27:0]
[23:0]
[23:0]
0
0
0
0
0
A
FF0000
0
REG_RST_SHUT
GPO_RST_SYNC
TEST
TEST
TEST
TEST
VSGSELECT
VSGMASK_CTL
[24]
0
[0]
[1]
1
1
18
19
1A
1B
1C
1D
1F
SCK
SCK
SCK
SCK
SCK
SCK
VSGMASK_CTL_EN
SCK
HCNT14_EN
PBLK_MASK_EN
Description
CLO oscillator reset bar.
0: oscillator in power-down state; 1: resume oscillator
operation.
Test mode only. Must be set to 0.
Serial update line.
Sets the line (HD) within the field to update the VD-updated
registers.
Prevents the update of the VD-updated registers.
0: normal update; 1: prevent update of VD-updated registers.
1: enable reset of the shutter control after SYNC operation
occurs.
1: forces shutter control to reset.
1: reset shutter and GPO control at SYNC operation.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0xA.
Each bit selects XV pulses for use as VSG pulses.
VSG masking. Overrides settings in field registers when
enabled.
0: disable VSGMAK_CTL bits. VSG masking is controlled by field
registers.
1: enable VSGMASK_CTL bits to control VSG masking
1: enable 14-bit H-counter.
1: disable clamp operation if PBLK is active at the same time as
CLPOB.
Table 50. VD/HD Registers
Address
20
21
22
Data Bits
[0]
[0]
[12:0]
[25:13]
Default Value
0
0
0
0
Update Type
SCK
VD
VD
Name
MASTER
VDHDPOL
HDRISE
VDRISE
Description
VD/HD master or slave mode. 0: slave mode; 1: master mode.
VD/HD active polarity. 0 = low, 1 = high.
Rising edge location for HD. Minimum value is 36 pixels.
Rising edge location for VD.
Table 51. I/O and Charge Pump Registers
Address
23
Data
Bits
[0]
Default
Value
0
Update
Type
SCK
[1]
0
XV_NVR
[2]
0
IO_NVR
[3]
0
DATA_NVR
[4]
[5]
[6]
[9:7]
0
0
0
1
TEST
TEST
LDO_32_EN
HCLKMODE
Name
OSC_NVR
Description
Oscillator normal voltage range. Set to match CLIVDD supply voltage.
0 = 1.8 V, 1 = 3.3 V
XV output normal voltage range. Set to match XVVDD supply voltage.
0 = 1.8 V, 1 = 3.3 V
I/O normal voltage range. Set the match IOVDD supply voltage.
0 = 1.8 V, 1 = 3.3 V
Data pin normal voltage range. Set to match DRVDD supply voltage.
0 = 1.8 V I/O, 1 = 3.3 V I/O.
Test use only. Set to 0.
Test use only. Set to 0.
1: internal regulator enable for 3.2 V output.
Selects HCLK output configuration. Should be written to desired value.
001 = Mode 1, 010 = Mode 2, 100 = Mode 3. All other values are invalid.
Rev. 0 | Page 86 of 100
AD9927
Default
Value
0
1
0
0
0
1
0
1
1
1
1
0
0
0
1
0
Update
Type
SCK
25
Data
Bits
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[24:0]
SCK
Name
SEL_VCO
SEL_DIV
SEL_CLI
O31V
O32V
O33V
O34V
TEST
TEST
TEST
TEST
TEST
TEST
TEST
CP_PDN
VT_STBY12
26
[24:0]
0
SCK
VT_STBY3
27
[7:0]
0
SCK
GP_STDBY12
Address
24
[15:8]
GP_STDBY3
Description
1: internal CP clock select VCO.
1: internal CP clock select divided-down version of CLI (default).
1: internal CP clock select CLI.
1: CP output voltage is 3.1 V.
1: CP output voltage is 3.2 V.
1: CP output voltage is 3.3 V.
1: CP output voltage is 3.4 V.
Test use only. Use default values only.
Test use only. Use default values only.
Test use only. Use default values only.
Test use only. Use default values only.
Test use only. Use default values only.
Test use only. Use default values only.
Test use only. Use default values only.
Charge pump power-down. 1: power-down; 0: CP is running.
[23:0] Standby1 and Standby2 polarity for XV[23:0].
[24] Standby1 and Standby2 polarity for XSUBCK.
Settings also apply when OUTCONTROL = low.
[23:0] Standby3 polarity for XV [23:0].
[24] Standby3 polarity for XSUBCK.
Standby1 and Standby2 polarity for GPO [7:0].
Settings also apply when OUTCONTROL = low.
Standby3 polarity for GPO [7:0].
Table 52. Memory Configuration and MODE Registers
Address
28
2A
2B
2C
Data Bits
[4:0]
[9:5]
[2:0]
[4:0]
[9:5]
[14:10]
[19:15]
[24:20]
[4:0]
[9:5]
Default Value
0
0
0
0
0
0
0
0
0
0
Update Type
SCK
SCK
SCK
SCK
Name
VPATNUM
SEQNUM
MODE
FIELD0
FIELD1
FIELD2
FIELD3
FIELD4
FIELD5
FIELD6
Description
Total number of V-pattern groups.
Total number of V-sequences.
Total number of fields in MODE.
Selected first field in MODE.
Selected second field in MODE.
Selected third field in MODE.
Selected fourth field in MODE.
Selected fifth field in MODE.
Selected sixth field in MODE.
Selected seventh field in MODE.
Table 53. Timing Core Registers
Address
30
31
32
Data
Bits
[5:0]
[13:8]
[16]
[5:0]
[13:8]
[16]
[5:0]
[13:8]
[16]
Default
Value
0
20
1
0
20
1
0
20
1
Update
Type
SCK
SCK
SCK
Name
H1POSLOC
H1NEGLOC
H1POL
H2POSLOC
H2NEGLOC
H2POL
HLPOSLOC
HLNEGLOC
HLPOL
Description
H1 rising edge location.
H1 falling edge location.
H1 polarity control. 0: inverse of Figure 20; 1: no inversion.
H2 rising edge location (H5 in HCLK Mode 3).
H2 falling edge location (H5 in HCLK Mode 3).
H2 polarity (H5 in HCLK Mode 3). 0: inverse of Figure 20; 1: no inversion.
HL rising edge location.
HL falling edge location.
HL polarity control. 0: inverse of Figure 20; 1: no inversion.
Rev. 0 | Page 87 of 100
AD9927
Address
33
34
35
36
37
38
39
Data
Bits
[5:0]
[13:8]
[16]
[0]
[1]
Default
Value
0
10
1
0
0
[2]
[3]
[7:4]
[2:0]
0
0
4
1
[6:4]
[10:8]
[14:12]
[18:16]
[22:20]
[2:0]
[6:4]
[10:8]
[14:12]
[5:0]
[11:6]
[17:12]
[5:0]
[11:6]
1
1
1
1
1
1
1
1
1
0
20
10
0
20
[12]
[14:13]
0
0
[15]
[2:0]
0
7
Update
Type
SCK
SCK
SCK
SCK
SCK
SCK
Name
RGPOSLOC
RGNEGLOC
RGH2POL
H1HBLKRETIME
H2HBLKRETIME
HLHBLKRETIME
HL_HBLK_EN
HCLK_WIDTH
H1DRV
H2DRV
H3DRV
H4DRV
HLDRV
RGDRV
H5DRV
H6DRV
H7DRV
H8DRV
SHDLOC
SHPLOC
SHPWIDTH
DOUTPHASEP
DOUTPHASEN
DCLKMODE
DOUTDELAY
SCK
DCLKINV
CPHMASK
Description
RG rising edge location.
RG falling edge location.
RG polarity control. 0: inverse of Figure 20, 1: no inversion.
Retime H1, H2, HL HBLK to the internal clock. 0: no retime; 1: retime.
Recommended setting is retime enabled (1). Setting to 1 adds one cycle delay
to programmed HBLK positions.
Enable HBLK for HL output. 0: disable; 1: enable.
Enables wide H-clocks during HBLK interval. Set to 0 to disable.
H1 drive strength. 0: off; 1: 4.3 mA; 2: 8.6 mA; 3: 12.9 mA; 4: 4.3 mA;
5: 8.6 mA; 6: 12.9 mA; 7: 17.2 mA.
H2 drive strength (same range as H1DRV).
H3 drive strength (same range as H1DRV).
H4 drive strength (same range as H1DRV).
HL drive strength (same range as H1DRV).
RG drive strength (same range as H1DRV).
H5 drive strength (same range as H1DRV).
H6 drive strength (same range as H1DRV).
H7 drive strength (same range as H1DRV).
H8 drive strength (same range as H1DRV).
SHD sampling edge location.
SHP sampling edge location.
SHP width (controls input dc restore switch active time).
DOUT phase control, positive edge. Specifies location of DOUT.
DOUT phase control, negative edge. Always set to DOUTPHASEP plus
32 edges to maintain 50% duty cycle of internal DOUTPHASE clocking.
DCLK mode. 0: DCLK tracks DOUT; 1: DCLK phase is fixed.
Data output delay (tOD) with respect to DCLK rising edge.
0: no delay; 1: ~3 ns; 2: ~6 ns; 3: ~9 ns
Invert DCLK output. 0: no inversion, 1: inversion of DCLK.
Enable H-masking during CP operation.
Table 54. Test Registers—Do Not Access
Address
3E ~ 4F
Data Bits
Default Value
Update
Name
Description
Test registers only. Do not access.
Table 55. Test Registers—Do Not Access
Address
50 ~ 6F
Data Bits
Default Value
Update Type
Name
Description
Test registers only. Do not access.
Table 56. Shutter and GPO Registers
Address
70
Data
Bits
[2:0]
[5:3]
Default
Value
0
0
Update
Type
VD
Name
PRIMARY_ACTION
SECOND_ACTION
Description
Selects action for primary and secondary counters.
0: idle (do nothing) autoreset on VD.
1: activate counter (primary: auto exposure/readout).
2: RapidShot: wrap/repeat counter.
3: ShotTimer: delay start of count.
4: ShotTimer with RapidShot.
5: SLR exposure (manual).
Rev. 0 | Page 88 of 100
AD9927
Address
71
72
73
74
75
76
77
78
Data
Bits
Default
Value
Update
Type
[13:6]
0
[12:0]
[24:13]
[27:25]
[12:0]
0
0
0
0
[13]
0
PRIMARY_SKIP
[26:14]
[27]
[2:0]
[5:3]
[8:6]
[11:9]
[14:12]
[17:15]
[20:18]
[23:21]
0
0
0
0
0
0
0
0
0
0
SECOND_DELAY
SECOND_SKIP
GP1_PROTOCOL
GP2_PROTOCOL
GP3_PROTOCOL
GP4_PROTOCOL
GP5_PROTOCOL
GP6_PROTOCOL
GP7_PROTOCOL
GP8_PROTOCOL
[12:0]
[25:13]
[26]
0
0
1
[27]
[0]
[13:1]
0
0
0
[26:14]
[27]
[12:0]
[25:13]
[26]
[12:0]
[25:13]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
0
0
1FFF
1FFF
0
1FFF
1FFF
0
0
0
0
0
0
0
0
1
1
1
1
1
Name
MANUAL_TRIG
VD
VD
VD
VD
SG
VD
VD/SG
VD
PRIMARY_MAX
SECOND_MAX
VDHD_MASK
PRIMARY_DELAY
SGMASK_NUM
SUBCKMASK_NUM
SUBCKTOG_UPDATE
SUBCKMASK_SKIP1
TEST
SUBCKSTARTLINE
SUBCKNUM
SG_SUPPRESS
SUBCK_TOG1
SUBCK_TOG2
SUBCK_POL
SUBCKHP_TOG1
SUBCKHP_TOG2
GP1_POL
GP2_POL
GP3_POL
GP4_POL
GP5_POL
GP6_POL
GP7_POL
GP8_POL
SEL_GP1
SEL_GP2
SEL_GP3
SEL_GP4
SEL_GP5
Description
6: SLR read (manual).
7: force to idle.
1: manual trigger for GP signals, when Protocol 1 is selected.
Bit [6] : GP1 manual trigger
…
Bit [13] : GP8 manual trigger
Primary counter maximum value.
Secondary counter maximum value.
Mask VD/HD during counter operation.
Number of fields to delay before the next count (exposure) starts.
ShotTimer with RapidShot, skip delay before first count (exposure).
Number of fields to delay before the next count starts.
ShotTimer with RapidShot, skip delay before first count.
Selects protocol for each general-purpose signal.
Idle = 0.
No counter association = 1.
Link to primary = 2.
Link to secondary = 3.
Link to mode = 4.
Primary repeat = 5.
Secondary repeat = 6.
Keep on = 7.
Exposure: number of fields to mask SGs.
Exposure plus readout: number of fields to mask SUBCK.
0: SUBCK toggles (Register 0x77) updated on SG line.
1: SUBCK toggles (Register 0x77) updated on UPDATE line (VD-updated)
Skip the SUBCK mask for the first exposure field only. Typically set to 1.
Reserved for test purpose. Must be set to 0.
Line location after VSG line to begin SUBCK pulses.
Must not be set to 1.
Number of SUBCK pulses per field. Must be set less than VDLEN.
Suppress the SG and allow SUBCK to finish at SUBCKNUM.
SUBCK Toggle Position 1.
SUBCK Toggle Position 2.
SUBCK start polarity.
Hi-Precision SUBCK Toggle Position 1.
Hi-Precision SUBCK Toggle Position 2.
GP1 low/high start polarity.
GP2 low/high start polarity.
GP3 low/high start polarity.
GP4 low/high start polarity.
GP5 low/high start polarity.
GP6 low/high start polarity.
GP7 low/high start polarity.
GP8 low/high start polarity.
1 = GP1 signal is selected for GPO1 output.
1 = GP2 signal is selected for GPO2 output.
1 = GP3 signal is selected for GPO3 output.
1 = GP4 signal is selected for GPO4 output. 0 = SUBCK is selected.
1 = GP5 signal is selected for GPO5 output. 0 = XV21 is selected.
Rev. 0 | Page 89 of 100
AD9927
Address
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
Data
Bits
[13]
[14]
[15]
[23:16]
[24]
[25]
[26]
[27]
[7:0]
[11:8]
[15:12]
[19:16]
[23:20]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
Default
Value
1
1
1
0
0
0
0
0
0
{0, 0, 0, 0}
{0, 0, 0, 0}
{0, 0, 0, 0}
{0, 0, 0, 0}
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Update
Type
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
Name
SEL_GP6
SEL_GP7
SEL_GP8
GPO_OUTPUT_EN
GPO5_OVERRIDE
GPO6_OVERRIDE
GPO7_OVERRIDE
GPO8_OVERRIDE
GP[*]_USE_LUT
LUT_FOR_GP12
LUT_FOR_GP34
LUT_FOR_GP56
LUT_FOR_GP78
GP1_TOG1_FD
GP1_TOG1_LN
GP1_TOG1_PX
GP1_TOG2_FD
GP1_TOG2_LN
GP1_TOG2_PX
GP1_TOG3_FD
GP1_TOG3_LN
GP1_TOG3_PX
GP1_TOG4_FD
GP1_TOG4_LN
GP1_TOG4_PX
GP2_TOG1_FD
GP2_TOG1_LN
GP2_TOG1_PX
GP2_TOG2_FD
GP2_TOG2_LN
GP2_TOG2_PX
GP2_TOG3_FD
GP2_TOG3_LN
GP2_TOG3_PX
GP2_TOG4_FD
GP2_TOG4_LN
GP2_TOG4_PX
GP3_TOG1_FD
GP3_TOG1_LN
GP3_TOG1_PX
GP3_TOG2_FD
GP3_TOG2_LN
GP3_TOG2_PX
GP3_TOG3_FD
GP3_TOG3_LN
GP3_TOG3_PX
GP3_TOG4_FD
GP3_TOG4_LN
GP3_TOG4_PX
GP4_TOG1_FD
GP4_TOG1_LN
Description
1 = GP6 signal is selected for GPO6 output. 0 = XV22 is selected.
1 = GP7 signal is selected for GPO7 output. 0 = XV23 is selected.
1 = GP8 signal is selected for GPO8 output. 0 = XV24 is selected.
1 = GPO outputs enabled. 0 = GPO is input high-Z state (default).
1 = when GPO5 configured as input, overrides internal OUT_CONT.
1 = when GPO6 configured as input, overrides internal HBLK.
1 = when GPO7 configured as input, overrides internal CLPOB.
1 = when GPO8 configured as input, overrides internal PBLK.
Use result from LUT, or else GP* is unaltered.
Two-input look-up table results.
Examples: {LUT_FOR_GP12} Å [GP2:GP1].
{0, 1, 1, 0} = GP2 XOR GP1; {1, 1, 1, 0} = GP2 OR GP1.
{0, 1, 1, 1} = GP2 NAND GP1; {1, 0, 0, 0} = GP2 AND GP1.
General-Purpose Signal 1, first toggle position, field location.
General-Purpose Signal 1, first toggle position, line location.
General-Purpose Signal 1, first toggle position, pixel location.
General-Purpose Signal 1, second toggle position, field location.
General-Purpose Signal 1, second toggle position, line location.
General-Purpose Signal 1, second toggle position, pixel location.
General-Purpose Signal 1, third toggle position, field location.
General-Purpose Signal 1, third toggle position, line location.
General-Purpose Signal 1, third toggle position, pixel location.
General-Purpose Signal 1, fourth toggle position, field location.
General-Purpose Signal 1, fourth toggle position, line location.
General-Purpose Signal 1, fourth toggle position, pixel location.
General-Purpose Signal 2, first toggle position, field location.
General-Purpose Signal 2, first toggle position, line location.
General-Purpose Signal 2, first toggle position, pixel location.
General-Purpose Signal 2, second toggle position, field location.
General-Purpose Signal 2, second toggle position, line location.
General-Purpose Signal 2, second toggle position, pixel location.
General-Purpose Signal 2, third toggle position, field location.
General-Purpose Signal 2, third toggle position, line location.
General-Purpose Signal 2, third toggle position, pixel location.
General-Purpose Signal 2, fourth toggle position, field location.
General-Purpose Signal 2, fourth toggle position, line location.
General-Purpose Signal 2, fourth toggle position, pixel location.
General-Purpose Signal 3, first toggle position, field location.
General-Purpose Signal 3, first toggle position, line location.
General-Purpose Signal 3, first toggle position, pixel location.
General-Purpose Signal 3, second toggle position, field location.
General-Purpose Signal 3, second toggle position, line location.
General-Purpose Signal 3, second toggle position, pixel location.
General-Purpose Signal 3, third toggle position, field location.
General-Purpose Signal 3, third toggle position, line location.
General-Purpose Signal 3, third toggle position, pixel location.
General-Purpose Signal 3, fourth toggle position, field location.
General-Purpose Signal 4, fourth toggle position, line location.
General-Purpose Signal 4, fourth toggle position, pixel location.
General-Purpose Signal 4, first toggle position, field location.
General-Purpose Signal 4, first toggle position, line location.
Rev. 0 | Page 90 of 100
AD9927
Address
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
Data
Bits
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
Default
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Update
Type
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
Name
GP4_TOG1_PX
GP4_TOG2_FD
GP4_TOG2_LN
GP4_TOG2_PX
GP4_TOG3_FD
GP4_TOG3_LN
GP4_TOG3_PX
GP4_TOG4_FD
GP4_TOG4_LN
GP4_TOG4_PX
GP5_TOG1_FD
GP5_TOG1_LN
GP5_TOG1_PX
GP5_TOG2_FD
GP5_TOG2_LN
GP5_TOG2_PX
GP5_TOG3_FD
GP5_TOG3_LN
GP5_TOG3_PX
GP5_TOG4_FD
GP5_TOG4_LN
GP5_TOG4_PX
GP6_TOG1_FD
GP6_TOG1_LN
GP6_TOG1_PX
GP6_TOG2_FD
GP6_TOG2_LN
GP6_TOG2_PX
GP6_TOG3_FD
GP6_TOG3_LN
GP6_TOG3_PX
GP6_TOG4_FD
GP6_TOG4_LN
GP6_TOG4_PX
GP7_TOG1_FD
GP7_TOG1_LN
GP7_TOG1_PX
GP7_TOG2_FD
GP7_TOG2_LN
GP7_TOG2_PX
GP7_TOG3_FD
GP7_TOG3_LN
GP7_TOG3_PX
GP7_TOG4_FD
GP7_TOG4_LN
GP7_TOG4_PX
GP8_TOG1_FD
GP8_TOG1_LN
GP8_TOG1_PX
GP8_TOG2_FD
Description
General-Purpose Signal 4, first toggle position, pixel location.
General-Purpose Signal 4, second toggle position, field location.
General-Purpose Signal 4, second toggle position, line location.
General-Purpose Signal 4, second toggle position, pixel location.
General-Purpose Signal 4, third toggle position, field location.
General-Purpose Signal 4, third toggle position, line location.
General-Purpose Signal 4, third toggle position, pixel location.
General-Purpose Signal 4, fourth toggle position, field location.
General-Purpose Signal 4, fourth toggle position, line location.
General-Purpose Signal 4, fourth toggle position, pixel location.
General-Purpose Signal 5, first toggle position, field location.
General-Purpose Signal 5, first toggle position, line location.
General-Purpose Signal 5, first toggle position, pixel location.
General-Purpose Signal 5, second toggle position, field location.
General-Purpose Signal 5, second toggle position, line location.
General-Purpose Signal 5, second toggle position, pixel location.
General-Purpose Signal 5, third toggle position, field location.
General-Purpose Signal 5, third toggle position, line location.
General-Purpose Signal 5, third toggle position, pixel location.
General-Purpose Signal 5, fourth toggle position, field location.
General-Purpose Signal 5, fourth toggle position, line location.
General-Purpose Signal 5, fourth toggle position, pixel location.
General-Purpose Signal 6, first toggle position, field location.
General-Purpose Signal 6, first toggle position, line location.
General-Purpose Signal 6, first toggle position, pixel location.
General-Purpose Signal 6, second toggle position, field location.
General-Purpose Signal 6, second toggle position, line location.
General-Purpose Signal 6, second toggle position, pixel location.
General-Purpose Signal 6, third toggle position, field location.
General-Purpose Signal 6, third toggle position, line location.
General-Purpose Signal 6, third toggle position, pixel location.
General-Purpose Signal 6, fourth toggle position, field location.
General-Purpose Signal 6, fourth toggle position, line location.
General-Purpose Signal 6, fourth toggle position, pixel location.
General-Purpose Signal 7, first toggle position, field location.
General-Purpose Signal 7, first toggle position, line location.
General-Purpose Signal 7, first toggle position, pixel location.
General-Purpose Signal 7, second toggle position, field location.
General-Purpose Signal 7, second toggle position, line location.
General-Purpose Signal 7, second toggle position, pixel location.
General-Purpose Signal 7, third toggle position, field location.
General-Purpose Signal 7, third toggle position, line location.
General-Purpose Signal 7, third toggle position, pixel location.
General-Purpose Signal 7, fourth toggle position, field location.
General-Purpose Signal 7, fourth toggle position, line location.
General-Purpose Signal 7, fourth toggle position, pixel location.
General-Purpose Signal 8, first toggle position, field location.
General-Purpose Signal 8, first toggle position, line location.
General-Purpose Signal 8, first toggle position, pixel location.
General-Purpose Signal 8, second toggle position, field location.
Rev. 0 | Page 91 of 100
AD9927
Address
A6
A7
A8
A9
AA
Data
Bits
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[0]
[1]
[2]
[3]
Default
Value
0
0
0
0
0
0
0
0
0
0
0
0
Update
Type
VD
Name
GP8_TOG2_LN
GP8_TOG2_PX
GP8_TOG3_FD
GP8_TOG3_LN
GP8_TOG3_PX
GP8_TOG4_FD
GP8_TOG4_LN
GP8_TOG4_PX
SUBCK_TOG1_13
SUBCK_TOG2_13
SUBCKHP_TOG1_13
SUBCKHP_TOG2_13
VD
VD
VD
VD
VD
VD/SG
VD/SG
Description
General-Purpose Signal 8, second toggle position, line location.
General-Purpose Signal 8, second toggle position, pixel location.
General-Purpose Signal 8, third toggle position, field location.
General-Purpose Signal 8, third toggle position, line location.
General-Purpose Signal 8, third toggle position, pixel location.
General-Purpose Signal 8, fourth toggle position, field location.
General-Purpose Signal 8, fourth toggle position, line location.
General-Purpose Signal 8, fourth toggle position, pixel location.
Bit [13] for SUBCK Toggle Position 1. For 14-bit H-counter mode.
Bit [13] for SUBCK Toggle Position 2. For 14-bit H-counter mode.
Bit [13] for SUBCK HP Toggle 1. For 14-bit H-counter mode.
Bit [13] for SUBCK HP Toggle 2. For 14-bit H-counter mode.
Table 57. Update Control Registers
Address
B0
Data
Bits
[15:0]
Default Value
1803
Update
SCK
Name
AFE_UPDT_SCK
B1
[15:0]
E7FC
SCK
AFE_UPDT_VD
B2
[15:0]
F8FD
SCK
MISC_UPDT_SCK
B3
[15:0]
0702
SCK
MISC_UPDT_VD
B4
B5
[15:0]
[15:0]
FFF9
0006
SCK
SCK
VDHD_UPDT_SCK
VDHD_UPDT_VD
Description
Each bit corresponds to one address location.
AFE_UPDT_SCK [0] = 1, update Address 0x00 on SL rising edge.
AFE_UPDT_SCK [1] = 1, update Address 0x01 on SL rising edge.
…
AFE_UPDT_SCK [15] = 1, update Address 0x0F on SL rising edge.
Each bit corresponds to one address location.
AFE_UPDT_VD [0] = 1, update Address 0x00 on VD rising edge.
AFE_UPDT_VD [1] = 1, update Address 0x01 on VD rising edge.
…
AFE_UPDT_VD [15] = 1, update Address 0x0F on VD rising edge.
Enable SCK update of miscellaneous registers,
Address 0x10 to Address 0x1F.
Enable VD update of miscellaneous registers,
Address 0x10 to Address 0x1F.
Enable SCK update of VDHD registers, Address 0x20 to Address 0x2F.
Enable VD update of VDHD registers, Address 0x20 to Address 0x2F.
Table 58. Extra Registers
Address
D4
Data Bits
[0]
[1]
Default Value
0
0
Update
SCK
Name
TEST
GPO_INT_EN
D7
[9:2]
[0]
[1]
0
0
0
SCK
TEST
TEST
XV24_SWAP
D8
[27:0]
0
SCK
START
Description
Test use only. Set to 0.
Allow observation of internal signals at GPO5 to GPO8 outputs.
GPO5: OUTCONTROL.
GPO6: HBLK.
GPO7: CLPOB.
GPO8: PBLK.
Test use only. Set to 0.
Test use only. Set to 0.
Set to 1 to change the V-driver output configuration so that XV15 is
output on the XV24 output pin. Useful with special vertical
sequence alternation mode when the XV24 register is reserved for
pattern selection.
Recommended start-up register. Should be set to 0x888.
Rev. 0 | Page 92 of 100
AD9927
Table 59. V-Pattern Group (VPAT) Register Map
Address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
Data Bits
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
Default Value
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Update Type
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
Rev. 0 | Page 93 of 100
Name
XV1TOG1
XV1TOG2
XV1TOG3
XV1TOG4
XV2TOG1
XV2TOG2
XV2TOG3
XV2TOG4
XV3TOG1
XV3TOG2
XV3TOG3
XV3TOG4
XV4TOG1
XV4TOG2
XV4TOG3
XV4TOG4
XV5TOG1
XV5TOG2
XV5TOG3
XV5TOG4
XV6TOG1
XV6TOG2
XV6TOG3
XV6TOG4
XV7TOG1
XV7TOG2
XV7TOG3
XV7TOG4
XV8TOG1
XV8TOG2
XV8TOG3
XV8TOG4
XV9TOG1
XV9TOG2
XV9TOG3
XV9TOG4
XV10TOG1
XV10TOG2
XV10TOG3
XV10TOG4
XV11TOG1
XV11TOG2
XV11TOG3
XV11TOG4
XV12TOG1
XV12TOG2
XV12TOG3
XV12TOG4
XV13TOG1
XV13TOG2
Description
XV1 Toggle Position 1.
XV1 Toggle Position 2.
XV1 Toggle Position 3.
XV1 Toggle Position 4.
XV2 Toggle Position 1.
XV2 Toggle Position 2.
XV2 Toggle Position 3.
XV2 Toggle Position 4.
XV3 Toggle Position 1.
XV3 Toggle Position 2.
XV3 Toggle Position 3.
XV3 Toggle Position 4.
XV4 Toggle Position 1.
XV4 Toggle Position 2.
XV4 Toggle Position 3.
XV4 Toggle Position 4.
XV5 Toggle Position 1.
XV5 Toggle Position 2.
XV5 Toggle Position 3.
XV5 Toggle Position 4.
XV6 Toggle Position 1.
XV6 Toggle Position 2.
XV6 Toggle Position 3.
XV6 Toggle Position 4.
XV7 Toggle Position 1.
XV7 Toggle Position 2.
XV7 Toggle Position 3.
XV7 Toggle Position 4.
XV8 Toggle Position 1.
XV8 Toggle Position 2.
XV8 Toggle Position 3.
XV8 Toggle Position 4.
XV9 Toggle Position 1.
XV9 Toggle Position 2.
XV9 Toggle Position 3.
XV9 Toggle Position 4.
XV10 Toggle Position 1.
XV10 Toggle Position 2.
XV10 Toggle Position 3.
XV10 Toggle Position 4.
XV11 Toggle Position 1.
XV11 Toggle Position 2.
XV11 Toggle Position 3.
XV11 Toggle Position 4.
XV12 Toggle Position 1.
XV12 Toggle Position 2.
XV12 Toggle Position 3.
XV12 Toggle Position 4.
XV13 Toggle Position 1.
XV13 Toggle Position 2.
AD9927
Address
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
Data Bits
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
Default Value
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Update Type
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
Rev. 0 | Page 94 of 100
Name
XV13TOG3
XV13TOG4
XV14TOG1
XV14TOG2
XV14TOG3
XV14TOG4
XV15TOG1
XV15TOG2
XV15TOG3
XV15TOG4
XV16TOG1
XV16TOG2
XV16TOG3
XV16TOG4
XV17TOG1
XV17TOG2
XV17TOG3
XV17TOG4
XV18TOG1
XV18TOG2
XV18TOG3
XV18TOG4
XV19TOG1
XV19TOG2
XV19TOG3
XV19TOG4
XV20TOG1
XV20TOG2
XV20TOG3
XV20TOG4
XV21TOG1
XV21TOG2
XV21TOG3
XV21TOG4
XV22TOG1
XV22TOG2
XV22TOG3
XV22TOG4
XV23TOG1
XV23TOG2
XV23TOG3
XV23TOG4
XV24TOG1
XV24TOG2
XV24TOG3
XV24TOG4
Description
XV13 Toggle Position 3.
XV13 Toggle Position 4.
XV14 Toggle Position 1.
XV14 Toggle Position 2
XV14 Toggle Position 3.
XV14 Toggle Position 4.
XV15 Toggle Position 1.
XV15 Toggle Position 2.
XV15 Toggle Position 3.
XV15 Toggle Position 4.
XV16 Toggle Position 1.
XV16 Toggle Position 2.
XV16 Toggle Position 3.
XV16 Toggle Position 4.
XV17 Toggle Position 1.
XV17 Toggle Position 2.
XV17 Toggle Position 3.
XV17 Toggle Position 4.
XV18 Toggle Position 1.
XV18 Toggle Position 2.
XV18 Toggle Position 3.
XV18 Toggle Position 4.
XV19 Toggle Position 1.
XV19 Toggle Position 2.
XV19 Toggle Position 3.
XV19 Toggle Position 4.
XV20 Toggle Position 1.
XV20 Toggle Position 2.
XV20 Toggle Position 3.
XV20 Toggle Position 4.
XV21 Toggle Position 1.
XV21 Toggle Position 2.
XV21 Toggle Position 3.
XV21 Toggle Position 4.
XV22 Toggle Position 1.
XV22 Toggle Position 2.
XV22 Toggle Position 3.
XV22 Toggle Position 4.
XV23 Toggle Position 1.
XV23 Toggle Position 2.
XV23 Toggle Position 3.
XV23 Toggle Position 4.
XV24 Toggle Position 1.
XV24 Toggle Position 2.
XV24 Toggle Position 3.
XV24 Toggle Position 4.
AD9927
Table 60. V-Sequence (VSEQ) Registers
Data
Bits
[0]
[1]
[5:2]
[9:6]
[13:10]
Default
Value
X
X
X
X
X
[15:14]
X
VREP_MODE
[19:16]
[23:20]
[25:24]
X
X
X
LASTREPLEN_EN
LASTTOG_EN
HBLK_MODE
02
[12:0]
[25:13]
[23:0]
X
X
X
03
04
05
06
07
[24]
[25]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
08
09
Address
00
01
0A
0B
0C
0D
0E
Update
Type
SCP
SCP
Name
CLPOBPOL
PBLKPOL
HOLD
VMASK_EN
CONCAT_GRP
SCP
HDLENE
HDLENO
VSGPATSEL
X
X
X
X
X
SCP
SCP
SCP
SCP
SCP
HDLENE_13
HDLENO_13
VPOL_A
VPOL_B
VPOL_C
VPOL_D
GROUPSEL_0
[23:0]
X
SCP
GROUPSEL_1
[4:0]
[9:5]
[14:10]
[19:15]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SCP
VPATSELA
VPATSELB
VPATSELC
VPATSELD
VSTARTA
VLENA
VREPA_1
VREPA_2
VREPA_3
VREPA_4
VSTARTB
VLENB
VREPB_ODD
VREPB_EVEN
SCP
SCP
SCP
SCP
SCP
Description
CLPOB start polarity.
PBLK start polarity.
1 = enable HOLD function for each VPAT group (A, B, C, D).
1 = enable FREEZE/RESUME for each VPAT group (A, B, C, D).
Combine multiple VPAT groups together in one sequence. Set register
equal to 0x01 to enable.
Defines V-alternation repetition mode.
00 = single pattern alternation for all groups.
01 = two pattern alternation for all groups.
10 = three-pattern alternation for Group A. Groups B, C, and D
follow pattern {0, 1, 1, 0, 1, 1…}.
11 = four-pattern alternation for Group A. Two-pattern alternation
for Groups B, C, and D.
Enable use of last repetition counter for last repetition length of each group.
Enable the fifth toggle position for all V-signals in each group.
Selection of HBLK modes.
00 = HBLK Mode 0 (normal six-toggle operation).
01 = HBLK Mode 1.
10 = HBLK Mode 2. (Address 0x19 to Address 0x1E operate differently.)
11 = test only, do not access.
HD line length for even lines.
HD line length for odd lines.
Selects which two toggle positions are used by each V-output when they
are configured as VSG pulses (Miscellaneous Register Address 0x1C, fixed
register area).
0 = use Toggles 1, 2; 1 = use Toggles 3, 4.
HD length Bit [13] for even lines when 14-bit H-counter is enabled.
HD length Bit [13] for odd lines when 14-bit H-counter is enabled.
Starting polarities for each V-output signal (Group A).
Starting polarities for each V-output signal (Group B).
Starting polarities for each V-output signal (Group C).
Starting polarities for each V-output signal (Group D).
Select which group each XV1 ~ XV12 signal is assigned to.
00 = Group A, 01 = Group B, 10 = Group C, 11 = Group D.
[1:0]: XV1; [3:2]: XV2 … [23:22]: XV12.
Select which group each XV13 ~ XV24 signal is assigned to.
00 = Group A, 01 = Group B, 10 = Group C, 11 = Group D.
[1:0]: XV13; [3:2]: XV14 … [23:22]: XV24.
Selected VPAT group for Group A, from VPAT Group 0 ~ 31.
Selected VPAT group for Group B, from VPAT Group 0 ~ 31.
Selected VPAT group for Group C, from VPAT Group 0 ~ 31.
Selected VPAT group for Group D, from VPAT Group 0 ~ 31.
Start position of selected V-Pattern Group A.
Length of selected V-Pattern Group A.
Number of repetitions for V-Pattern Group A for first lines.
Number of repetitions for V-Pattern Group A for second lines.
Number of repetitions for V-Pattern Group A for third lines.
Number of repetitions for V-Pattern Group A for fourth lines.
Start position of selected V-Pattern Group B.
Length of selected V-Pattern Group B.
Number of repetitions for V-Pattern Group B for odd lines.
Number of repetitions for V-Pattern Group B for even lines.
Rev. 0 | Page 95 of 100
AD9927
Address
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
Data
Bits
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[20:13]
[21]
[22]
[23]
[25:24]
[12:0]
Default
Value
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Update
Type
SCP
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
X
X
X
X
X
X
X
X
X
X
X
X
[25:13]
X
[12:0]
X
[13]
[14]
X
X
VSEQALT_EN
VALT_MAP
[17:15]
X
SPC_PAT_EN
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
Name
VSTARTC
VLENC
VREPC_ODD
VREPC_EVEN
VSTARTD
VLEND
VREPD_ODD
VREPD_EVEN
FREEZE1
RESUME1
FREEZE2
RESUME2
FREEZE3
RESUME3
FREEZE4
RESUME4
HBLKSTART
HBLKEND
HBLKLEN
HBLKREP
HBLKMASK_H1
HBLKMASK_H2
HBLKMASK_HL
TEST
HBLKTOGO1
HBLKTOGO2
HBLKTOGO3
HBLKTOGO4
HBLKTOGO5
HBLKTOGO6
HBLKTOGE1
HBLKTOGE2
HBLKTOGE3
HBLKTOGE4
HBLKTOGE5
HBLKTOGE6
HBLKSTARTA
HBLKSTARTB
SCP
HBLKSTARTC
Description
Start position of selected V-Pattern Group C.
Length of selected V-Pattern Group C.
Number of repetitions for V-Pattern Group C for odd lines.
Number of repetitions for V-Pattern Group C for even lines.
Start position of selected V-Pattern Group D.
Length of selected V-Pattern Group D.
Number of repetitions for V-Pattern Group D for odd lines.
Number of repetitions for V-Pattern Group D for even lines.
Holds the V-outputs at their current levels.
Resumes the operation of V-outputs to finish the pattern.
Holds the V-outputs at their current levels.
Resumes the operation of V-outputs to finish the pattern.
Holds the V-outputs at their current levels.
Resumes the operation of V-outputs to finish the pattern.
Holds the V-outputs at their current levels.
Resumes the operation of V-outputs to finish the pattern.
Start location for HBLK in HBLK Modes 1 and 2.
End location for HBLK in HBLK Modes 1 and 2.
HBLK length in HBLK Modes 1 and 2.
Number of HBLK repetitions in HBLK Modes 1 and 2.
Masking polarity for H1/H3/H5/H7 during HBLK.
Masking polarity for H2/H4/H6/H8 during HBLK.
Masking polarity for HL during HBLK.
Test use only. Set to 0.
First HBLK toggle position for odd lines, or RA0H1REPABC in HBLK Mode 2
(see HBLK Mode 2 Operation for more information).
Second HBLK toggle position for odd lines, or RA1H1REPABC.
Third HBLK toggle position for odd lines, or RA2H1REPABC.
Fourth HBLK toggle position for odd lines, or RA3H1REPABC.
Fifth HBLK toggle position for odd lines, or RA4H1REPABC.
Sixth HBLK toggle position for odd lines, or RA5H1REPABC.
First HBLK toggle position for even lines, or RA0H2REPABC.
Second HBLK toggle position for even lines, or RA1H2REPABC.
Third HBLK toggle position for even lines, or RA2H2REPABC.
Fourth HBLK toggle position for even lines, or RA3H2REPABC.
Fifth HBLK toggle position for even lines, or RA4H2REPABC.
Sixth HBLK toggle position for even lines, or RA5H2REPABC.
HBLK Repeat Area Start Position A for HBLK Mode 2. Set to 8191 if not
used.
HBLK Repeat Area Start Position B for HBLK Mode 2. Set to 8191 if not
used.
HBLK Repeat Area Start Position C for HBLK Mode 2. Set to 8191 if not
used.
Special V-sequence alternation enable.
1= enables operation of VALTSEL0_EVEN/ODD, VALTSEL1_EVEN/ODD
registers in FREEZE/RESUME registers. Must be enabled if special VALT
mode is used.
1 = enables use of special vertical pattern insertion into VPATA sequence.
[0]: use VPATB as the special pattern.
[1]: use VPATC as the special pattern.
[2]: use VPATD as the special pattern.
Rev. 0 | Page 96 of 100
AD9927
Address
21
22
23
24
25
26
27
Data
Bits
[2:0]
[6:4]
[10:8]
[14:12]
[18:16]
[22:20]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
Default
Value
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Update
Type
SCP
SCP
SCP
SCP
SCP
SCP
SCP
Name
HBLKALT_PAT1
HBLKALT_PAT2
HBLKALT_PAT3
HBLKALT_PAT4
HBLKALT_PAT5
HBLKALT_PAT6
CLPOBTOG1
CLPOBTOG2
PBLKTOG1
PBLKTOG2
LASTREPLEN_A
LASTREPLEN_B
LASTREPLEN_C
LASTREPLEN_D
LASTTOG_A
LASTTOG_B
LASTTOG_C
LASTTOG_D
Description
HBLK Mode 2, Repeat Area 0 pattern for odd lines.
HBLK Mode 2, Repeat Area 0 pattern for odd lines.
HBLK Mode 2, Repeat Area 0 pattern for odd lines.
HBLK Mode 2, Repeat Area 0 pattern for odd lines.
HBLK Mode 2, Repeat Area 0 pattern for odd lines.
HBLK Mode 2, Repeat Area 0 pattern for odd lines.
CLPOB Toggle Position 1.
CLPOB Toggle Position 2.
PBLK Toggle Position 1.
PBLK Toggle Position 2.
Last repetition length for Group A. Set equal to VLENA.
Last repetition length for Group B. Set equal to VLENB.
Last repetition length for Group C. Set equal to VLENC.
Last repetition length for Group D. Set equal to VLEND.
Optional fifth toggle position for Group A.
Optional fifth toggle position for Group B.
Optional fifth toggle position for Group C.
Optional fifth toggle position for Group D.
Rev. 0 | Page 97 of 100
AD9927
Table 61. Field Registers
Address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
Data
Bits
[4:0]
[9:5]
[14:10]
[19:15]
[24:20]
[4:0]
[9:5]
[14:10]
[19:15]
[21:20]
[23:22]
[25:24]
[12:0]
[14:13]
[16:15]
[18:17]
[20:19]
[22:21]
[24:23]
[25]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[23:0]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
Default
Value
X
X
X
X
X
X
X
X
X
Update
Type
VD
VD
X
X
X
X
X
X
X
VD
X
X
X
X
X
X
X
X
X
VD
VD
VD
VD
VD
X
X
VD
X
X
X
X
X
X
X
X
X
X
X
X
X
VD
VD
VD
VD
VD
VD
VD
Name
SEQ0
SEQ1
SEQ2
SEQ3
SEQ4
SEQ5
SEQ6
SEQ7
SEQ8
MULT_SWEEP0
MULT_SWEEP1
MULT_SWEEP2
HDLASTLEN
MULT_SWEEP3
MULT_SWEEP4
MULT_SWEEP5
MULT_SWEEP6
MULT_SWEEP7
MULT_SWEEP8
HDLASTLEN_13
SCP0
SCP1
SCP2
SCP3
SCP4
SCP5
SCP6
SCP7
SCP8
VDLEN
SGACTLINE1
SGACTLINE2
SGMASK
CLPMASKSTART1
CLPMASKEND1
CLPMASKSTART2
CLPMASKEND2
CLPMASKSTART3
CLPMASKEND3
PBLKMASKSTART1
PBLKMASKEND1
PBLKMASKSTART2
PBLKMASKEND2
PBLKMASKSTART3
PBLKMASKEND3
Description
Selected V-sequence for first region in the field.
Selected V-sequence for second region in the field.
Selected V-sequence for third region in the field.
Selected V-sequence for fourth region in the field.
Selected V-sequence for fifth region in the field.
Selected V-sequence for sixth region in the field.
Selected V-sequence for seventh region in the field.
Selected V-sequence for eighth region in the field.
Selected V-sequence for ninth region in the field.
Enables multiplier mode and/or sweep mode for Region 0.
0: multiplier off/sweep off; 1: multiplier off/sweep on;
2: multiplier on/sweep off; 3: multiplier on/sweep on.
Enables multiplier mode and/or sweep mode for Region 2.
Enables multiplier mode and/or sweep mode for Region 1.
HD last line length. Line length of last line in the field.
Enables multiplier mode and/or sweep mode for Region 3.
Enables multiplier mode and/or sweep mode for Region 4.
Enables multiplier mode and/or sweep mode for Region 5.
Enables multiplier mode and/or sweep mode for Region 6.
Enables multiplier mode and/or sweep mode for Region 7.
Enables multiplier mode and/or sweep mode for Region 8.
HD last line length Bit [13] when 14-bit H-counter is enabled.
V-Sequence Change Position 0.
V-Sequence Change Position 1.
V-Sequence Change Position 2.
V-Sequence Change Position 3.
V-Sequence Change Position 4.
V-Sequence Change Position 5.
V-Sequence Change Position 6.
V-Sequence Change Position 7.
V-Sequence Change Position 8.
VD field length (number of lines in the field).
SG Active Line 1.
SG Active Line 2 (set to SG Active Line 1 or maximum if not
used).
Masking of VSG outputs during SG active line.
CLPOB Mask Region 1 start position. Set to 8191 to disable.
CLPOB Mask Region 1 end position. Set to 0 to disable.
CLPOB Mask Region 2 start position. Set to 8191 to disable.
CLPOB Mask Region 2 end position. Set to 0 to disable.
CLPOB Mask Region 3 start position. Set to 8191 to disable.
CLPOB Mask Region 3 end position. Set to 0 to disable.
PBLK Mask Region 1 start position. Set to 8191 to disable.
PBLK Mask Region 1 end position. Set to 0 to disable.
PBLK Mask Region 2 start position. Set to 8191 to disable.
PBLK Mask Region 2 end position. Set to 0 to disable.
PBLK Mask Region 3 start position. Set to 8191 to disable.
PBLK Mask Region 3 end position. Set to 0 to disable.
Rev. 0 | Page 98 of 100
AD9927
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
9.10
9.00 SQ
8.90
12 11 10 9 8 7 6 5 4 3 2 1
BALL A1
PAD CORNER
TOP VIEW
A
B
C
D
E
F
G
H
J
K
L
M
7.15
BSC SQ
0.65 BSC
DETAIL A
*1.40 MAX
DETAILA
0.65 MIN
0.15 MIN
0.45
0.40
0.35
BALL DIAMETER
SEATING
PLANE
COPLANARITY
0.10
*COMPLIANT TO JEDEC STANDARDS MO-225
WITH THE EXCEPTION OF PACKAGE HEIGHT.
Figure 102. 128-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
9 mm × 9 mm Body
(BC-128)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9927BBCZ 1
AD9927BBCZRL1
1
Temperature Range
–25°C to +85°C
–25°C to +85°C
Package Description
128-Lead CSP_BGA
128-Lead CSP_BGA
Z = Pb-free part.
Rev. 0 | Page 99 of 100
Package Option
BC-128
BC-128
AD9927
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05892-0-1/06(0)
Rev. 0 | Page 100 of 100